KR20040016679A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to sufficiently guarantee specification of a resistor even if the area occupied by a unit cell is reduced by a miniaturized line width caused by high integration of the device. CONSTITUTION: An isolation layer(110) is formed on a semiconductor substrate(100) to define a device formation region in a cell region(C) and a peripheral circuit region(P). A gate insulation layer(121), a gate conductive layer(123) and a mask insulation layer(125) are sequentially formed in the device formation region to form a gate(120). A source/drain(105a,105b) is formed at both sides of the gate. The first interlayer dielectric(130) is formed on the substrate. A contact pad(140) connected to the source/drain is formed in the first interlayer dielectric. The second interlayer dielectric(150) is formed on the substrate. A bitline contact is formed in the second interlayer dielectric and a bitline(160) is formed. The third interlayer dielectric(170) is formed on the bitline. A storage node contact is formed in the third and second interlayer dielectrics in the cell region. A resistor pattern is formed in the third and second interlayer dielectrics in the peripheral circuit region. A filling conductive layer is formed on the substrate. The filling conductive layer is evenly eliminated to the upper portion of the third interlayer dielectric to form a storage node contact fill and a resistor(190). A capacitor(210) is formed on the storage node contact fill. A connector for connecting the resistor is formed on the resistor to complete a resistor element.

Description

Method for manufacturing semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a resistor that is one of the components of a semiconductor device.

Generally, a semiconductor device consists of a transistor, a capacitor, a resistor, etc. according to the use of a device. In particular, among static random access memories (SRAM) and logic devices (LOGIC Devices), resistance is often formed in the peripheral circuit area using a resistor as an essential element.

In the method of forming the resistor, the resistor is formed during the gate forming process or the bit line and capacitor forming process in which the conductive polysilicon is formed by pattern among the processes for forming the semiconductor device. That is, in the cell region, when the gate is formed, in the peripheral circuit region, a predetermined resistance pattern is formed to form a resistor. It is formed through the process of forming a predetermined pattern on the doped polysilicon (doped poly-silicon). That is, any one of the above pattern processes is selected to form a predetermined resistance pattern formed of polysilicon in the peripheral circuit region.

Thus, as shown in Fig. 7, conductive polysilicon formed in a plurality of rods on a single plane forms a resistor disposed at a predetermined distance. The polysilicon resistor formed as a single layer has a narrow unit length as the device becomes extremely fine, making it difficult to secure a sufficient sheet resistance value.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of sufficiently securing a specification of resistance even if the area occupied per unit cell decreases due to the miniaturization of the line width due to the high integration of the device.

1 is a cross-sectional view of a semiconductor device manufactured by the present invention.

2 to 5 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device of the present invention.

Figure 6 is a perspective view showing three-dimensional resistance completed by the present invention.

7 is a perspective view three-dimensionally showing the resistance according to the prior art.

In order to achieve the above technical problem, the method of manufacturing a semiconductor device of the present invention first defines an element formation region of a cell region and a peripheral circuit region by forming an insulating film for element isolation on a semiconductor substrate. A gate insulating film, a gate conductive film, and a mask insulating film are sequentially formed in the element formation region to form a gate. After the source and the drain are formed on both sides through the gate, a first interlayer insulating film is formed on the entire surface of the semiconductor substrate, and a contact pad connected to the source and the drain is formed on the first interlayer insulating film. After the second interlayer insulating film is formed over the entire semiconductor substrate, bit line contacts are formed on the second interlayer insulating film to form bit lines. After the third interlayer insulating film is formed on the bit line, a contact for the storage node is formed in the third interlayer insulating film and the second interlayer insulating film in the cell region, and the resistance pattern is formed in the third interlayer insulating film and the second interlayer insulating film in the peripheral circuit area. To form. A filling conductive film is formed over the entire semiconductor substrate, and the filling conductive film is removed evenly to the upper level of the third interlayer insulating film to form a contact fill and a resistance. A capacitor is formed on the contact fill, and a connector for resistance connection is formed on the resistor to complete the resistor.

Here, in the method of forming the element isolation insulating film, a mask insulating film is formed on a semiconductor substrate, and a trench pattern is formed in the mask insulating film. A trench is formed in the semiconductor substrate by a dry etching method using the patterned insulating film for a mask as a mask. A trench filling insulating film is formed on the entire surface of the semiconductor substrate to fill the trench, and the trench filling insulating film is removed evenly to the upper level of the mask insulating film, so that the filling insulating film remains only inside the trench. The insulating film for mask separation is completed by removing the mask insulating film, and the device formation region is defined.

In the forming of the contact pad, a contact for the contact pad is formed using a predetermined self-aligning method, and the contact pad is formed of conductive polysilicon.

In the forming of the bit line, a bit line contact is formed on the contact pad connected to the drain in the second interlayer insulating layer through a photo and dry etching process, and a bit line conductive film is formed on the entire surface of the semiconductor substrate. Then, a bit line is formed through a predetermined photo and dry etching process. Here, the bit line conductive film is preferably a polyside film in which conductive polysilicon and a metal silicide film are sequentially stacked.

In step f), a third interlayer insulating film is formed on the entire surface of the semiconductor substrate. The storage node contacts are formed on the contact pads connected to the source in the third interlayer insulating film and the second interlayer insulating film through predetermined photo and dry etching processes, and a resistance pattern is formed in the peripheral circuit region. After the contact filling conductive film is formed on the entire surface of the semiconductor substrate, the contact filling conductive film is removed evenly to the upper level of the third interlayer insulating film by using a predetermined flattening process to form a contact fill in the cell region and a resistance in the peripheral circuit region. To form. In this case, the third interlayer insulating film is a silicon oxide film formed by chemical vapor deposition. In the resistance pattern, a plurality of rectangular parallelepipeds are formed adjacent to each other. In addition, it is preferable that the conductive film for contact filling is polysilicon doped with impurities formed by chemical vapor deposition because it can be easily removed in the planarization process. The planarization process is preferably a planarization process by chemical vapor deposition because the conductive film for filling a contact can be flat and easily removed without damaging the semiconductor substrate.

In the step of forming the capacitor, an insulating film for a pattern is formed on the entire surface of the semiconductor substrate, and a pattern for the storage electrode is formed on the insulating film for the pattern. The conductive film for the storage electrode and the silicon insulating film are sequentially formed on the entire surface of the semiconductor substrate. The silicon insulating film and the conductive film for the storage electrode are removed evenly to the upper level of the pattern insulating film by using chemical mechanical polishing. The silicon insulating film and the pattern insulating film are removed using a predetermined etching method to form a storage electrode. A dielectric is then formed on the surface of the storage electrode, exposing the top of the resistance of the peripheral circuit area. A conductive film for a plate electrode is formed on the surface of the semiconductor substrate, and a plate electrode and a connector for resistance connection are formed through a predetermined photo and dry etching process. Here, the insulating film for a pattern is a silicon oxide film formed by chemical vapor deposition, and the conductive film for a strip electrode and the conductive film for a plate electrode are polysilicon doped with an impurity. The silicon insulating film is formed of a silicon oxide film formed by chemical vapor deposition and can be easily removed later by a predetermined etching method.

Since the etching method used to remove the pattern insulating film and the silicon insulating film is to add a silicon oxide film, it is preferable to use wet etching using an oxide film etching solution.

The connector for resistance connection may connect the upper portions of the resistors laterally to form independently separated resistors as one unit resistor.

As described above, the semiconductor manufacturing apparatus of the present invention can configure the shape of the resistor in three dimensions so that the resistance area can be increased in the height direction, and a resistor having the same sheet resistance can be formed in a smaller area. In addition, since the resistor of the present invention only needs to deform the photomask for the pattern in the existing process, there is an advantage that the resistor can be easily manufactured without additional cost.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; However, embodiments of the present invention illustrated below may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art.

1 is a cross-sectional view of a semiconductor device manufactured according to the present invention, and FIGS. 2 to 5 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to this, in the semiconductor device manufactured according to the present invention, the insulating layer for device isolation 110 formed to separate the cell region C and the peripheral circuit region P on the semiconductor substrate 100 to define an element formation region. Is formed. In the device formation region, the gate insulating layer 121, the gate conductive layer 123, and the mask insulating layer 125 are sequentially stacked, and the gate 120 having the insulating layer spacer 127 is formed on sidewalls of the layers 123 and 125. have. Source 105a and drain 105b are formed on both sides of the gate 120, and the first interlayer is interposed between the first and second interlayer insulating films 130 and 150 between the silicon of the semiconductor substrate 100. And a bit line 160 connected to the drain 105b through a contact pad 140 formed on the insulating layer 130 and a contact (not shown) of the second interlayer insulating layer 150. Contact pads 140 sequentially formed on the first, second, and third interlayer insulating layers 130, 150, and 170 between the silicon substrates of the semiconductor substrate 100 through the first, second, and third interlayer insulating layers 130, 150, and 170. And a capacitor 210 connected to the source 105a through the contact pen 180. In the peripheral circuit region P, a resistor 191 formed at the same time as the contact fill 180 is formed in the cell region C and a capacitor 210 formed at the same time as the capacitor 210 of the cell region C are formed. And a resistor 190 having a connector 193. Here, reference numeral 220 denotes a fourth interlayer insulating film formed of a silicon oxide film, 230 denotes a metal wiring, and 240 denotes a fifth interlayer insulating film formed of a silicon insulating film.

2 to 5 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 2, the isolation layer 110 for device isolation may be formed on the semiconductor substrate 100 to partition the cell region C and the peripheral circuit region P and define the device formation region thereof. In this case, the device isolation insulating layer 110 is formed using a LOCOS technique or a trench isolation technique. As devices become more integrated, they typically use trench techniques.

That is, a mask insulating film (not shown) is formed on the semiconductor substrate 100, and a trench pattern is formed on the mask insulating film through a patterning process using a predetermined photo and dry etching process. The patterned mask insulating film is used as a mask to form a trench having a predetermined depth (same space as the insulating film for isolation 110) in the semiconductor substrate by a dry etching method. Then, a trench filling insulating film (not shown) is deposited on the entire surface of the semiconductor substrate 100 using chemical vapor deposition, and a trench filling insulating film is masked using chemical mechanical polishing. The upper portion is removed to leave the trench filling insulating layer only inside the trench. Thereafter, the mask insulating film is removed by a wet etching method to complete the device isolation insulating film 110.

The gate insulating layer 121 is formed on the element formation region where the known silicon is exposed on the semiconductor substrate 100 in which the element formation region is defined, and the gate conductive layer 123 and the mask insulating layer 125 are sequentially formed thereon. . The gate pattern is formed on the gate conductive layer 123 and the mask insulating layer 125 through a predetermined photo and dry etching process. Next, an insulating film for spacers (not shown) is formed on the entire surface of the semiconductor substrate 100, and the insulating film spacers 127 are formed on sidewalls of the gate conductive film 123 and the mask insulating film 125 that are patterned by a front surface etching using dry etching. To form. Then, the gate 120 is completed in the cell region C and the peripheral circuit region P on the semiconductor substrate 100. Source and drain junctions 105a and 105b are formed on both sides of the semiconductor substrate 100 through the gate 120 by ion implantation using the completed gate 120 as a mask. . At this time, the source and drain junctions 105a and 105b are separately formed into a PMOS region and an NMOS region by using a predetermined photo process.

Thereafter, a first interlayer insulating film 130 is formed on the entire surface of the semiconductor substrate 100, and a pad contact (the same as a contact pad) for connecting the source and drain junctions 105a and 105b to the first interlayer insulating film 130. Space). Here, the first interlayer insulating film 130 is a silicon oxide film formed by chemical vapor deposition. In this case, the pad contact may be formed by a self aligned contact formation by forming a predetermined self-aligning pattern on the first interlayer insulating layer 130. Next, a pad conductive film (not shown) is formed on the entire surface of the semiconductor substrate 100, and the pad conductive film is formed by using a predetermined flat method such as chemical mechanical polishing. The contact pad 140 may be formed to be flat to the upper level of the pad contact to fill the pad contact with the conductive film.

The planarized second interlayer insulating film 150 is formed on the entire surface of the semiconductor substrate 100, and drain junctions are formed among the contact pads 140 already formed on the second interlayer insulating film 150 using a predetermined photo and dry etching method. Bit line contacts are formed on the contact pads 140 connected to 105b). Then, the polysilicon 161 and the metal silicide film 163 doped with impurities are sequentially formed as the conductive film for the bit line. The second interlayer insulating film 150 is a silicon oxide film formed by chemical vapor deposition, and particularly, plasma enhanced chemical vapor deposition using plasma having high deposition rate and good pattern filling property is preferable.

The bit line 160 is formed by forming a bit line pattern on the bit line conductive film formed through the photo and dry etching process. The planarized third interlayer insulating layer 170 is formed on the entire surface of the semiconductor substrate 100 on which the bit lines 160 are formed. The third interlayer insulating film 170 is a silicon oxide film formed by chemical vapor deposition, and it is preferable to use plasma enhanced chemical vapor deposition using plasma.

Referring to FIG. 3, a contact pad 140 connected to a source junction 105a is connected to a third interlayer insulating film 170 and a second interlayer insulating film 150 in a cell region C through a predetermined photo and dry etching process. The storage node contact 180a is formed on the peripheral circuit region, and a separate resistance pattern 190a is simultaneously formed on the third and second interlayer insulating layers 170 and 150 in the peripheral circuit region P.

That is, a photoresist (not shown) is formed on the third interlayer insulating layer 170, and a storage node contact (not shown) and a resistance pattern (not shown) are formed in the photoresist using a predetermined alignment exposure. At this time, in the photomask used for alignment exposure during the photo process, a storage node contact pattern is formed in the cell region C, and a resistance pattern is formed in the peripheral circuit region P. The dog's pattern can be transferred. Then, using the patterned photoresist as a mask, a dry etching method is formed on the third interlayer insulating film 170 and the second interlayer insulating film 150, and the storage node contact 180a is formed in the cell region C. In the peripheral circuit region P, a resistance pattern 190a is formed. In this case, a contact pad 140 formed under the storage node contact 180a may be used as the etching stop layer. During the etching process, the contact pad 140 of the cell region C is etched to obtain an etch end point based on the etch stop layer, so that the contact 180a for the storage node is formed on the first interlayer insulating layer 130. ) Up to the upper level. However, in the peripheral circuit region P without the etch stop layer, the resistance pattern 190a may be formed to extend to a predetermined depth of the first interlayer insulating layer 130 formed continuously below.

Referring to FIG. 4, a contact filling conductive film (not shown) is formed on the entire surface of the semiconductor substrate 100, and the contact filling conductive film is removed to the level of the third interlayer insulating layer 170 using a planarization process. Then, the contact fill 180 is formed in the cell region C, and the resistor 191 is formed in the peripheral circuit region P. In this case, the conductive film for contact filling is conductive poly-silicon formed by chemical vapor deposition, and is doped with impurities such as phosphorus (P). As the planarization process, chemical mechanical polishing is effective for high film removal rate and good flatness.

Referring to FIG. 5, in the cell region C, a capacitor 210 is formed on the surface of the contact fill 180, and the resistor 191 is connected to the peripheral circuit region P so as to be interconnected thereon. The connector 193 is formed.

That is, a pattern insulating film (not shown) is formed on the entire surface of the semiconductor substrate 100, and a storage node pattern (not shown) is formed to expose the upper portion of the contact fill 180 in the cell region C through a predetermined patterning process. do. Here, the insulating film for a pattern is a silicon oxide film formed by chemical vapor deposition. The conductive layer (not shown) and the filling silicon insulating layer (not shown) for the storage node are sequentially formed on the entire surface of the semiconductor substrate 100 to completely fill the inside of the storage node pattern. At this time, the conductive layer for the storage node is formed by chemical vapor deposition (Chemical vapor deposition) (doped poly-silicon) doped with conductive impurities, the filling silicon insulating film is a silicon oxide film formed by the chemical vapor deposition method.

Thereafter, the filling silicon insulating layer and the storage node conductive layer are evenly removed to the upper level of the pattern insulating layer using chemical mechanical polishing to separate the storage node 211. The storage electrode 211 is completed by removing both the pattern insulating film and the filling silicon insulating film by a wet etching method using an oxide film etching solution to expose the inner and outer surfaces of the storage node.

The dielectric 213 is formed on the surface of the storage electrode 211, and predetermined patterning is performed to expose the upper portion of the resistance 191 of the peripheral circuit region P through a process and a wet etching process. A conductive film for a plate electrode (not shown) is formed on the entire surface of the semiconductor substrate 100, and a predetermined patterning process is performed to form a plate electrode 215 in the cell region C to complete the capacitor 210. In the circuit region P, a resistor 193 is formed to interconnect the resistors 191 formed at the bottom thereof, thereby completing the resistor 190.

Subsequent processes apply a manufacturing process of a conventional semiconductor device to form a metal wiring (230 of FIG. 1) through a metal wiring process, and a passivation film (not shown) using a passivation film forming process to form a product. Complete

As described above, in the method of manufacturing the semiconductor device according to the present invention, the resistor 190 formed in the peripheral circuit region P is formed in the height direction while the contact fill forming process and the capacitor forming process of the cell region C are performed. Since it is extended and formed three-dimensionally, the area required per unit resistance can be reduced and can be easily applied to a highly integrated semiconductor device. In addition, since only the pattern of the photomask needs to be changed in the existing process, there is almost no basic process change, thereby reducing additional costs.

6 is a perspective view showing the resistance of the semiconductor device of the present invention.

Referring to this, a plurality of resistors 191 having a rectangular parallelepiped shape on a plate having a high height are disposed adjacent to each other in the peripheral circuit region P of FIG. A bar type resistance connector 193 is formed to alternately connect 191. Thus, the volume constituting the resistor 190 can be expanded not only in the horizontal and vertical area directions but also in the height direction, so that the resistor 190 having various specifications and shapes can be manufactured in the same area. In addition, the manufacturing method of the semiconductor device of the present invention can form the same resistor 190 in a smaller area compared with the resistor 1190 manufactured by the conventional technique of FIG.

Meanwhile, in the method of manufacturing the semiconductor device of the present invention, when the resistance pattern 190a is formed during the process of forming the contact fill 180 of FIG. 3, the second interlayer insulating film 150 and the third interlayer insulating film 170 are formed. A separate etch stop layer such as a polysilicon film or a silicon nitride film may be further included therebetween. Then, the depth of the resistance pattern 190a formed in the peripheral circuit region P is formed to be relatively constant, which has the advantage of forming a more uniform resistance.

As described above, in the method of manufacturing a semiconductor device according to the present invention, a resistance formed in a peripheral circuit region may be three-dimensionally formed to form a resistor in a smaller area, and a resistor having various specs is formed in the same area. can do.

In addition, since only the photo mask used in the photo process is changed in the existing process, various types of resistors may be formed without additional costs.

Claims (16)

a) forming a device isolation insulating film on a semiconductor substrate to define a device formation region of a cell region and a peripheral circuit region; b) forming a gate by sequentially forming a gate insulating film, a gate conductive film, and a mask insulating film in an element formation region; c) forming a source and a drain on both sides via the gate; d) forming a first interlayer insulating film on the entire surface of the semiconductor substrate, and forming a contact pad connected to the source and the drain on the first interlayer insulating film; e) forming a second interlayer insulating film on the entire surface of the semiconductor substrate, and then forming a bit line contact on the second interlayer insulating film and forming a bit line; f) forming a third interlayer insulating film on said bit line, and forming a contact for a storage node in said third interlayer insulating film and said second interlayer insulating film in said cell region, and said third interlayer insulating film in said peripheral circuit region And forming a resistance pattern on the second interlayer insulating film; g) forming a filling conductive film on the entire surface of the semiconductor substrate, and removing the filling conductive film evenly to an upper portion of the third interlayer insulating film to form a contact node for a storage node and a resistor; h) forming a capacitor on the contact node for the storage node, and forming a resistor connecting connector on the resistor to complete the resistor. The method of claim 1, wherein step a) comprises: Forming an insulating film for a mask on the semiconductor substrate; Forming a trench pattern in the mask insulating film; Forming a trench in the semiconductor substrate by a dry etching method using the patterned insulating film for a mask as a mask; Filling the trench by forming an insulating film for filling the trench in an entire surface of the semiconductor substrate; Removing the trench filling insulating layer evenly to the upper level of the mask insulating layer to leave the filling insulating layer only in the trench; And And removing the insulating film for the mask. The method of claim 1, wherein in the step d), the contact pad is formed of conductive polysilicon. The method of claim 1, wherein step e) Forming a bit line contact connected to the contact pad on the second interlayer insulating layer through a photo and dry etching process; Forming a bit line conductive film on the entire surface of the semiconductor substrate; And Forming a bit line through a predetermined photo and a dry etching process. The method of manufacturing a semiconductor device according to claim 4, wherein the bit line conductive film is a polyside film in which conductive polysilicon and a metal silicide film are sequentially stacked. The method of claim 1, wherein f) is Forming a third interlayer insulating film on the entire surface of the semiconductor substrate; Forming a contact for a storage node on the contact pad connected to the source to the third interlayer insulating layer and the thinner second interlayer insulating layer through a predetermined photo and dry etching process, and forming a resistance pattern in a peripheral circuit region; Forming a contact filling conductive film on the entire surface of the semiconductor substrate; And And removing the contact filling conductive film evenly to an upper level of the third interlayer insulating film using a predetermined planarization process. 7. The method of claim 6, wherein the third interlayer insulating film is a silicon oxide film formed by chemical vapor deposition. The method of manufacturing a semiconductor device according to claim 6, wherein the resistance pattern has a plurality of rectangular parallelepipeds formed adjacent to each other. The method of claim 6, wherein the contact filling conductive film is polysilicon doped with impurities formed by chemical vapor deposition. The method of claim 6, wherein the planarization process is a planarization process by chemical vapor deposition. The method of claim 1, wherein h), Forming an insulating film for a pattern on the entire surface of the semiconductor substrate; Forming a storage electrode pattern on the pattern insulating layer; Sequentially forming a conductive electrode for a storage electrode and a filling silicon insulating film on the entire surface of the semiconductor substrate; Removing the filling silicon insulating layer and the storage electrode conductive layer evenly to the upper level of the pattern insulating layer by chemical mechanical polishing; And Forming a storage electrode by removing the filling silicon insulating layer and the pattern insulating layer by a predetermined etching method; Forming a dielectric on the storage electrode surface; Exposing an upper portion of the resistor in the peripheral circuit area; Forming a conductive film for a plate electrode on a surface of the semiconductor substrate; And And forming a plate electrode and the connector for resistance connection through a predetermined photo and dry etching process. The method of claim 11, wherein the pattern insulating film is a silicon oxide film formed by chemical vapor deposition. The method of claim 11, wherein the storage electrode conductive film and the plate electrode conductive film are polysilicon doped with impurities. The method of manufacturing a semiconductor device according to claim 11, wherein the filling silicon insulating film is a silicon oxide film formed by chemical vapor deposition. The method of claim 11, wherein the etching method is a wet etching method using an oxide film etching solution. The method of claim 6, wherein the connector for resistance connection connects an upper portion of the resistor.