KR20040016662A - Liquid crystal display and gate driving apparatus of a display device - Google Patents

Abstract

PURPOSE: An LCD and a gate driving device for a display system are provided to drop a gate-on voltage by a line resistance between gate driving ICs for making all final gate-on voltage applied to the respective gate driving ICs almost equal, thereby improving the screen quality of an LCD. CONSTITUTION: A gate driving device for an LCD includes a sequence information distinguish part(901), a voltage generating part(902) and a voltage selecting part(903). The voltage generating part generates a plurality of voltages on the bases of a gate-on voltage(Von) of a driving voltage generating part. The sequence information distinguish part distinguishes sequence information signals(SISs) informing the sequences of gate-on voltage supply for gate driving ICs to generate corresponding signals. The voltage selecting part selects one of the plurality of voltages generated from the voltage generating part according to the signals output from the sequence information distinguish part.

Description

Liquid crystal display and gate drive device for display device {LIQUID CRYSTAL DISPLAY AND GATE DRIVING APPARATUS OF A DISPLAY DEVICE}

The present invention relates to a liquid crystal display device and a drive device thereof.

A general liquid crystal display (LCD) includes a liquid crystal layer having dielectric anisotropy interposed between two display panels. The desired image is obtained by applying an electric field to the liquid crystal layer and adjusting the intensity of the electric field to adjust the transmittance of light passing through the liquid crystal layer. Such liquid crystal displays are typical among portable flat panel displays (FPDs) that are easy to carry. Among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

In the display panel on which the thin film transistor is formed, a plurality of gate lines and data lines are formed in row and column directions, respectively, and pixel electrodes connected to the gate lines and data lines are formed through the thin film transistors. The thin film transistor controls the data signal transmitted through the data line according to the gate signal transmitted through the gate line and transmits the data signal to the pixel electrode. The gate signal is generated by combining a plurality of gate driving integrated circuits (ICs) receiving the gate on voltage and the gate off voltage generated by the driving voltage generator according to control from the signal controller. The data signal is obtained by converting the gradation signal from the signal controller into a plurality of data driving ICs into analog voltages. The signal controller and driving voltage generator are usually provided on a printed circuit board (PCB) located outside the display panel, and the driving IC is a flexible printed circuit (FPC) located between the PCB and the liquid crystal panel assembly. It is mounted on a substrate. Two PCBs are usually placed in this case, one above and one left of the liquid crystal panel assembly, and the left one is called a gate PCB and the right one is called a data PCB. A gate driver IC is positioned between the gate PCB and the display panel, and a data driver IC is positioned between the data PCB and the display panel, and receives signals from the corresponding PCB.

However, instead of using a gate PCB, only a data PCB can be used. In this case, the gate-side FPC substrate and the gate driver IC thereon may be left as it is. In this case, in order to transfer signals from the signal controller and the driving voltage generator located in the data PCB to all the gate driver ICs, wires are separately formed on the data FPC board and the display panel. Wiring is also made on the gate FPC board so that signals can be passed to the next gate driver IC.

As such, the signal on the PCB, in particular, the gate-on voltage generated by the driving voltage generator, moves back and forth between the gate FPC substrate and the display panel and is transmitted to the gate driving IC, so that the entire signal path is long and the gate-on voltage supplied to the last gate driving IC is The state is much lower than the original voltage. As a result, the gate-on voltage applied to the gate line connected to the gate driver IC is drastically decreased, so that the gate-on voltage value difference between the gate driver ICs is greatly increased.

The technical problem to be achieved by the present invention is to reduce the gate-on voltage difference between the plurality of gate driving ICs to stabilize the operation of the liquid crystal display and to improve image quality.

1 is a conceptual diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a layout view schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a block diagram of a gate on voltage corrector according to an exemplary embodiment of the present invention.

5 is a schematic configuration diagram of a gate-on voltage converter according to an embodiment of the present invention.

6 is an operation timing diagram of a gate on voltage correction unit according to an embodiment of the present invention.

7 is a schematic diagram of a gate-on voltage converter according to another exemplary embodiment of the present invention.

According to one embodiment of the invention, the gate drive device

A gate driving device for a display device that receives a gate-on voltage from an external device.

A voltage generator configured to generate a plurality of voltages having different values based on the input gate on voltage, and

And a voltage selector configured to select one of the plurality of voltages and output the corrected gate-on voltage according to a first control signal from the outside.

The voltage generator includes a plurality of resistors connected in series with the input gate-on voltage, and preferably have the same value.

The voltage generator includes a plurality of resistors connected in parallel to the input gate-on voltage, and the values of the resistors are different from each other.

The first control signal has predetermined information, and the gate driver starts operation according to a second control signal from the outside to identify the information of the first control signal and supply it to the voltage selector. It is preferable to further include an order information identification unit.

The voltage selector may select one of the plurality of voltages based on the information.

The order information identifying unit may include a counter for counting a pulse width of the first control signal.

According to another embodiment of the present invention, a liquid crystal panel assembly comprising a plurality of gate lines, a plurality of data lines, and a switching element connected to one of the gate lines and one of the data lines, respectively.

A gate on voltage signal wire at least partially disposed on the liquid crystal panel assembly and transferring an input gate on voltage to turn on the switching element;

A plurality of gate drivers connected to the gate on voltage signal wires and sequentially supplied with the input gate on voltage through the gate on voltage signal wires;

Including,

At least one of the gate drivers

And a gate on voltage corrector configured to correct the input gate on voltage based on a resistance of the gate on voltage signal wire.

The gate driver may further include a flexible printed circuit board, the gate driver being mounted in the form of a chip on the liquid crystal panel assembly or formed in the liquid crystal panel assembly, and all of the gate-on voltage wirings are formed in the liquid crystal panel assembly. It may be formed on.

The gate on voltage correction unit

A voltage generator configured to generate a plurality of voltages having different values based on the input gate on voltage, and

A voltage selector which selects one of the plurality of voltages according to a value of a first control signal and outputs the corrected gate-on voltage

It includes.

The voltage generator preferably includes a plurality of resistors connected in series with the input gate-on voltage.

The resistance value of each resistor is set to a value within a range of about ± 60% of the resistance value of the gate-on voltage wiring portion located between the gate driver, and the resistance value of the gate-on voltage wiring portion located between the gate driver. The same is good.

Preferably, the voltage generator includes a plurality of resistors connected in parallel to the input gate-on voltage, and the resistance values of the resistors are different from each other.

The difference between the resistance values of the respective resistors is set to a value within a range of ± 60% of the resistance value of the gate-on voltage wiring portion located between the gate drivers, and the resistance of the gate-on voltage wiring portion located between the gate drivers. The same value is good.

The first control signal may include order information of the gate driver, and the gate-on voltage corrector may further include an order information identifier to identify and supply order information of the first control signal to the voltage selector. In this case, the order information is related to the pulse width of the first control signal.

The order information identification unit may include a counter for measuring the pulse width, and the first control signal may be supplied to each gate driver from an external source.

The order information identifying unit starts an operation based on the second control signal.

One of the gate drivers receives the second control signal from the outside, and the other gate driver receives the second control signal from the other gate driver.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

1 is a conceptual diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the liquid crystal display according to the present invention includes a liquid crystal panel assembly 300, a gate driver 400 and a data driver 500 connected thereto. A driving voltage generator 700 connected to the gate driver 400, a gray voltage generator 800 connected to the data driver 500, and a signal controller controlling the driving voltage generator 700. 600).

The liquid crystal panel assembly 300 includes a plurality of signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected thereto in an equivalent circuit, and each pixel includes the signal lines G ₁ -G. _n , D ₁ -D _m ), a switching element Q connected to the liquid crystal capacitor C _lc and a storage capacitor C _st connected thereto. The signal lines G ₁ -G _n , D ₁ -D _m transmit a scanning signal or a gate signal, and the plurality of scanning signal lines or gate lines G ₁ -G _n extending in the row direction. And a data signal line or data line D ₁ -D _m which transmits an image signal or a data signal and extends in the column direction. The switching element Q is a three-terminal element, the control terminal of which is connected to the gate line G ₁ -G _n , the input terminal of which is connected to the data line D ₁ -D _m , and the output terminal of the liquid crystal capacitor ( C _lc ) and one terminal of the holding capacitor C _st .

The liquid crystal capacitor C _lc is connected to the output terminal of the switching element Q and a common voltage V _com or a reference voltage. The other terminal of the holding capacitor C _st is connected to another voltage, for example a reference voltage. However, the other terminal of the holding capacitor C _st may be connected to the gate line directly above (hereinafter referred to as "previous gate line"). The former is called a separate wire type and the latter is called a prior gate type.

Meanwhile, the liquid crystal panel assembly 300 may be schematically illustrated as shown in FIG. 2. For convenience, only one pixel is shown in FIG. 2.

As shown in FIG. 2, the liquid crystal panel assembly 300 includes a lower panel 100 and an upper panel 200 facing each other and a liquid crystal layer 3 therebetween. The lower panel 100 includes gate lines G _i-1 , G _i , a data line D _j , a switching element Q, and a storage capacitor C _st . The liquid crystal capacitor C _lc has two terminals as the pixel electrode 190 of the lower panel 100 and the reference electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270 is It functions as a dielectric.

The pixel electrode 190 is connected to the switching element Q, and the reference electrode 270 is formed on the entire surface of the upper panel 200 and is connected to the common voltage V _com .

Herein, the liquid crystal molecules change their arrangement according to the change of the electric field generated by the pixel electrode 190 and the reference electrode 270, and thus the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

In the pixel electrode 190, a separate wiring to which a reference voltage is applied is provided on the lower panel 100 to overlap the pixel electrode 190 to form the storage capacitor C _st . For the previous gate way form the two terminals of the pixel electrode 190 is maintained with a previous gate line (G _i-1) by being overlapped with the previous gate line (G _i-1), an insulator as a medium capacitor (C _st).

FIG. 2 shows a MOS transistor as an example of the switching element Q, which is implemented as a thin film transistor having amorphous silicon or polysilicon as a channel layer in an actual process.

Unlike in FIG. 2, the reference electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 are linearly formed.

On the other hand, in order to implement color display, each pixel should be able to display color, which is provided by a color filter 230 of red, green, or blue in a region corresponding to the pixel electrode 190. It is possible. The color filter 230 is mainly formed in the corresponding region of the upper panel 200 as shown in FIG. 2, but may be formed above or below the pixel electrode 190 of the lower panel 100.

Referring back to FIG. 1, the driving voltage generator 700 generates a gate on voltage V _on for turning _{on the} switching element Q, a gate off voltage V _off for turning off the switching element Q, and the like. do.

The gray voltage generator 800 generates a plurality of gray voltages related to the luminance of the liquid crystal display.

The gate driver 400, also referred to as a scan driver, is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300, and has a gate-on voltage V from the driving voltage generator 700. _on ) is corrected and a gate signal composed of a combination of the corrected gate on voltage V _on ′ and gate off voltage V _off is applied to the gate lines G ₁ -G _n .

The data driver 500, also referred to as a source driver, is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 to select a gray voltage from the gray voltage generator 800 to select a data signal. Is applied to the data lines D ₁ -D _m .

The signal controller 600 generates a control signal for controlling operations of the gate driver 400, the data driver 500, and the driving voltage generator 700, and outputs a corresponding control signal to the gate driver 400, The data driver 500 and the driving voltage generator 700 are supplied to the data driver 500 and the driving voltage generator 700.

As shown in FIG. 3, the gate driver 400 and the data driver 500 generally include a plurality of gate driver integrated circuits 441-444 and data driver ICs 540. Each IC may exist separately from the liquid crystal panel assembly 300 or may be mounted on the liquid crystal panel assembly 300, and may have the same process as the signal lines G ₁ -G _n , D ₁ -D _m and the thin film transistor Q. The liquid crystal display panel 300 may be formed on the liquid crystal panel assembly 300.

Next, the structure of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIG. 3.

3 is a layout view schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 3, a signal controller 600 for driving a liquid crystal display device is disposed above the liquid crystal panel assembly 300 including the gate lines G ₁ -G _n and the data lines D ₁ -D _m . ), A printed circuit board (PCB) 550 including circuit elements such as the driving voltage generator 700 and the gray voltage generator 800 is located. The liquid crystal panel assembly 300 and the PCB 550 are electrically and physically connected to each other through a data printed circuit (FPC) substrate 510.

The data driver IC 540 is mounted on the data FPC substrate 510, and a plurality of data lead lines 440 and gate driving signal lines 521-524 are formed. The data lead line 440 is connected to the output terminal of the data driver IC 540 and is connected to the data line D ₁ -D _m through the contact portion C2, so that the data line D ₁ -D _m ) to transmit an image signal. Although only four gate driving signal lines 521 to 524 are shown in the figure for convenience, the number thereof is more than five. In this embodiment, the signal line 521 is a signal line for transmitting a gate-on voltage, the signal line 522 transfers a gate-off voltage or a gate clock signal, for example, and the signal line 523 carries a vertical synchronization start signal. do. In addition, the signal line 524 transmits a sequence information signal (SIS) transmitted from the signal controller 600.

The signal lines 521-524 are electrically connected to the circuit elements of the PCB 550, as are the data driver ICs 540.

Four gate driving FPCs 411-414 are attached to the left side of the liquid crystal panel assembly 300, and gate driving ICs 441-444 are mounted on the gate FPC substrates 411-414, respectively. A plurality of gate lead lines 420 and gate driving signal lines 421, 422, 423a, 423b, and 424 are formed on the flexible FPC substrates 411-414. Some signal lines 421, 422, and 424 of the gate driving signal wires 421, 422, 423a, 423b, and 424 are connected to the input terminals of the gate driving ICs 441-444 by outputting branch signal lines, but some other signal lines ( 423a and 423b have a structure in which one end is connected to the gate driving ICs 441-444. Among the other signal lines 423a and 423b, the upper signal line 423a is connected to the input terminal of the gate driving IC 441-444, and the lower signal line 423b is connected to the gate driving IC 441-444. It is connected to the output terminal. Although only five gate driving signal wires 421, 422, 423a, 423b, and 424 are shown in the drawing for convenience, the number may vary.

As shown in FIG. 3, a plurality of pixel regions defined by the intersection of the horizontal gate lines G ₁ -G _n and the vertical data lines D ₁ -D _m provided in the liquid crystal panel assembly 300 are formed. The display area D which collects and displays an image is comprised. The black matrix 220 is provided outside the display area D to block light leaking out of the display area D. The gate lines G ₁ -G _n and the data lines D ₁ -D _m remain substantially parallel in the display area D, respectively. The gaps between each other become narrow and become substantially parallel again.

Gate driving signal lines 321a-321d, 322a-322d, 323a-323d, and 324a-324d are formed at the upper left and left edges of the liquid crystal panel assembly 300 outside the display area D. FIG. The gate drive signal wires 321a, 322a, 323a, and 324a located at the upper left corner are electrically connected to the gate drive signal wires 521, 522, 523, and 524 of the data FPC board 510 through the contact part C4. The gate driving signal wires 421, 422, 423a and 424 of the uppermost gate FPC board 411 are connected via C3. The other gate driving signal wires 321b-321d, 322b-322d, 323b-323d, and 324a-324d are located between the portions _{where the} gate lines G ₁ -G _n are gathered, and are adjacent to each other through the contact parts C5 and C6. Gate driving signal wires 421, 422, 423a, 423b, and 424 of the gate FPC boards 411-414 are connected to each other.

Meanwhile, an FPC substrate (not shown) in which the data driver IC 540 is not mounted in addition to the data FPC substrate 510 may be attached to the PCB 550 and the liquid crystal panel assembly 300, wherein the gate driving signal wiring ( 521-524 may be provided on this FPC substrate.

Here, the gate lines G ₁ -G _n , the data lines D ₁ -D _m , the signal lines 521-524 and the FPC substrate 411-414 of the liquid crystal panel assembly 300 at the contact portions C1-C6. The connection between the lead wires 420 and 440 and the signal lines 321a-321d, 322a-322d, 323a-323d, and 324a-324d of the 510 is performed through an anisotropic conductive film.

According to an embodiment of the present invention, each gate driver IC 441-444 corrects and corrects the gate-on voltage V _on from the driving voltage generator 700 according to a control signal from the signal controller 600. And a gate on voltage corrector 900 for outputting the gate on voltage V _on ′.

At this time, it is preferable that the corrected gate-on voltage (V _on ') value of each gate driver IC 441-444 is as small as possible, particularly the same.

For example, in FIG. 3, the wiring resistance between the first and second gate driver ICs 441 and 442 is r1, and the wiring resistance between the second and third gate driver ICs 442 and 443 is r2, and the third and fourth gate driver ICs 443 and 444. ) as the wiring resistance between r3, and the first, second, and said third and fourth gate drive the gate-on voltage to each V _on1, V _on2, V _on3, V _on4 supplied to the IC (441-444) , let's say the first, second, third, and fourth gate gate-on voltage outputted from the drive IC (441-444) each _{V on1 ', V on2',} V on3 ', V on4'. When both the output voltage of the _{V on1 '= V on2' =} V on3 '= V on4'.

According to an embodiment of the present invention, the last gate driving IC 444 outputs the input gate on voltage V _on4 as it is, and the magnitude of the gate on voltage output from the other gate driving ICs 441-443 is the last gate driving. The output gate on voltage V _on4 ′ of the IC 444 is equal to the magnitude. That _{is, V on1 '= V on2'} = V on3 '= V on4' a = V _on4. However, the wiring resistance (r1, r2, r3), the first, second, third, because it is due to voltage drop is respectively _{(V on1 -V on2), (} V on2 -V on3), (V on3 -V on4) the gate-on voltage correction unit 900 that the size of the gate receiving supply turn-on voltage (V _on1, V _on2, V _on3) wiring resistance [(r1 + r2 + r3) of the gate drive IC (441, 442, 443) , (r2 + r3), thereby r3] voltage drop [(V _on1 -V _on4), each drop _{(V on2 -V on4), (} V on3 -V on4)] as resulting from. That _{is, V on1 '= V on1 -} (V on1 -V on4) = V on4, V on2' = V on2 - (V on2 -V on4) = V on4, V on3 '= V on3 - (V on3 -V _on4 ) = V _on4

The gate-on voltage corrector 900 according to the exemplary embodiment of the present invention illustrated in FIG. 4 generates a plurality of voltages having different values based _on the gate-on voltage V _on from the driving voltage generator 700. A sequence information identification unit 901 for identifying a sequence information signal SIS indicating a sequence of supplying a gate-on voltage to the gate generator ICs 441-444, and generating a corresponding signal; A voltage selector 903 that selects one of a plurality of voltages from the voltage generator 902 and outputs the final gate-on voltage V _on 'according to a signal from the sequence information identification unit 901; have.

As illustrated in FIG. 5, the voltage generator 902 according to an embodiment of the present invention includes a plurality of resistors RG1, RG2, and RG3 connected in series to the gate-on voltage V _on . The voltage generator 902 outputs a plurality of voltages V1, V2, V3, and V4 through a plurality of output terminals out 1 through 4, for example. Two output terminals out1 and out4 are connected to both ends of the resistor strings RG1, RG2 and RG3, and the remaining two output terminals out2 and out3 are connected between the resistors RG1, RG2 and RG3. . Accordingly, the plurality of voltages V1, V2, V3, and V4 output from the voltage selector 903 have a relationship of V1>V2>V3> V4, and each voltage difference is related to the magnitude of the resistors RG1, RG2, and RG3. It depends on.

The value of the resistors RG1, RG2, and RG3 is preferably set to a value in a range of about ± 60% of the value of the wiring resistances r3, r2, and r1 between the gate driving ICs 441 to 444, and in particular, the wiring resistance ( The same value as r3, r2, r1) is good. In addition, the values of the resistors RG1, RG2, and RG3 are preferably the same.

For example, the values of the resistors RG1, RG2, and RG3 are set within the range of -0.6r3 <RG1 <0.6r3, -0.6r2 <RG2 <0.6r2, -0.6r1 <RG3 <0.6r1.

In one embodiment of the present invention, since the signal controller 600 informs the sequence of the gate driving ICs 441-444 by changing the pulse width of the sequence information signal SIS, the sequence information identification unit 901 is a sequence information signal. This counter outputs a count signal obtained by calculating the pulse width of (SIS). For example, the value of the count signal is "1" for the first gate driver IC 441, "2" for the second gate driver IC 442, and "3" for the third gate driver IC 443. And 4 in the case of the fourth gate driving IC 444. However, the value of this counting signal may vary.

The voltage selector 903 includes a multiplexer that selects and outputs one voltage among a plurality of voltages applied from the voltage generator 902 according to the value of the count signal applied from the sequence information identification unit 901. In the above example, the voltage selector 903 is respectively V4, V3, V2 when the value of the count signal of the sequence information identification unit 901 is "1", "2", "3", "4", respectively. Select V1.

Next, the display operation of the liquid crystal display device will be described in more detail.

The signal controller 600 included in the PCB 550 is a control input signal for controlling the RGB data signals R, G, and B and their display from an external graphic controller (not shown). signals, for example, a vertical synchronizing signal (V _sync ), a horizontal synchronizing signal (H _sync ), a main clock (CLK), and a data enable signal (DE). Get a back. The signal controller 600 generates a gate control signal and a data control signal based on the control input signal, processes the gray level signals R, G, and B appropriately according to the operating conditions of the liquid crystal panel assembly 300, and then controls the gate. The signal is sent to the gate driver 400 and the driving voltage generator 700, and the data control signal and the processed gray level signals R ′, G ′, and B ′ are sent to the data driver 500.

The gate control signal controls the output timing of the vertical synchronization start signal (STV) and gate on voltage V _on indicating the start of the output of the gate on voltage V _on (high period of the gate signal). Sequence of gate clock signal CPV, gate on enable signal OE defining the pulse width of gate on voltage V _on and respective gate driving ICs 441-444. An order information signal SIS or the like for identifying the? Among them, the gate-on enable signal OE and the gate clock signal CPV are supplied to the driving voltage generator 700, and the vertical synchronization start signal STV, the gate clock signal CPV, and the sequence information signal SIS are provided. Is supplied to the gate driver 400.

The data control signal includes a horizontal synchronization start signal (STH) indicating the start of input of the gray scale signal, a load signal (load signal, LOAD or TP) for applying a corresponding data voltage to the data line, and a polarity of the data voltage. An inversion control signal RVS and a data clock signal HCLK to invert.

On the other hand, the driving voltage generator 700 according to the gate control signal from the signal controller 550, the gate on voltage (V _on ), the gate off voltage (V _off ) and the common voltage (V) applied to the reference electrode 270 _com ), and supply a gate on voltage V _on and a gate off voltage V _off to the gate driver 400. The gray voltage generator 800 generates a plurality of gray voltages related to the luminance of the liquid crystal display and applies them to the data driver 500.

At this time, among the gate control signals, the gate clock signal CPV, the gate on enable signal OE, and the gate off voltage V _off are connected to the respective gate driving ICs 441 through the signal lines 522, 322a-322d, and 422. The vertical synchronization start signal STV is supplied to the first gate driving IC 441 through the signal lines 523, 323a, and 423a.

The gate-on voltage V _on is supplied to each gate driving IC 441-444 through the signal lines 521 and 321a-321d. In addition, the sequence information signal SIS is supplied in parallel to each gate driving IC 441-444 through the signal lines 524 and 324a to 324d.

The gate driver 400 corrects the gate-on voltage V _on according to the gate control signal from the signal controller 600, and sequentially corrects the gate-on voltage V _on ′ to the gate lines G ₁ -G _n . And turns on the switching element Q of one row connected to this gate line G ₁ -G _n . At the same time, the data driver 500 generates a gray voltage corresponding to the gray signals R ', G', and B 'in the pixel row where the switching element Q is turned on according to the data control signal from the signal controller 600. The gray voltage, which is an analog voltage from the unit 800, is supplied as a data signal to the data lines D ₁ -D _m . The data signal supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q. In this manner, the gate-on voltages V _on 'are sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data signals to all the pixel rows. At this time, if the inversion control signal RVS is supplied after the data signal is applied to the pixels of all rows corresponding to one frame, the polarity of the data signals of all the rows corresponding to the next frame is changed.

With reference to Figures 3 to 6, this operation will be described in more detail.

First, when the gate-on voltage V _on from the driving voltage generator 700 is supplied to the voltage generator 902 included in the gate-on voltage corrector 900 of each gate driving IC 441-444. The voltage generator 902 generates a plurality of voltages V1, V2, V3, and V4 having different magnitudes and supplies the generated voltages to the voltage selector 903 through output terminals out1 to out4.

When the vertical synchronization start signal STV from the signal controller 600 is transmitted to the order information identifying unit 901 of the first gate driver IC 441, the gate-on voltage correction unit of the first gate driver IC 441 ( Operation 900 begins.

At this time, the signal controller 600 simultaneously supplies the first pulse of the sequence information signal SIS having the given pulse width with the vertical synchronization start signal STV. In the example shown in FIG. 6, the first pulse width of the sequence information signal SIS is equal to one period of the gate clock signal CPV.

The sequence information identification unit 901 of the first gate driver IC 441 counts the number of pulses of the gate clock signal CPV while the sequence information signal SIS maintains a high level in synchronization with the vertical synchronization start signal STV. To generate a corresponding count signal and supply it to the voltage selector 903. At this time, the order information signal SIS is also supplied to the gate-on voltage correction unit 900 of the other gate driving ICs 442-444 but does not operate because the vertical synchronization start signal STV or the carry signal is not supplied.

Then, the voltage selector 903 selects one voltage from the plurality of voltages V1, V2, V3, V4 of the voltage generator 902 according to the value of the count signal from the sequence information identification unit 901. The first gate line G ₁ of the liquid crystal panel assembly 300 is supplied as a final corrected gate on voltage V _on ′. At this time, the gate-off voltage V _off is applied to the other gate lines G ₂ -G _n .

The switching element Q of the first row connected to the first gate line G ₁ is conducted by the gate-on voltage V _on ', and the data signal of the first row is transferred through the switching element Q of the first row. It is applied to the liquid crystal capacitor C _lc and the sustain capacitor C _st of the pixels in the first row. After a certain period of time, when the charging of the capacitors C _lc and C _st of the pixels in the first row is completed, the first gate driving IC 441 applies the gate-off voltage V _off to the first gate line G ₁ . The connected switching element Q is turned off and the gate-on voltage V _on ′ from the voltage selector 903 is applied to the second gate line G ₂ .

The first gate driver IC 441 applying the gate-on voltage V _on ′ at least once to all the gate lines connected in this manner generates a carry signal indicating that the scan is completed to generate the signal lines 423b, 323b, and 423a. The gate-on voltage corrector 900 of the second gate driver IC 442 starts operation by providing the gate driver IC 442 to the second gate driver IC 442.

At this time, the signal controller 600 supplies the second pulse of the sequence information signal SIS to the second gate driving IC 442 in accordance with the carry signal.

As described above, whenever one gate driving IC completes the scan operation, a carry signal is transmitted to the next gate driving IC, and according to the carry signal, the signal controller 600 drives the corresponding pulse of the sequence information signal SIS according to the carry signal. Supply to IC 441-444. The signal controller 600 changes the pulse width of the sequence information signal SIS according to the order of the corresponding gate driving IC 441-444 whenever the vertical synchronization start signal STV is generated or the carry signal is generated. In the example of FIG. 6, the first pulse has a pulse width corresponding to one period of the gate clock signal CPV, and each subsequent pulse has a pulse width increased by one period of the gate clock signal than the previous pulse width. Therefore, the coefficient value of the sequence information identification unit 901 is "1" for the first gate driving IC 441, the second is "2", the third is "3", and the last fourth is "4". , so that the voltage selection section 903, respectively V4, V3, V2, select V1 and the corrected gate-on voltage (V _on1 'V _on2', V _on3 ', V _on4') as an output, and a voltage (V _on ') Is applied to the corresponding gate line. When the last gate driver IC 444 completes this operation, the scan operation for one frame is completed.

As described above, the gate-on voltage correction unit 900 of the gate driving IC which receives the vertical synchronization start signal STV or the carry signal among the plurality of gate driving ICs 441-444 operates, and the sequence information identifying unit 901 is operated. Based on the coefficient signal value of, the corresponding voltage among the plurality of voltages V1, V2, V3, and V4 is supplied to the corresponding gate line as the corrected gate-on voltage V _on ′. At this time, the voltage selection takes into account the wiring resistances r1, r2, and r3 between the gate driving ICs 441-444.

Therefore, even if different gate-on voltages V _on are applied to each gate driver IC 441-444 due to the wiring resistance, the values of the final gate-on voltages V _on 'applied to the respective gate lines are almost the same. .

In the present exemplary embodiment, the signal controller 600 generates and supplies the sequence information signal SIS, but the signal controller 600 gives the first pulse only to the first gate driver IC 441 and in each gate driver IC. There may be a method of generating a pulse having a larger pulse width than the input pulse and supplying it to the next gate driving IC. It is also possible to change the pulse width of the carry signal instead of generating pulses separately.

Next, the voltage generator 9021 according to another embodiment of the present invention will be described with reference to FIG. 7.

The voltage generator 9021 includes a plurality of resistors R1, R2, and R3 connected in parallel to the gate-on voltage V _on , and has a relationship of R1 <R2 <R3. The voltage generator 9021 has a plurality, for example, four output terminals out 1 -out 4, and the output terminals out 1 -out 4 in turn turn on the gate-on voltage V _on and the resistors R 1, R 2, and R 3. Is connected to the end and outputs the corresponding voltage (V1, V2, V3, V4). The resistance value difference of each resistor is preferably set to a value in the range of ± 60% of the wiring resistance value between the gate driving ICs 441-444, and particularly preferably the same as the wiring resistance value. For example, the values of the resistors R1, R2, and R3 are -0.6r3≤R1≤0.6r3, -0.6 (r2 + r3) ≤R2≤0.6 (r2 + r3), -0.6 (r1 + r2 + r3) ≤ R3 ≤ 0.6 (r1 + r2 + r3).

In the above-described embodiment, only the case where the gate driver IC 441-444 is mounted on the gate FPC substrates 411-414 has been described. However, the gate driver IC is directly mounted on the liquid crystal panel assembly 300 in the form of a chip. Even when directly formed, the present invention can be applied. In this case, since there are no gate FPC substrates 411-414, all of the gate driving signal lines that transfer the gate- _on voltage V _on are formed in the liquid crystal panel assembly 300.

When the gate-on voltages are sequentially supplied to the plurality of gate driver ICs, all the gate-on voltages applied to the gate lines in each gate driver IC are lowered by lowering the supplied gate-on voltage by considering the wiring resistance between the gate driver ICs. Make almost the same. Therefore, the gate-on voltage difference generated by each gate driving IC is greatly reduced to improve the image quality of the liquid crystal display.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (24)

A gate driving device for a display device that receives a gate-on voltage from an external device. A voltage generator configured to generate a plurality of voltages having different values based on the input gate on voltage, and A voltage selector configured to select one of the plurality of voltages and output the corrected gate-on voltage according to a first control signal from the outside Gate drive. In claim 1, And the voltage generator includes a plurality of resistors connected in series with the input gate-on voltage. In claim 2, And a gate driver having the same value of the resistance. In claim 2, And the voltage generator includes a plurality of resistors connected in parallel to the input gate-on voltage. In claim 4, And a gate driver different in value of each resistor. In claim 2, The first control signal has a predetermined information, The gate driving apparatus further includes an order information identifying unit which starts an operation according to a second control signal from the outside and identifies the information of the first control signal and supplies the information to the voltage selector. And the voltage selector selects one of the plurality of voltages based on the information. In claim 6, And the counter information identifying unit comprises a counter for counting a pulse width of the first control signal. A liquid crystal panel assembly comprising a plurality of gate lines, a plurality of data lines, and a switching element connected to one of the gate lines and one of the data lines, respectively; A gate on voltage signal wire at least partially disposed on the liquid crystal panel assembly and transferring an input gate on voltage to turn on the switching element; A plurality of gate drivers connected to the gate on voltage signal wires and sequentially supplied with the input gate on voltage through the gate on voltage signal wires; Including, At least one of the gate drivers A gate on voltage corrector configured to correct the input gate on voltage based on a resistance of the gate on voltage signal line; Liquid crystal display. In claim 8, The gate driver further includes a flexible printed circuit board. In claim 8, And the gate driver is mounted on the liquid crystal panel assembly in the form of a chip or formed on the liquid crystal panel assembly, and all of the gate-on voltage wirings are formed on the liquid crystal panel assembly. In claim 8, The gate on voltage correction unit A voltage generator configured to generate a plurality of voltages having different values based on the input gate on voltage, and A voltage selector which selects one of the plurality of voltages according to a value of a first control signal and outputs the corrected gate-on voltage Liquid crystal display comprising a. In claim 11, And the voltage generator includes a plurality of resistors connected in series with the input gate-on voltage. In claim 12, And a resistance value of each resistor is set to a value within a range of about ± 60% of a resistance value of the gate-on voltage wiring portion disposed between the gate drivers. In claim 13, And a resistance value of each of the resistors is the same as that of the gate-on voltage wiring portion disposed between the gate drivers. In claim 11, And the voltage generator includes a plurality of resistors connected in parallel to the input gate-on voltage. The method of claim 15, A liquid crystal display device having a different resistance value of each resistor. The method of claim 16, And the difference between the resistance values of the respective resistors is set to a value within ± 60% of the resistance value of the gate-on voltage wiring portion disposed between the gate drivers. The method of claim 17, And a difference in resistance of each of the resistors is equal to a resistance of the gate-on voltage wiring portion disposed between the gate drivers. In claim 8, The first control signal has order information of the gate driver, And the gate on voltage correction unit further includes an order information identification unit for identifying and supplying order information of the first control signal to the voltage selector. The method of claim 19, And the order information is related to a pulse width of the first control signal. The method of claim 20, And the counter information identifying unit comprises a counter for measuring the pulse width. The method of claim 19, The first control signal is supplied to the respective gate driver from the outside. The method of claim 22, And the order information identifying unit starts an operation based on a second control signal. The method of claim 23, One of the gate drivers receives the second control signal from the outside, and the other gate driver receives the second control signal from the other gate driver.