KR20040015651A - A semiconductor device having a reverse active region using a selective epitaxial growth and the fabrication method thereof - Google Patents

Abstract

PURPOSE: A semiconductor device having a reverse active region formed by a selective epitaxial growth and a manufacturing method thereof are provided to be capable of increasing the width of a gate and reducing leakage current. CONSTITUTION: A semiconductor device is provided with a semiconductor substrate(100), a multi-layer having a contact region(290), deposited on semiconductor substrate, a reverse active region(300) formed in the contact region, and a gate formed on the surface of the reverse active region. At this time, the upper portion of the reverse active region is larger than the lower portion. At the time, a pair of stress portions(300-1) are formed at the upper portion of the reverse active region, so that three kinds of upper surfaces are formed at the upper portion of the reverse active region.

Description

A semiconductor device having a reverse active region formed by selective epitaxial growth and a method for manufacturing the same.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a reverse active region and a method of manufacturing the same. Specifically, a multi-layer is deposited on a semiconductor substrate to form a T-shaped contact, and the semiconductor substrate exposed as a contact is referred to as a seed. A semiconductor device having a reverse active region formed by a selective epitaxial growth (SEG) method and a method of manufacturing the same.

Recently, a semiconductor device having a trench in a semiconductor substrate has a problem of filling a trench formed for device isolation by reducing design rules, an increase in leakage current of a source / drain region forming a gate, and an area of an active region that is reduced in size. WIDTH) has a problem facing reduction.

The leakage current is generated due to a junction having a built-in potential BUI LT-IN POTENTIAL between the wells WELL separating NMOS and PMOS when the source / drain formed under the semiconductor substrate is not driven.

Hereinafter, with reference to the accompanying drawings will be described in the prior art.

1A to 1B are cross-sectional views of a semiconductor device in which a gate is formed on a semiconductor substrate with device isolation in the prior art.

As shown in FIG. 1A, the gate 30 and the gate spacer 35 are formed in the semiconductor substrate 10 having the trench 20 embedded therein using the device isolation layer 25.

In the trench 20, as the design rule of the semiconductor device is reduced, the width 1W of the bottom surface of the trench is reduced while the trench height 1D is fixed, thereby increasing the ASPECT RATIO.

The increase in the aspect ratio causes problems such as the formation of voids (VOID, not shown in the figure) when the trench 20 is buried in the device isolation film 25.

The physical gate whistle 2W and WIDTH of the gate 30 is a space interval formed between the trenches 20, and the increase / decrease of the gate whistle is proportional to the increase / decrease of the current driving capability of the semiconductor device.

The reduction of the design rule of the semiconductor device means a reduction in the space spacing formed between the trenches 20, and the method of overcoming the reduction of the gate whistle 2W using the semiconductor substrate 10 has reached its limit.

As shown in FIG. 1B, the gate 30 formed in FIG. 1A is cut in the opposite direction to overlie the gate 30 and the gate spacer 35 in the semiconductor substrate 10 having the trench 20 embedded in the device isolation layer 25. An overlapped source / drain region 40 is formed.

The source / drain region 40 forms a junction with a well (not shown) formed in the semiconductor substrate 10 to form a built-in potential (BUILT-IN POTENTIAL).

The junction refers to a depletion layer formed between regions having different types of N-type or P-type formed by an implant on the semiconductor substrate 10.

When no power is applied to the semiconductor device, the built-in potential is a natural leakage current corresponding to the area portions 40-1 and 40-2 of the junctions formed on the bottom and side surfaces of the source / drain region 40 (Fig. Emi city) only shed.

However, when power is applied to the semiconductor device, the sum (SUM) of the built-in potential and the artificial potential increase is equal to the area portion of the junction 40-1 formed at the bottom and side surfaces of the source / drain region 40 with a corresponding leakage current. 40-2).

Since the prior art calculates the design rule of the semiconductor device using the top surface of the semiconductor substrate 10, the increase in the aspect ratio (1D / 1W, ASPECT RATIO) and the gate of the trench 20 corresponding to the design rule reduction. It has reached its limit in overcoming a decrease in whistle (2W).

In addition, the related art does not prevent leakage current LEAKAGE CURRENT from leaking to the junction of the source / drain region 40 formed under the semiconductor substrate 10 with the well WELL.

In order to solve the above technical problem, the present invention forms a reverse active region by using a SEG (SELE CTIVE EPITAXIAL GROWTH) method on the semiconductor substrate to solve the problem of filling the insulating film for device isolation and increase the gate whistle This reduces the area fraction of the junction of the leaking source / drain regions.

1A to 1B are cross-sectional views of a semiconductor device in which a gate is formed on a semiconductor substrate in which a device of the prior art is separated.

2A is a cross-sectional view of a semiconductor device in which openings are formed in selected portions of a semiconductor substrate on which the multi-layers of the present invention are deposited.

FIG. 2B is a cross-sectional view of a semiconductor device in which a reverse active region is formed in a semiconductor substrate by a selective epitaxial growth (SEG) method after etching a selected layer among multiple layers of the present invention; FIG.

Fig. 2C is a cross sectional view of the semiconductor device with the upper portion of the reverse active region of the present invention open;

Fig. 2D is a cross sectional view of the semiconductor device deposited with an insulating film to isolate between the upper portions of the reverse active regions of the present invention.

2E-2F are cross-sectional views of a semiconductor device with a gate formed in the reverse active region of the present invention.

(Explanation of symbols for the main parts of the drawing)

100 semiconductor substrate 200 first insulating film

230, 230-1: nitride film 260: second insulating film

280: multi-layer 285: opening

290: Contact 3W: Space interval

300: REVERSE ACTIVE REGION

300-1: stress area 300-2: bottom

300-3: CORNER

A, C: vertical direction B, B ': horizontal direction

D: Top E: Bottom

F: curve G: straight line

H: buried depth

400, 400-1: Third insulating film 500: Gate

600: source / drain area 600-1, 600-2: area

In order to realize the above technical problem, the semiconductor device of the present invention includes a multi-layer having a contact deposited on a semiconductor substrate, a reverse active region formed at a predetermined height within the contact, and a gate formed in contact with an upper surface of the reverse active region. And forming a T-shaped contact on the multi-layer, wherein the upper portion of the reverse active region is larger than the lower portion in a direction parallel to the semiconductor substrate, and a stress portion is formed on the multi-layer in the direction perpendicular to the semiconductor substrate. It is characterized by three curved surfaces on the top of the active area.

In addition, the method of manufacturing a semiconductor device of the present invention comprises the steps of depositing a multi-layer on a semiconductor substrate, etching the multi-layer to expose a selected portion of the semiconductor substrate to form an opening, and through the opening Forming a contact by etching the selected layer in parallel with the semiconductor substrate, and forming a reverse active region by filling the contact using a selective epitaxial growth (SEG) method using the exposed semiconductor substrate as a seed; Etching only a portion of the multi-layer forming the contact to open only an upper portion of the reverse active region; depositing an insulating film to isolate the reverse active region; and performing chemical mechanical polishing on the insulating layer to perform reverse activation. Exposing an upper surface of the region and an insulating layer etched from the upper surface of the reverse active region And forming a gate by depositing a poly film, wherein the whistle of the gate is increased by using an upper surface of the reverse active region formed in the contact, and a lower surface of the reverse active region is in contact with the insulating layer to reduce the leakage current. .

The layer selected in the multi layer is different from other layers in which the etch selectivity constitutes the multi layer, and the contact buried may be filled to the upper surface of the multi layer.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A is a cross-sectional view of a semiconductor device in which openings are formed in selected portions of a semiconductor substrate on which the multi-layers of the present invention are deposited.

As illustrated in FIG. 2A, the first insulating layer 200, the nitride layer 230, and the second insulating layer 260 are sequentially deposited on the semiconductor substrate 100 to form the multi layer 280, and the multi layer 280 is etched. Openings 285 are formed to expose selected portions of the semiconductor substrate 100.

The opening 285 has a taper because the selectivity to etching of the layers 200, 230, and 260 constituting the multi layer 280 is different.

That is, when the nitride film 230 is not disposed in the middle of the multi-layer 280, an opening (not shown) having a constant width may be formed.

FIG. 2B is a cross-sectional view of a semiconductor device in which a reverse active region is formed on a semiconductor substrate by etching a layer selected from among the multi-layers of the present invention by a selective epitaxial growth (SEG) method.

As shown in FIG. 2B, only the nitride film 230 is selectively etched in the multi layer 280 forming the opening 285 of FIG. 2A to form a T-shaped contact 290, and the SEG method is used for the semiconductor substrate 100. Thus, the reverse active region 300 is formed by filling the contact 290.

The lower portion E of the reverse active region 300 is primarily insulated using the first insulating layer 200 without the need for an additional process compared to the related art.

The etched nitride layer 230-1 maintains a predetermined space interval 3W that is not electrically connected between the reverse active regions 300, and the etching is performed on the reverse active region 300 formed in the semiconductor substrate 100. It helps to increase the width of.

The reverse active region 300 is divided into a lower portion E contacting the first insulating layer 200 and an upper portion D contacting the nitride layer 230-1 and the second insulating layer 260.

The lower portion E of the reverse active region 300 has a shape of an opening 285 formed by the first insulating layer 200 of FIG. 2A, and the SEG is grown in the vertical direction A with respect to the semiconductor substrate 100. In the upper portion D of the reverse active region 300, the SEG is grown in the vertical direction C and the horizontal direction B and B ′ with respect to the semiconductor substrate 100 by etching of the nitride film 230 of FIG. 2A. Is formed.

The upper portion D of the reverse active region 300 may have a stress portion 300-at the corner CORNER of the second insulating layer 260 when the SEG is grown in the vertical direction C with respect to the semiconductor substrate 100. 1) is a portion where the growth rate is lowered to the semiconductor substrate 100 than the horizontal directions B and B '.

That is, the difference in growth rate creates three inflection points (INFLECTION POINT) in the stress area (300-1) to form three curves on the upper surface of the reverse active region (300).

The three curves form the effect of increasing the area of the upper surface of the reverse active region 300.

2C is a cross-sectional view of the semiconductor device with the upper portion of the reverse active region of the present invention open.

As illustrated in FIG. 2C, the nitride layer 230-1 and the second insulating layer 260 of FIG. 2B are etched to expose the upper portion D of the reverse active region 300.

The thickness of the first insulating layer 200 is spaced apart from the bottom surface 300-2 of the reverse active region 300 so that a predetermined lower portion E is exposed so that voids are not generated in a subsequent process (not shown). Control to prevent damage.

The voids may deteriorate characteristics during temperature testing after packaging the semiconductor device (not shown).

2D is a cross-sectional view of a semiconductor device in which an insulating film is deposited to isolate between upper portions of the reverse active regions of the present invention.

As illustrated in FIG. 2D, a third insulating layer 400 is deposited on the upper surface of the first insulating layer 200 and the upper portion D of the reverse active region 300 to insulate the reverse active region 300 in a second order.

The third insulating layer 400 is deposited to have a predetermined thickness such that the bending of the upper surface of the third insulating layer 400 does not occur due to the shape of the upper portion D of the reverse active region 300.

2E to 2F are cross-sectional views of a semiconductor device in which a gate is formed in a reverse active region of the present invention.

As shown in FIG. 2E, the third insulating film 400-etched by performing chemical mechanical polishing (not shown) on the third insulating film 400 of FIG. 2D to expose the upper surface D of the reverse active region 300. 1) the reverse active region 300 is isolated, and a poly film is deposited on the etched third insulating layer 400-1 and the upper surface D of the reverse active region 300 to form the gate 500.

In the chemical mechanical polishing, the first insulating layer 200 and the etched third insulating layer 400-1 have a predetermined buried depth H to isolate the reverse active region 300 from each other. The upper surface D is exposed.

The gate 500 has a straight line G which is expected to be SEG growth when the curve F created by the growth of the SEG formed on the side of the second insulating film 260 of FIG. 2B is absent from the second insulating film 260 of FIG. 2B. Because of its length compared to), it has a physically increased WIDTH.

The formation of the reverse active region 300 may increase the whistle of the gate 500 in response to the reduction of the design rule.

The increase of the gate 500 increases the current driving capability of the gate 500 and improves the characteristics of the semiconductor device.

FIG. 2F is a cross-sectional view of the semiconductor device cut in the opposite direction to FIG. 2E with respect to the reverse active region 300.

2E, the thickness of the etched third insulating layer 400-1 that isolates the reverse active region is determined in consideration of a process capability of etching the poly film deposited on the upper surface of the reverse active region 300. You have to control it.

If the thickness is not controlled, a poly film residue is formed at the corner 300-3 formed between the upper surface D and the side surface of the reverse active region 300 to cause a short between the gate 500. .

In addition, the formation of the reverse active region 300 has the advantage that the area portions 600-1 and 600-2 of the junction that generate leakage current (not shown) from the source / drain region 600 are reduced. The junction refers to a depletion layer formed between regions having different types of N-type or P-type formed by an implant on the semiconductor substrate 10.

That is, since the bottom surface 600-1 of the source / drain region 600 is in contact with the first insulating layer 200, the well formed in the reverse active region 300 and the built-in potential BUILT− IN POTENTIAL).

Therefore, the part which makes leakage current is the area portion 600-2 of the junction which forms the built-in potential with the well WELL in the side of the source / drain area 600, and through this, the reverse active area 300 becomes the leakage current. It has the advantage that can significantly reduce.

According to the present invention, the reverse active region 300 is formed in the semiconductor substrate 100 by the SEG method, thereby increasing the gate 500 whistle and reducing the leakage current in the reduced design rule, thereby improving the characteristics of the semiconductor device.

As described above, the present invention eliminates the problem of isolating the reverse active region by forming a reverse active region by using the SEG method on the semiconductor substrate, and by forming three curves on the upper surface of the reverse active region to increase the gate whistle, The bottom surface of the reverse active region is brought into contact with the insulating layer to reduce the leakage current in proportion to the area of the junction of the source / drain region with the well, thereby improving semiconductor characteristics.

Claims (4)

A multi-layer having a contact deposited on the semiconductor substrate, a reverse active region formed at a predetermined height within the contact, and a gate formed in contact with an upper surface of the reverse active region, By forming a T-shaped contact on the multi-layer, the width of the upper portion of the reverse active region in the direction parallel to the semiconductor substrate is larger than the lower portion, and the stress portion is formed in the multi-layer in the direction perpendicular to the semiconductor substrate to reverse A semiconductor device having a reverse active region formed by selective epitaxial growth characterized by three curved surfaces on an upper surface of the region. Depositing multiple layers on a semiconductor substrate; Etching the multi-layer to expose selected portions of the semiconductor substrate to form openings; Etching selected layers of the multi-layers in parallel with the semiconductor substrate through the openings to form contacts; Forming a reverse active region by contact embedding using the exposed semiconductor substrate as a seed using a selective epitaxial grow (SEG) method; Etching only a portion of the multi-layer forming the contact to open only an upper portion of a reverse active region; Depositing an insulating film to isolate said reverse active region; Performing chemical mechanical polishing on the insulating layer to expose a top surface of a reverse active region; Depositing a poly film on an upper surface of the reverse active region and an etched insulating layer to form a gate; Including; A semiconductor having a reverse active region formed by selective epitaxial growth characterized by increasing the whistle of the gate by using an upper surface of the reverse active region formed in the contact, and reducing the leakage current by contacting the bottom surface of the reverse active region with the insulating film. Device manufacturing method. The method of claim 2, wherein the layer selected from the multi-layers has a reverse active region formed by selective epitaxial growth, wherein an etch selectivity is different from other layers constituting the multi-layers. The method of claim 2, wherein the contact buried material is filled to the top surface of the multi-layer, and the reverse active region formed by selective epitaxial growth.