KR20040015594A - Method for forming mos transistor of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming an MOS(Metal Oxide Semiconductor) transistor of a semiconductor device is provided to be capable of minimizing the deterioration of punch-through characteristics. CONSTITUTION: A pair of punch barriers(113a) are formed at the inner portions of a semiconductor substrate(100). A channel epitaxial layer(117) is formed at the upper surface of the semiconductor substrate. An isolation layer(119) is formed at the inner portion of the resultant structure for defining an active region. At this time, at least one punch barrier is located in the active region. At the time, the punch barrier is across the active region. Preferably, the punch barrier is made of an insulating layer. Preferably, a CVD(Chemical Vapor Deposition) silicon oxide layer is used as the insulating layer.

Description

Method for forming MOS transistor of semiconductor device

The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a MOS transistor.

The MOS transistor of the semiconductor device is typically composed of a source / drain region formed on a semiconductor substrate, a channel region between the source region and a drain region, and a gate electrode disposed over the channel region. According to the tendency of high integration of semiconductor devices, punch-through characteristics of the MOS transistor may be degraded.

1 is a cross-sectional view illustrating a general MOS transistor.

Referring to FIG. 1, in a typical MOS transistor, a gate electrode 5 is disposed on a first conductive semiconductor substrate 1, and a gate insulating film 4 is disposed between the gate electrode 5 and the semiconductor substrate 1. ) Is interposed. Impurity diffusion layers 2 and 3 of the second conductivity type are disposed on the semiconductor substrate 1 on both sides of the gate electrode 5. The impurity diffusion layers 2 and 3 correspond to the source region 2 and the drain region 3. When the MOS transistor is an NMOS transistor, the semiconductor substrate 1 is p-type, and the source / drain regions 2 and 3 are n-type. In contrast, when the MOS transistor is a PMOS transistor, the semiconductor substrate 1 is n-type, and the source / drain regions 2 and 3 are p-type. An interface between the source / drain regions 2 and 3 and the semiconductor substrate 1 forms a pn junction. Accordingly, a source depletion region a is formed into the semiconductor substrate 1 from an interface between the source region 2 and the semiconductor substrate 1, and the drain region 2 and the semiconductor substrate 1 are formed. A drain depletion region b is formed in the liver. Typically, since the source / drain regions 2 and 3 have the same impurity concentration, the area of the source / drain depletion regions a and b is the same.

The punch-through refers to a phenomenon in which a current flows between the source / drain regions 2 and 3 by a drain voltage applied to the drain region 3 while the transistor is turned off.

Briefly explaining the cause of the punch-through characteristic, after applying a turn off voltage to the gate electrode 5, applying a ground voltage to the source region 2, and then drain voltage to the drain region 3. Is applied. In this case, as illustrated in FIG. 1, the drain depletion region b is extended by the drain voltage. As the drain voltage increases gradually (in the case of PMOS transistors), the area of the drain depletion region b gradually increases. When the drain depletion region b is in contact with the source depletion region a, the drain region 3 and the source region 2 are conductive. At this time, the drain voltage is referred to as punch-through voltage. When the punch-through voltage is low, the transistor turned off may be turned on due to a noise voltage.

As the semiconductor device is highly integrated, the distance between the source region and the drain region is becoming narrower. As a result, the punch-through voltage may gradually decrease to deteriorate the punch-through characteristic.

An object of the present invention is to provide a MOS transistor forming method that can minimize the deterioration of punch-through characteristics.

1 is a cross-sectional view illustrating a general MOS transistor.

2 is a plan view illustrating a MOS transistor according to a preferred embodiment of the present invention.

3 to 8 are cross-sectional views illustrating a method of forming a MOS transistor taken along the line II ′ of FIG. 2.

9 is a cross-sectional view for describing a method of forming a punch barrier in an active region according to an exemplary embodiment of the present invention.

Provided are a MOS transistor forming method for solving the above technical problem. This method involves forming a pair of punch barriers having a predetermined depth from the surface of the semiconductor substrate. A channel epitaxial layer is formed on the entire surface of the semiconductor substrate having the pair of punch barriers, and an isolation layer is formed on the channel epitaxial layer and the semiconductor substrate to define an active region. At least one of the pair of punch barriers is located in the active area, and the punch barriers located in the active area cross the active area.

Specifically, the method of forming the pair of punch barriers includes forming a barrier mask pattern having an opening that exposes a predetermined region of the semiconductor substrate. The semiconductor substrate exposed to the opening is selectively etched to form a barrier trench, and barrier spacers are formed on both sidewalls of the opening and on both sidewalls of the barrier trench. A gap fill epitaxial layer is formed to fill the barrier trench from the bottom of the barrier trench exposed to the barrier spacer. The barrier mask pattern is etched to expose the semiconductor substrate. In this case, the barrier spacer formed on the sidewall of the opening forms a protrusion protruding onto the semiconductor substrate. The protrusion is removed to form a pair of punch barriers interposed between both sidewalls of the barrier trench and the gapfill epitaxial layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout.

2 is a plan view illustrating a MOS transistor according to a preferred embodiment of the present invention.

Referring to FIG. 2, a plurality of active regions 102 are two-dimensionally arranged on the semiconductor substrate 101. An isolation layer 119 is disposed between the active regions 102, and a plurality of gate patterns 125 that cross the upper portions of the active regions 102 are disposed. The punch barrier 113a parallel to the gate pattern 125 is disposed in the semiconductor substrate 101 under the gate patterns 125. In other words, the punch barrier 113a crosses the active region 113a. A pair of gate patterns 125 may cross the upper portion of each of the active regions 102.

3 to 8 are cross-sectional views illustrating a method of forming a MOS transistor taken along the line II ′ of FIG. 2.

3 and 4, a barrier trench mask layer 107 is formed on the semiconductor substrate 101. The barrier trench mask layer 107 may be composed of a barrier buffer insulating layer 103 and a barrier hard mask layer 105 which are sequentially stacked. The barrier hard mask layer 105 may be formed of a material layer having an etching selectivity with the semiconductor substrate 101. For example, it can be formed from a silicon nitride film. The barrier buffer insulating layer 103 serves to suppress stress between the barrier hard mask layer 105 and the semiconductor substrate 101. The barrier buffer insulating film 103 is preferably formed of a thermal oxide film.

The barrier trench mask layer 107 is patterned to form a barrier mask pattern 107a having an opening 109 exposing a predetermined region of the semiconductor substrate 10. The barrier mask pattern 107a includes a barrier buffer pattern 103a and a barrier hard mask pattern 105a that are sequentially stacked. Both sidewalls of the opening 109 may include the barrier buffer pattern 103a and the barrier hard mask pattern 105a.

The semiconductor substrate 101 exposed to the opening 109 is selectively etched to form a barrier trench 111. A barrier spacer layer is conformally formed on the semiconductor substrate 101 having the barrier trench 111, and the barrier spacer layer is anisotropically etched to barrier both sidewalls of the opening 109 and both sidewalls of the barrier trench 111. The spacer 113 is formed.

The barrier spacer 113 is formed of an insulating film. For example, it is preferable to form with a CVD silicon oxide film.

A gap filling epitaxial layer 115 is formed from an inner bottom of the barrier trench 111 in which the barrier spacer 113 is formed. The gapfill epitaxial layer 115 fills the inside of the barrier trench 111. In this case, the gap fill epitaxial layer 115 is not formed in the semiconductor substrate 1 due to the barrier mask pattern 107a. The gap fill epitaxial layer 115 may be formed to have the same height as the surface of the semiconductor substrate 101. The gap fill epitaxial layer 115 is formed of a silicon layer and has the same crystal structure as the semiconductor substrate 101.

5 and 6, the barrier mask pattern 107a is etched to expose the semiconductor substrate 101. In this case, a protrusion k protruding from the barrier spacer formed on the sidewall of the opening 109, that is, the sidewall of the barrier mask pattern 107a is formed. The protrusion k is removed to form a pair of punch barriers 113a interposed between both sidewalls of the barrier trench 111 and the gapfill epitaxial layer 115. The pair of punch barriers 113a are the barrier spacers 113 remaining between both sidewalls of the barrier trench 111 and the gapfill epitaxial layer 115. The punch barriers 113a have a predetermined depth from the surface of the semiconductor substrate 101.

When the barrier mask pattern 107a is etched to expose the semiconductor substrate 101, the punch barriers 113a may also be etched simultaneously to form the punch barriers 113a. In other words, when the barrier buffer pattern 103a constituting the barrier mask pattern 107a is etched, the protrusion k may be simultaneously etched by isotropic etching. Alternatively, the barrier mask pattern 107a and the protrusion k may be planarized by a chemical mechanical polishing process (CMP) until the barrier mask pattern 107a is exposed to the semiconductor substrate 101. Can be removed at the same time.

After the punch barriers 113 are formed, the surface of the gap fill epitaxial layer 115 and the semiconductor substrate 101 may be flattened by a chemical mechanical polishing process.

2, 7 and 8, the channel epitaxial layer 117 is formed on the entire surface of the semiconductor substrate having the punch barriers 113a. The channel epitaxial layer 117 is formed of a silicon layer and has the same crystal structure as the semiconductor substrate 101. In this case, the channel epitaxial layer 117 is formed on the upper surfaces of the punch barriers 113a. This is because silicon layers are formed on sidewalls of the channel epitaxial layer 117 formed from the surfaces of the semiconductor substrate 101 on both sides of the punch barriers 113a.

The channel epitaxial layer 117 and the semiconductor substrate 101 are successively patterned to form a device isolation trench 118 defining a plurality of active regions 102, and to fill the device isolation trench 118. An isolation layer 119 is formed. At this time, at least one of the pair of punch barriers 113a is located in each of the active regions 102. 2 and 8 illustrate that the pair of punch barriers 113a are all formed in the active regions 101. The active region 102 is defined such that the punch barriers 113a cross the active region 102.

A gate pattern 125 is formed on the channel epitaxial layer 117 on the punch barriers 113a. The gate pattern 125 is parallel to the punch barriers 113a. In other words, the gate pattern 125 crosses the active region 102 while passing through the punch barriers 113a. The gate pattern 125 includes a gate insulating layer 121 and a gate electrode 123 sequentially stacked on the channel epitaxial layer 117. The gate insulating layer 121 may be formed of a thermal oxide layer. The gate electrode 123 may be formed of a doped polysilicon layer or a polyside layer. The polyside film is composed of a doped polysilicon film and a metal silicide film sequentially stacked. Gate spacers 127 may be formed on both sidewalls of the gate pattern 125. The impurity diffusion layer 129 is formed by implanting impurity ions using the gate spacer 127 and the gate pattern 125 as a mask. The impurity diffusion layer 129 is disposed on the channel epitaxial layer 117 and the semiconductor substrate 101 on both sides of the gate pattern 125. The impurity diffusion layer 129 corresponds to a source / drain region, and the channel epitaxial layer between the source region and the drain region corresponds to a channel region. The gate pattern 125, the source / drain region 129, and the channel region constitute a MOS transistor. In this case, due to the punch barrier 113a under the gate pattern 125, the area of the depletion region of the drain region 119 due to the drain voltage may be prevented from expanding to the source region 119. As a result, the punchthrough characteristics of the MOS transistor can be improved. The punch barrier 125 does not affect the normal operation of the MOS transistor due to the channel region.

2 and 8 illustrate that two gate patterns 125 are formed in the active region 102. Alternatively, one gate pattern 125 may be formed in the active region 102. In this case, one punch barrier 113a is formed in the active region 101.

9 is a cross-sectional view illustrating a method of forming a punch barrier in an active region according to an embodiment. The method of forming the pair of punch barriers and the channel epitaxial layer is the same as described with reference to FIGS. 3 to 7.

Referring to FIG. 9, the channel epitaxial layer 117 and the semiconductor substrate 101 are successively etched to form an isolation trench 118a defining an active region. In this case, the device isolation trench 118a exposes any one selected from the pair of punch barriers 113a. The exposed punch barrier 113a is preferably partially exposed in the depth direction from the surface of the semiconductor substrate 101.

The exposed punch barrier 113a may be etched to the bottom surface of the device isolation trench 118a. An isolation layer 119a is formed to fill the isolation trench 118a in which the exposed punch barrier 113a is etched. Unlike this, since the punch barrier 113a is an insulating layer, the punch barrier 113a may not be etched. That is, the device isolation layer filling the inside of the device isolation trench 118a having the exposed punch barrier 113a may be formed.

A gate pattern 125 is formed on the punch barrier 113a in the active region, and an impurity diffusion layer 129 is formed on both sides of the gate pattern 125. Before forming the impurity diffusion layer 129, gate spacers 127 may be formed on both sides of the gate pattern 125.

According to the present invention, punch barriers are formed in a semiconductor substrate, and an isolation layer defining an active region is formed so that the punch barriers cross the active region. Each of the punch barriers is located under the channel region under the gate pattern. As a result, the punch barriers can prevent the depletion region of the source region and the depletion region of the drain region from expanding. As a result, the punchthrough characteristics of the MOS transistor can be improved.

Claims (7)

Forming a pair of punch barriers having a predetermined depth from the surface of the semiconductor substrate; Forming a channel epitaxial layer on a surface of the semiconductor substrate having the pair of punch barriers; And Forming an isolation layer in the channel epitaxial layer and the semiconductor substrate to define an active region, wherein at least one of the pair of punch barriers is located in the active region, and the punch barrier is located in the active region And MOS transistors across the active region. The method of claim 1, Forming the pair of punch barriers, Forming a barrier mask pattern having an opening that exposes a predetermined region of the semiconductor substrate; Selectively etching the semiconductor substrate exposed to the opening to form a barrier trench; Forming barrier spacers on both side walls of the opening and both side walls of the barrier trench; Forming a gapfill epitaxial layer filling the barrier trench from the bottom of the barrier trench exposed to the barrier spacer; And Etching the barrier mask pattern to expose the semiconductor substrate, wherein the barrier spacer formed on the sidewall of the opening forms a protrusion protruding onto the semiconductor substrate; And Removing the protrusion to form a pair of punch barriers interposed between both sidewalls of the barrier trench and the gapfill epitaxial layer. The method of claim 2, And forming the barrier mask pattern and the protrusion at the same time. The method of claim 1, And the pair of punch barriers are formed of an insulating film. The method of claim 4, wherein And the insulating film is formed of a CVD silicon oxide film. The method of claim 1, And the device isolation layer is formed of a trench device isolation layer. The method of claim 1, After forming the device isolation film, Forming a gate pattern parallel to the punch barriers on the punch barriers in the active region; And And forming an impurity diffusion layer in the active region on both sides of the gate pattern.