KR20040012403A - Decoding apparatus for variable length code and method thereof - Google Patents

Abstract

PURPOSE: An apparatus and a method for decoding a variable length code are provided to realize fast decoding by dividing a data bit stream by 3 bits, and reduce the size of a target table to be decoded, thereby reducing power consumption. CONSTITUTION: A pre-decoder(107) receives a data bit stream, and generates a first selection signal or a second selection signal selecting one of first to Mth look-up table address registers(140). A selector(150) selects one of outputs of the first to Mth look-up table address registers according to the first selection signal or the second selection signal. A memory control unit(153) generates a third selection signal selecting a terminal value to obtain a predetermined symbol address, and a fourth selection signal selecting a predetermined fixed length code. A memory(165) stores an LOC table value, the terminal value, and the fixed length code, and outputs the LOC table value, the terminal value in response to the third selection signal, and outputs the fixed length code in response to the fourth selection signal. A shifter(130) shifts the data bit stream as many as certain bits in response to the first selection signal or the second selection signal, and continuous node signals.

Description

Variable length code decoding apparatus and method

The present invention relates to a decoding apparatus, and more particularly, to a variable length code decoding apparatus for decoding variable length coded data.

The International Standard for the Video Specification of the Moving Picture Expert Group (MPEG) 2 is a standard for moving picture compression and decompression, published in April 1994, and several parties are working to make it a reality.

Digital video signal compression is increasing in many applications such as digital image data transmission and digital storage devices.

Image compression algorithms generally perform lossless compression of image data using a variable length encoder.

The variable length encoding apparatus allocates short bits for a symbol of data that is used a lot, and long bits for a symbol of data that is used relatively little. Therefore, when the variable length encoding apparatus encodes a data bit stream having the same length, the length of the data bit stream is shorter than that of the fixed length encoding apparatus.

A variable length decoder separates a variable length code corresponding to one symbol from an input variable length coded data bit stream. Fixed length codes can be obtained using a symbol table from separate variable length codes.

In this case, if the variable length encoding table used in the variable length encoding apparatus should be set by the user, the variable length decoding apparatus reads a fixed length bit from the input data bit stream based on the table written in the encoding apparatus. As you look, you separate out the variable length code.

The most basic method is to use a tree search algorithm by separating the input data bit stream by one bit. In the case of MPEG, since the maximum length of a code is 16 bits, a code value can be obtained only when a maximum of 16 tree searches are performed. Another method is to use a tree search algorithm by separating the data bit stream by two bits. In this case, a maximum of eight tree searches must be performed to obtain a code value.

The more bits in the data bit stream that are separated at one time, the faster the decoding speed is. However, the larger the number of bits of the separated data bit stream, the more complicated the structure of the decoding apparatus is, so a proper trade off between the decoding speed and the area of the decoding apparatus is required.

The present invention proposes a decoding apparatus and method for separating an input data bit stream by three bits. The present invention also proposes a decoding apparatus and method for selecting two pre-decoding methods according to characteristics of code values of an input data bit stream.

An object of the present invention is to provide a variable length code decoding apparatus capable of separating and decoding an input data bit stream by L bits and selecting a pre-decoding method according to characteristics of a code value of an input data bit stream. have.

Another technical problem to be solved by the present invention is to provide a variable length code decoding method for separating and decoding an input data bit stream by L bits and selecting a pre decoding method according to a characteristic of a code value of an input data bit stream. It is.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram illustrating a variable length code decoding apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a LOC information table stored in the memory search unit of FIG. 1.

3 is a diagram showing symbols and variable length codes.

4 is a conceptual diagram for obtaining a symbol from a variable length code.

FIG. 5 is a diagram illustrating a LOC table value and a terminal value stored in the memory of FIG. 1.

6 is a diagram illustrating a symbol and a fixed length code.

7 is a flowchart illustrating a method of decoding a variable length code according to a first embodiment of the present invention for achieving another technical problem.

8 is a flowchart illustrating operation 710 of FIG. 7.

The decoding apparatus according to the embodiment of the present invention for achieving the above technical problem is a pre-decoding unit, a shifting unit, the first to M (M is a natural number) lookup table address register, selector, memory controller, memory and memory search unit It is characterized by including.

The pre decoding unit receives a data bit stream and generates a first or second selection signal for selecting one of predetermined first through Mth lookup table address registers according to a code value of the data bit stream.

The shifting unit shifts the data bit stream by a predetermined bit in response to one of the first selection signal or the second selection signal and the continuous node signal.

The first through Mth (M is a natural number) lookup table address registers each have a LOC address specifying an LOC table value of K (K is a natural number) bits stored in a predetermined memory.

The selector selects and outputs one of the outputs of the first to Mth lookup table address registers in response to the first selection signal or the second selection signal.

The memory controller receives the output of the selector, and selects a third select signal for selecting a terminal value corresponding to the LOC table value stored in the memory and the LOC table value and obtaining a predetermined symbol address in response to a predetermined continuous node signal. Or a fourth selection signal for selecting a predetermined fixed length code stored in the memory in response to the predetermined symbol address signal.

The memory stores the LOC table value, the terminal value and the fixed length code and outputs the selected LOC table value and the terminal value in response to the third selection signal or the fixed length in response to the fourth selection signal. Output the code

The memory retrieval unit receives the selected LOC table value, the terminal value, and the L (L is a natural number) bit of the data bit stream output from the memory, and uses the LOC information table stored therein to determine the data bit stream. It is determined whether the L bit is a terminal node or a continuous node to generate a continuous node signal or a symbol address signal.

The fixed length code output from the memory is received and output.

The pre decoding unit may include a first pre decoding unit and a second pre decoding unit.

When the first pre-decoding unit receives the data bit stream and 0 or 1 is contiguous to the most significant bit MSB of the data bit stream, the first pre-decoding unit includes one of the first to Mth lookup table address registers according to the number of zeros or ones. Generate a first selection signal to select one.

The second pre-decoding unit receives the data bit stream and selects one of the first to Mth lookup table address registers by using N (N is a natural number) bit of the most significant bit (MSB) side of the data bit stream. Generate a second selection signal.

The shifting unit shifts the data bit stream by 3 bits in response to the continuous node signal.

The memory controller may include an offset register, an adder, a LOC address register, and a symbol address register.

An offset register receives the output of the selector and stores the output of the selector until a new output of the selector is received.

The adder generates a third select signal that selects the values of the LOC table stored in the memory by adding the output of the offset register and a predetermined next LOC address.

The LOC address register generates the next LOC address for selecting a LOC table value in response to the continuous node signal.

A symbol address register generates the fourth select signal for obtaining the fixed length code in response to the symbol address signal.

The next LOC address is characterized by adding the current LOC address and the number of non-terminal nodes before the current node including the current node in the current LOC.

The symbol address may be a value obtained by adding a terminal value corresponding to a current LOC table value and the number of terminal nodes before the current node excluding the current node in the current LOC.

The LOC information table stored in the memory retrieval unit has a node type indicating whether a node indicated by a variable length code is a terminal node, a continuous node, or an invalid node, wherein each node type is N * { 2} ^ {L} bits having LOC information bits, and the LOC information bits are characterized by being represented by four types of A, B, C, and D each consisting of N bits.

In the LOC information table stored in the memory searching unit, when the variable length code is 0, 1, 00, 01, 10, or 11, the node type indicated by the variable length code is a terminal node, and the variable length code is 000 to 111. If present, the node type indicated by the variable length code is any one of a terminal node, a continuous node, and an invalid node.

If N is 2 bits and L is 3 bits, if the variable length code is 0, the upper 8 bits of the LOC information bits are represented by ABBB. If the variable length code is 1, the lower 8 bits of the LOC information bits are represented. If the variable length code is 00, the upper 4 bits of the LOC information bits are represented by AB. If the variable length code is 01, the upper 5 to 8 bits of the LOC information bits are represented by AB. If the variable length code is 10, the upper 9 to 12 bits of the LOC information bits are represented by AB, and when the variable length code is 11, the upper 13 to 16 bits of the LOC information bits are represented by AB. When the variable length code is 000 to 111, the LOC information bit is represented by A when the node type indicated by the variable length code is a terminal node, and the LOC information bit is represented by C when the node is a continuous node. If the LOC is characterized in that the information bits are represented by D.

In the LOC information table stored in the memory retrieval unit, when the variable length code is 0 or 1, the node type indicated by the variable length code is a terminal node, and when the variable length code is present between 00 and 11, the variable length The node type indicated by the code is any one of a terminal node, a continuous node, and an invalid node. If the N is 2 bits and the L is 2 bits, the upper 4 bits of the LOC information bit are 0 when the variable length code is 0. When the variable length code is 1 and the variable length code is 1, the lower 4 bits of the LOC information bit are represented by the AB. When the variable length code is 00 to 11, the node type indicated by the variable length code is a terminal node. The LOC information bits are represented by A, the LOC information bits are represented by C when the node is a continuous node, and the LOC information bits are represented by D when the node is an invalid node.

The LOC table value stored in the memory may include LOC information bits corresponding to a node type of the LOC information table indicated by a variable length code.

According to another aspect of the present invention, there is provided a variable length code decoding method including: first through M (M is natural numbers) lookup table address registers each having a predetermined LOC address, and the LOC address. And a memory retrieval unit having a LOC table value corresponding to K (K is a natural number), a memory storing a predetermined terminal value and a fixed length code, and a LOC information table having information as a reference for decoding a variable length code. In the variable length code decoding method of a variable length code decoding apparatus,

(a) receiving a data bit stream and generating a first or second selection signal that selects one of the lookup table address registers according to a code value of the data bit stream; (b) the first selection signal or the Selecting and outputting one of the outputs of the first to Mth lookup table address registers in response to a second selection signal; (c) adding the output of step (b) and a predetermined next LOC address to the memory; Generating a third selection signal that selects a value of a stored LOC table and a terminal value corresponding to the LOC table value and to obtain a predetermined symbol address, (d) a LOC table value selected in response to the third selection signal, and Outputting a terminal value, (e) the selected LOC table value, terminal value and data bit stream output from the memory; Receiving an L bit, and determining whether the L bit of the data bit stream is a terminal node or a continuous node using the LOC information table to generate a continuous node signal or a symbol address signal; and (f) generating the continuous node signal. In response to generating the next LOC address for selecting the LOC table value and applying it to step (c), (g) generating a fourth selection signal for obtaining the fixed length code in response to the symbol address signal And (h) outputting a terminal value from the memory in response to the fourth selection signal, selecting a symbol address in response to the output terminal value, and outputting a fixed length code corresponding to the selected symbol address. Characterized in that it comprises a step.

Step (a) may include (a1) a first selection of selecting one of the plurality of lookup table address registers according to the number of 0s or 1s when 0s or 1s are contiguous to the most significant bit (MSB) of the data bit stream. Generating a signal; (a2) generating a second selection signal for selecting one of the plurality of lookup table address registers using N (N is a natural number) bit of the most significant bit (MSB) side of the data bit stream; And (a3) moving the data bit stream by a constant bit in response to one of the first selection signal or the second selection signal and the continuous node signal.

The next LOC address is characterized by adding the current LOC address and the number of non-terminal nodes before the current node including the current node in the current LOC.

The symbol address may be a value obtained by adding a terminal value corresponding to a current LOC table value and the number of terminal nodes before the current node excluding the current node in the current LOC.

The LOC information table stored in the memory retrieval unit has a node type indicating whether a node indicated by a variable length code is a terminal node, a continuous node, or an invalid node.

Each node type has a LOC information bit of N * {2} ^ {L} bits.

The LOC information bits are represented by four types of A, B, C, and D each consisting of N bits.

The LOC table value stored in the memory is characterized by consisting of LOC information bits corresponding to the node type of the LOC information table indicated by the variable length code.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a block diagram illustrating a variable length code decoding apparatus according to an embodiment of the present invention.

Referring to FIG. 1, the variable length code decoding apparatus 100 according to the first embodiment of the present invention may include a pre-decoding unit 107, a shifting unit 130, and first through M-th lookup table addresses. A register 140, a selector 150, a memory controller 153, a memory 165, and a memory searcher 170 are provided.

The pre-decoding unit 107 receives the data bit stream DSTREAM and selects one of the first to Mth lookup table address registers 140 according to a code value of the data bit stream DSTREAM. 2 Generates the selection signals SEL1 and SEL2.

The pre decoding unit 107 includes a first pre decoding unit 110 and a second pre decoding unit 120.

The first pre-decoding unit 110 receives the data bit stream DSTREAM, and when 0 or 1 is contiguous to the most significant bit MSB of the data bit stream DSTREAM, the first pre decoding unit 110 according to the number of 0 or 1 may be used. A first select signal SEL1 for selecting one of the Mth lookup table address registers 140 is generated.

The second pre-decoder 120 receives the data bit stream DSTREAM and uses the first to Mth lookup tables using N bits (N is a natural number) on the most significant bit MSB side of the data bit stream DSTREAM. A second select signal SEL2 for selecting one of the address registers 140 is generated.

The shifting unit 130 moves the data bit stream DSTREAM by a predetermined bit in response to one of the first selection signal SEL1 or the second selection signal SEL2 and the continuous node signal NCONS. In more detail, the shifting unit 130 moves the data bit stream DSTREAM by L bits in response to the continuous node signal NCONS. Where L may be 3.

The first through M (M is natural numbers) lookup table address registers 140 each include LOC addresses specifying LOC table values (LOCTVs) of K (K is natural numbers) bits stored in the predetermined memory 165.

The selector 150 selects and outputs one of the outputs of the first to Mth lookup table address registers 140 in response to the first selection signal SEL1 or the second selection signal SEL2. The selector 150 may be a multiplexer.

The memory controller 153 receives an output of the selector 150 and selects a LOC table value LOCTV and a terminal value TRMV stored in the memory 165 in response to a predetermined continuous node signal NCONS. The third select signal SEL3 may be generated, or a fourth select signal for selecting a predetermined fixed length code SFLC stored in the memory 165 may be generated in response to a predetermined symbol address signal SYMADDS.

In more detail, the memory controller 153 includes an offset register 155, an adder 160, a LOC address register 175, and a symbol address register 180.

The offset register 155 receives the output of the selector 150 and stores the output of the selector 150 until a new output of the selector 150 is received.

The adder 160 adds the output of the offset register 155 and a predetermined next LOC address NLOCADD to select a third selection signal (LOCTV) and a terminal value (TERMV) stored in the memory 165. SEL3).

The LOC address register 175 generates the next LOC address NLOCADD for selecting the LOC table value LOCTV in response to the continuous node signal NCONS. The next LOC address (NLOCADD) is a sum of the current LOC address and the number of non-terminal nodes before the current node including the current node in the current LOC.

The symbol address register 180 generates a fourth select signal SEL4 for obtaining the fixed length code SFLC in response to the symbol address signal SYMADDS. The symbol address is obtained by adding the terminal value TRMV corresponding to the current LOC table value LOCTV and the number of terminal nodes before the current node except for the current node in the current LOC.

The memory 165 stores the LOC table value LOCTV, the predetermined terminal value TRMV, and the fixed length code SFLC, and selects the selected LOC table value LOCTV and the terminal value in response to the third selection signal SEL3. Outputs the fixed length code SFLC in response to the predetermined fourth selection signal SEL4.

The LOC table value LOCTV stored in the memory 165 includes LOC information bits corresponding to the node type of the LOC information table 200 indicated by the variable length code.

The memory search unit 170 receives the selected LOC table value (LOCTV), the terminal value (TERMV), and the L (L is a natural number) bit of the data bit stream DSTREAM, which are output from the memory 165, and are stored therein. The LC information table 200 determines whether the L bit of the data bit stream DSTREAM is a terminal node or a continuous node to generate a continuous node signal NCONS or a symbol address signal SYMADDS. Where L may be 3.

In addition, the memory search unit 170 receives and outputs a fixed length code SFLC output from the memory 165.

The LOC information table 200 stored in the memory retrieval unit 170 has a node type indicating whether a node indicated by a variable length code is a terminal node, a continuous node, or an invalid node. The type includes LOC information bits of N * {2} ^ {L} bits, and the LOC information bits are represented by four types of A, B, C, and D each consisting of N bits.

In the LOC information table stored in the memory retrieval unit 170, when the variable length code is 0, 1, 00, 01, 10, or 11, the node type indicated by the variable length code is a terminal node, and the variable length code is 000. To 111, the node type indicated by the variable length code is any one of a terminal node, a continuous node, and an invalid node. If N is 2 bits and L is 3 bits, the upper 8 bits of the LOC information bits are represented by ABBB when the variable length code is 0, and the lower 8 bits of the LOC information bits when the variable length code is 1. If the bit is represented by ABBB and the variable length code is 00, the upper 4 bits of the LOC information bit are represented by AB, and if the variable length code is 01, between the upper 5 bits and 8 bits of the LOC information bit is AB. If the variable length code is 10, the upper 9 to 12 bits of the LOC information bits are represented by AB. If the variable length code is 11, the upper 13 to 16 bits of the LOC information bits are represented by AB. When the variable length code is 000 to 111, the LOC information bit is represented by A when the node type indicated by the variable length code is a terminal node, and the LOC information bit is represented by C when the continuous node is a continuous node. If the effective node LOC information bits are represented by D.

In the LOC information table stored in the memory retrieval unit 170, when the variable length code is 0 or 1, the node type indicated by the variable length code is a terminal node, and when the variable length code is present between 00 and 11, The node type indicated by the variable length code is any one of a terminal node, a continuous node, and an invalid node.

If N is 2 bits and L is 2 bits, if the variable length code is 0, the upper 4 bits of the LOC information bits are represented by AB. If the variable length code is 1, the lower 4 bits of the LOC information bits are represented. If the variable length code is 00 to 11 and is represented by AB, the LOC information bit is represented by A when the node type indicated by the variable length code is a terminal node, and the LOC information bit is represented by C when the node is a continuous node. In case of an invalid node, the LOC information bit is represented by D.

FIG. 2 is a diagram illustrating a LOC information table stored in the memory search unit of FIG. 1.

3 is a diagram showing symbols and variable length codes.

4 is a conceptual diagram for obtaining a symbol from a variable length code.

FIG. 5 is a diagram illustrating a LOC table value and a terminal value stored in the memory of FIG. 1.

6 is a diagram illustrating a symbol and a fixed length code.

Hereinafter, the operation of the decoding apparatus of the variable length code according to the embodiment of the present invention will be described in detail with reference to FIGS. 1 to 6.

The data bit stream DSTREAM is stored in the data bit stream storage 105. The data bit stream storage unit 105 applies the data bit stream DSTREAM to the pre decoding unit 107. A data bit stream (DSTREAM) is data information in which data is encoded with a variable length code.

This will be described further with reference to FIG. 3. Symbols may be encoded with a fixed length code in the encoding step or may be encoded with a variable length code.

In fixed length codes, all symbols are encoded with the same number of bits. Variable length codes are encoded with a different number of bits per symbol. You can reduce the number of bits of encoded data by encoding frequently used symbols with fewer bits and encoding less frequently used symbols with more bits.

Therefore, encoding using a variable length code is frequently used. The data bit stream of the present invention is encoded with a variable length code.

The pre decoding unit 107 includes a first pre decoding unit 110 and a second pre decoding unit 120.

The first pre-decoding unit 110, according to the number of zeros or ones, is 0 or 1 in the most significant bit MSB side of the data bit stream DSTREAM, such as a DC coefficient table of MPEG or JPEG. The first selection signal SEL1 selects one of the first to Mth lookup table address registers 140.

That is, the first selection signal SEL1 is 0 in the most significant bit of the data bit stream DSTREAM or 0 in the most significant bit of the data bit stream DSTREAM. If 1 or 4 is less than or equal to 1, one of the first to Mth lookup table address registers 140 is selected according to the characteristics of the data bit stream DSTREAM, such as the second lookup table address register LUTADD1.

When there are no consecutive 0s or 1s as in the AC coefficient table in MPEG, the second pre-decoding unit 120 uses some bits toward the most significant bit MSB of the data bit stream DSTREAM. A second select signal SEL2 for selecting one of the first to Mth lookup table address registers 140 is generated.

If four bits of the most significant bit MSB side are used, the second selection signal SEL2 may have a first lookup table address register LUTADD0, 0001 when the four bits of the most significant bit side of the data bit stream DSTREAM are 0000. Is one of the first to Mth lookup table address registers 140 according to the characteristics of the data bit stream DSTREAM, such as the second lookup table address register LUTADD1 and the third lookup table address register LUTADD2, etc. Select.

In this way, the size of the decoding target is reduced according to the characteristics of the code value of the input data bit stream DSTREAM by distinguishing the first pre decoding unit 110 and the second pre decoding unit 120, thereby reducing power consumption and decoding speed. Also faster.

In this case, whether the user selects whether the first pre-decoding unit 110 or the second pre-decoding unit 120 is to be selected, the data bit stream DSTREAM inputted by the user is grasped, and the information is pre-controlled. When input to, the data bit stream DSTREAM is input to the selected pre decoding unit 107.

The shifting unit 130 shifts the input data bit stream DSTREAM in response to the first selection signal SEL1 or the second selection signal SEL2. If the second pre-decoding unit 120 divides the code value of the input data bit stream DSTREAM by 4 bits and determines the characteristic thereof, the shifting unit 130 responds to the second selection signal SEL2. Shift the stream DSTREAM by 4 bits.

In addition, the shifting unit 130 moves the data bit stream DSTREAM by L bits in response to the continuous node signal NCONS. In an embodiment of the present invention, L may be 3. This will be described later.

The first through Mth lookup table address registers 140 each have a LOC address that specifies a LOC table value (LOCTV) of K (K is a natural number) bits stored in the memory 165.

Referring to FIG. 5, LOC addresses are 0 and 1 indicated by addresses. The LOC table values (LOCTV) are the values marked with Content. That is, when LOC address 0 is selected, 16 bits of 11 10 11 01 11 10 11 11 are selected as the LOC table value (LOCTV) of K bits.

The memory 165 stores the LOC table value LOCTV, and the first to Mth lookup table address registers 140 store the LOC address specifying the LOC table value LOCTV.

The selector 150 selects and outputs one of the outputs of the first to Mth lookup table address registers 140 in response to the first selection signal SEL1 or the second selection signal SEL2. The selector 150 may be a multiplexer.

If the data bit stream DSTREAM is input to the second pre-decoding unit 120, a second selection signal SEL2 is generated and the second selection signal SEL2 is input to the first to Mth lookup table address registers 140. Select one of the stored LOC addresses.

The LOC address selected by the second selection signal SEL2 is input to the memory controller 153. The memory controller 153 selects a LOC table value LOCTV corresponding to the input LOC address.

When the data bit stream DSTREAM is pre-decoded according to the code characteristics of the input data bit stream DSTREAM and the LOC address is selected, decoding the data bit stream DSTREAM using a tree search algorithm. This is done.

The tree search algorithm is performed based on the LOC. An operation of decoding the data bit stream DSTREAM will be described in detail with reference to FIG. 4.

LOC is a group of child nodes connected to one node. A node means a data symbol output by a decoding operation. Nodes have a terminal node and a continuation node. The terminal node is the node finally represented by the data symbol and the continuous node is the node present in the intermediate process of moving to the terminal node. In Fig. 4, the terminal node is indicated by hatching inside and the continuous node has no indication inside.

In the pre-decoding step, the pre-decoding operation is performed according to the characteristics of the code value of the input data bit stream DSTREAM, and the LOC address is selected. At this time, the characteristic of the code value may be determined based on 4 bits of the data bit stream DSTREAM, or the characteristic of the code value may be determined based on 5 bits.

However, the decoding operation divides the data bit stream DSTREAM by L bits. For convenience of explanation, the case where L is 3, that is, the decoding operation is performed by dividing the data bit stream DSTREAM by 3 bits.

The decoding operation of the variable length code decoding apparatus 100 of FIG. 1 receives a data bit stream DSTREAM by three bits, and three bits of the data bit stream DSTREAM are received using the LOC information table 200 of FIG. 2. It is to determine whether it is a node or a continuous node.

The LOC information table of FIG. 2 will be described in more detail. The LOC information table 200 stored in the memory retrieval unit 170 may determine a node type indicating whether a node indicated by a variable length code is a terminal node, a continuous node, or an invalid node, and determine the node type. With LOC information bits that may be present.

Herein, the variable length code refers to a code value of 3 bits of the input data bit stream DSTREAM.

The number of parts indicating the node type in the table of FIG. 2 is a 3-bit data bit stream DSTREAM.

The LOC information table 200 stored in the memory retrieval unit 170 has a node type indicating whether a node indicated by a variable length code is a terminal node, a continuous node, or an invalid node. The node type has LOC information bits of N * {2} ^ {L} bits. The LOC information bits are expressed in four forms, A, B, C, and D, each consisting of N bits.

In the LOC information table 200 of FIG. 2, the LOC information bits are represented by four types of A, B, C, and D, which consist of 2 bits. That is, A is 11, B is 10, C is 01, and D is 00. That is, N is two. This is for convenience of description and N is not limited to two. In the following description, 11, 10, 01, and 00 are used instead of A, B, C, and D, respectively.

Since N is 2 and L is 3, the node type eventually has 2 * {2} ^ {3} = 16 bits of LOC information bits.

If the most significant bit of the 3 bits of the data bit stream DSTREAM is 0, and the LOC table value stored in the memory 165 is equal to the LOC information bits of the LOC information table 200, the 3 bits of the data bit stream DSTREAM The most significant bit of zero is the terminal node.

Referring to the LOC information table 200 stored in the memory retrieval unit 170, if three bits of the input data bit stream DSTREAM include 0, 1, 00, 01, 10, 11, 0, 1, 00, Nodes indicated by 01, 10, and 11 become terminal nodes.

If three bits of the data bit stream (DSTREAM) are present between 000 and 111, the node indicated by the data bit stream (DSTREAM) between 000 and 111 indicates a terminal node, a continuous node, and an invalid node according to the LOC information bits, respectively. Can be represented. The terminal node, the continuous node, and the invalid node each have 16 bits of LOC information bits.

If the most significant bit of the input data bit stream DSTREAM is 0 and the node indicated by 0 is a terminal node, the 0 terminal node has 11, 10, 10, 10 in the upper 8 bits of the LOC information bit.

If the most significant bit of the input data bit stream DSTREAM is 1 and the node indicated by 1 is a terminal node, one terminal node has 11, 10, 10, 10 in the lower 8 bits of the LOC information bit.

If the upper two bits of the input data bit stream DSTREAM are 00 and the node indicated by 00 is a terminal node, the 00 terminal node has 11 and 10 in the upper four bits of the LOC information bit.

If the upper two bits of the input data bit stream DSTREAM are 01 and the node indicated by 01 is a terminal node, the 01 terminal node has 11 and 10 between the upper five bits and eight bits of the LOC information bit.

If the upper 2 bits of the input data bit stream DSTREAM are 10 and the node indicated by 10 is a terminal node, the 10 terminal node has 11 and 10 between the upper 9 and 12 bits of the LOC information bit.

If the upper two bits of the input data bit stream DSTREAM are 11 and the node indicating 11 is a terminal node, the 11 terminal node has 11 and 10 between the upper 13 and 16 bits of the LOC information bit.

If the three bits of the input data bit stream DSTREAM are one of 000 to 111 and the node indicated is a terminal node, the terminal node indicated by the three bits has 11.

If the three bits of the input data bit stream DSTREAM are one of 000 to 111, and the node indicated is a continuous node, the continuous node indicated by the three bits has 01.

If the three bits of the input data bit stream DSTREAM are one of 000 to 111 and the node indicated is an invalid node, the invalid node indicated by the three bits has 00.

The LOC table value LOCTV stored in the memory 165 is obtained using the conceptual diagram of FIG. 4 and the LOC information table 200 of FIG. 2.

Referring to FIG. 4, when the input data bit stream DSTREAM is 00, 00 in FIG. 4 indicates a terminal node c. It can be seen that the LOC information bits at this time are indicated by 11 10 in the LOC information table 200 of FIG. 2. This value is recorded in the Content portion representing the LOC table value LOCTV in FIG.

When the input data bit stream DSTREAM is 010, 010 in FIG. 4 indicates a terminal node f. It can be seen that the LOC information bits at this time are indicated by 11 in the LOC information table 200 of FIG. 2. This value is recorded after 11 and 10 of the Content part representing the LOC table value (LOCTV) in FIG.

When the input data bit stream DSTREAM is 011, 011 in FIG. 4 indicates a continuous node. It can be seen that the LOC information bits at this time are indicated by 01 in the LOC information table 200 of FIG. This value is recorded after 11, 10, and 11 of the Content portion representing the LOC table value (LOCTV) in FIG.

When the input data bit stream DSTREAM is 10, the 10 branches of FIG. 4 indicate the terminal node a. It can be seen that the LOC information bits at this time are indicated by 11 10 in the LOC information table 200 of FIG. 2. This value is recorded after 11, 10, 11, and 01 of the Content portion representing the LOC table value (LOCTV) in FIG.

When the input data bit stream DSTREAM is 110, 110 branches of FIG. 4 indicate the terminal node g. It can be seen that the LOC information bits at this time are indicated by 11 in the LOC information table 200 of FIG. 2. This value is recorded after 11, 10, 11, 01, 11, and 10 of the Content portion representing the LOC table value (LOCTV) in FIG.

When the input data bit stream DSTREAM is 111, 111 in FIG. 4 indicates a terminal node b. It can be seen that the LOC information bits at this time are indicated by 11 in the LOC information table 200 of FIG. 2. This value is recorded after 11, 10, 11, 01, 11, 10, 11 of the Content portion representing the LOC table value (LOCTV) in FIG.

Then all LOC table values corresponding to LOC 0 are completed. LOC address 0 corresponds to LOC 0, and LOC address 1 corresponds to LOC 1. LOC table values (LOCTV) can also be obtained for variable-length codes 0 and 1 indicated on branches from LOC 0 continuous nodes to LOC 1.

In Figure 4 R is the root node. Branches are connected to LOC 0 at the root node, and each branch has an input data bit stream (DSTREAM) in the form of variable length code. The variable length code is shown in FIG.

The smaller logical values of variable length codes are placed on the left and the larger on the right. If the variable length code is 4 bits, the first 3 bits indicate the continuous node, and the last 1 bit of the variable length code from the continuous node indicates the terminal node.

Since the variable length code shown in FIG. 3 is merely an example, the variable length code indicating the symbol a does not necessarily need to be 00. If the variable length code is different from that of FIG. 3, the conceptual diagram of FIG. 4 will also be different. The table of FIG. 5 shows the LOC table value (LOCTV) stored in the memory 165.

The portion indicated by the address indicates the LOC address and is stored in the first to Mth lookup table address registers 140.

The input data bit stream DSTREAM may have various code values. If the 3 bits of the input data bit stream DSTREAM are not one of 00, 010, 011, 10, 110, and 111 of FIG. 4, the data bit stream DSTREAM is an invalid data bit stream DSTREAM and is processed by an interrupt.

A case where the data bit stream DSTREAM is 011000 .... will be described as an example.

When the LOC address value 0 is output from the selector 150 by the first select signal SEL1 or the second select signal SEL2, the value is stored in the offset register 155.

The case where the LOC address is 0 among the LOC table values LOCTV stored in the memory 165 is selected.

The LOC table value (LOCTV) is 11, 10, 11, 01, 11, 10, 11, 11 and 3 bits of the input data bit stream DSTREAM are 011. If the data bit stream (DSTREAM) is 00, 010, 011, 10, 110, and 111, the LOC table value (LOCTV) is valid. If the data bit stream (DSTREAM) is 011, Valid input value. Also, as can be seen in the conceptual diagram of FIG. 4, the node indicated by the data bit stream (DSTREAM) 011 is not a terminal node but a continuous node. The memory search unit 170 generates a continuous node signal NCONS.

The LOC address register 175 of the memory controller 153 receives the continuous node signal NCONS to generate the next LOC address NLOCADD.

The next LOC address (NLOCADD) is a sum of the current LOC address and the number of non-terminal nodes before the current node including the current node in the current LOC. The number of non-terminal nodes before the current node, including the current node in the current LOC, since the current LOC address is 0 and there are only one 011 node in front of it, including nodes that point to 011 within the current LOC. Is 1 Therefore, the next LOC address (NLOCADD) is one.

In this case, the shifting unit 130 moves the data bit stream DSTREAM input by 3 bits in response to the continuous node signal NCONS. Therefore, the data bit stream DSTREAM is 000. The adder 160 adds the value 0 stored in the offset register 155 and the next LOC address 1 to output the third selection signal SEL3 as 1.

The first LOC address 0 stored in the offset register 155 remains the same until the data bit stream DSTREAM specifies a terminal node and is decoded to a symbol value. When the input data bit stream DSTREAM is decoded into a symbol value, a new LOC address is again selected by the first or second pre decoding unit 120 and the new LOC address is stored in the offset register 155.

The third select signal SEL3 selects the case where the LOC address is 1 from the LOC table value LOCTV stored in the memory 165 and applies the selected LOC address to the memory search unit 170. In addition, the third selection signal SEL3 selects the terminal value TRMV stored in the memory 165 and applies it to the memory search unit 170.

The memory search unit 170 receives 3 bits of the LOC table value LOCTV, the terminal value TRMV, and the data bit stream DSTREAM output from the memory 165.

The LOC table value (LOCTV) is 11, 10, 10, 10, 11, 10, 10, 10 and 3 bits of the input data bit stream DSTREAM are 000. Referring to the LOCTV value (LOCTV), if the input data bit stream (DSTREAM) is 0 or 1, it can be known as a valid input. The upper 0 value of the input data bit stream (DSTREAM) 000 is a valid input value.

4, the node indicated by the data bit stream DSTREAM 0 is a terminal node. It can be seen from the diagram of FIG. 5 that the terminal value TRMV is five. The terminal value TRMV is stored in the memory 165. The terminal value TRMV is the number of terminal nodes before LOC 1 corresponding to the case where the LOC address is 1. If the LOC address is 1, the terminal value is 5. If the LOC address is zero, the terminal value (TERMV) is zero.

The memory search unit 170 receives a terminal value TRMV output from the memory 165, selects a symbol address stored therein, and generates a symbol address signal SYMADDS corresponding to the selected symbol address.

The symbol address is a value obtained by adding a terminal value corresponding to a current LOC table value and the number of terminal nodes before the current node excluding the current node in the current LOC. The terminal value TRMV corresponding to the current LOC table value is 5, and the number of terminal nodes before the current node except for the current node in the current LOC is 0. That is, the symbol address is five.

6 shows a symbol address, a fixed length code and a symbol. Since the symbol address is 5, the memory search unit 170 generates a symbol address signal SYMADDS for selecting the symbol e.

The symbol address register 180 stores the symbol address signal SYMADDS and generates the symbol address signal SYMADDS as a fourth select signal SEL4 for obtaining the fixed length code SFLC.

The fourth selection signal SEL4 is applied to the memory 165, stored in the memory 165, and outputs a fixed length code SFLC corresponding to the symbol e.

Then, the memory search unit 170 receives the fixed length code SFLC output from the memory 165 and outputs it.

By the above-described process, the variable length code decoding apparatus 100 of the present invention can decode a data bit stream DSTREAM having a variable length code by 3 bits, thereby increasing the decoding speed. In addition, by using the first pre-decoding unit 110 and the second pre-decoding unit 120, it is possible to reduce the overall power consumption by reducing the size of the target table to be decoded according to the characteristics of the code value of the input data bit stream.

In order to decode the data bit stream DSTREAM by three bits, a table having the same structure as that of the LOC information table 200 of FIG. 2 should be created, and A and B representing the LOC information bits of the LOC information table 200 of FIG. 2. , C and D are represented by 2 bit digital values. However, A, B, C, and D representing the LOC information bits are not necessarily limited to 2 bits.

For example, the data bit stream DSTREAM may be decoded by 2 bits. At this time, if the bits representing A, B, C, and D are 2 bits, that is, if N is 2, the LOC information bits have 2 * {2} ^ {2} = 8 bits.

Then, the LOC information table of FIG. 2 will be changed as follows. That is, when the variable length code is 0 and 1, the node type indicated by the variable length code is a terminal node. When the variable length code is present between 00 and 11, the node type indicated by the variable length code is determined by the terminal node. It is either a continuous node or an invalid node.

If the variable length code is 0, the upper 4 bits of the LOC information bits are represented by AB. If the variable length code is 1, the lower 4 bits of the LOC information bits are represented by AB. In case of 11, LOC information bit is represented by A when the node type indicated by the variable length code is a terminal node, LOC information bit is represented by C when the node is a continuous node, and LOC information bit is D by an invalid node. Will be expressed.

7 is a flowchart illustrating a method of decoding a variable length code according to a first embodiment of the present invention for achieving another technical problem.

8 is a flowchart illustrating operation 710 of FIG. 7.

Referring to FIG. 7, the variable length code decoding method 700 according to the first embodiment of the present invention may include first to Mth lookup table address registers each having a predetermined LOC address, and the LOC. A variable length having a memory retrieval unit having a LOC table value of K (K is a natural number) bit corresponding to an address, a memory storing a predetermined terminal value, and a LOC information table having information as a reference for decoding a variable length code A variable length code decoding method of a code decoding apparatus, receiving a data bit stream and generating a first or second selection signal for selecting one of the lookup table address registers according to a code value of the data bit stream. step)

In more detail, step 710 may include a first selection of selecting one of the plurality of lookup table address registers according to the number of 0s or 1s when 0s or 1s are contiguous to the most significant bit MSB of the data bit stream. Generate a signal (step 810).

A second selection signal for selecting one of the plurality of lookup table address registers is generated using N bits (N is a natural number) of the most significant bit (MSB) side of the data bit stream (step 820).

The data bit stream is shifted by a predetermined bit in response to one of the first selection signal or the second selection signal and the continuous node signal (step 830).

In response to the first selection signal or the second selection signal, one of the outputs of the first to Mth lookup table address registers is selected and output (step 720).

The output of step 720 and the following LOC address are added to generate a third selection signal for selecting a value of a LOC table stored in the memory and a terminal value corresponding to the LOC table value to obtain a predetermined symbol address. Step) The next LOC address is characterized by adding the current LOC address and the number of non-terminal nodes before the current node including the current node in the current LOC.

The selected LOC table value and the terminal value are output in response to the third selection signal (step 740). The selected LOC table value, the terminal value and the L bit of the data bit stream are output from the memory, and the LOC is received. A continuous node signal or a symbol address signal is generated by determining whether the L bit of the data bit stream is a terminal node or a continuous node using an information table. (Step 750) The continuous node signal generates the data bit stream by 3 bits. You can move it.

The next LOC address for selecting the LOC table value is generated in response to the continuous node signal, and is applied to step 730. (Step 760) A fourth selection signal for obtaining a fixed length code in response to the symbol address signal. (Step 770).

The fixed length code is output from the memory in response to the fourth selection signal (step 780).

The symbol address may be a value obtained by adding a terminal value corresponding to a current LOC table value and the number of terminal nodes before the current node excluding the current node in the current LOC.

Since the LOC information table stored in the memory searching unit is the same as the LOC information table of the first embodiment, detailed description thereof will be omitted.

The LOC table value stored in the memory is characterized by consisting of LOC information bits corresponding to the node type of the LOC information table indicated by the variable length code. In an embodiment of the present invention, L may be 3.

The variable length code decoding method 700 of FIGS. 7 and 8 corresponds to the operation of the variable length code decoding apparatus 100 of FIG. 1. Therefore, a detailed description of the operation of the variable length code decoding method 700 is omitted.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the apparatus and method for variable-length code decoding according to the present invention decodes the input data bit stream by 3 bits so that fast decoding is possible, and pre-decoding is performed according to the characteristics of the code value of the input data bit stream. As a result, the overall power consumption can be reduced by reducing the size of the target table to be decoded.

Claims (19)

A pre-decoding unit for receiving a data bit stream and generating a first or second selection signal for selecting one of predetermined first to Mth lookup table address registers according to a code value of the data bit stream; A shifting unit for shifting the data bit stream by a predetermined bit in response to one of the first selection signal or the second selection signal and a predetermined continuous node signal; First to Mth lookup table address registers each having a LOC address specifying a LOC table value of K (K is a natural number) bits stored in a predetermined memory; A selector configured to select and output one of outputs of the first to Mth lookup table address registers in response to the first selection signal or the second selection signal; A third selection signal for receiving an output of the selection unit and selecting a terminal value corresponding to the LOC table value stored in the memory and the LOC table value and obtaining a predetermined symbol address in response to a predetermined continuous node signal; A memory control section for generating a fourth selection signal for selecting a predetermined fixed length code stored in the memory in response to a predetermined symbol address signal; Store the LOC table value, the terminal value and the fixed length code, output the selected LOC table value and the terminal value in response to the third selection signal, or output the fixed length code in response to the fourth selection signal. The memory for outputting; And Receives the L (L is a natural number) bit of the selected LOC table value, the terminal value, and the data bit stream output from the memory, and L bits of the data bit stream are stored using an internally stored LOC information table. Determine whether it is a terminal node or a continuous node to generate a continuous node signal or a symbol address signal, And a memory retrieval unit for receiving and outputting the fixed length code output from the memory. The method of claim 1, wherein the pre-decoding unit, Receiving one of the data bit streams and selecting one of the first to Mth lookup table address registers according to the number of zeros or ones when 0 or 1 is consecutive to the most significant bit (MSB) of the data bit stream; A first pre decoding section for generating a first selection signal; And A second selection signal for receiving the data bit stream and selecting one of the first to Mth lookup table address registers using N (N is a natural number) bit of the most significant bit (MSB) side of the data bit stream; And a second pre decoding unit for generating. The method of claim 1, wherein the shifting unit, And varying the data bit stream by three bits in response to the continuous node signal. The method of claim 1, wherein the memory control unit, An offset register for receiving the output of the selector and storing the output of the selector until a new output of the selector is received; A summation section for generating a third selection signal for selecting values of the LOC table stored in the memory by adding the output of the offset register and a predetermined next LOC address; A LOC address register for generating said next LOC address for selecting a LOC table value in response to said continuous node signal; And And a symbol address register for generating said fourth select signal for obtaining said fixed length code in response to said symbol address signal. The method of claim 4, wherein the next LOC address, And a number of non-terminal nodes before the current node including the current node in the current LOC address and the current LOC. The method of claim 1, wherein the symbol address is, And a terminal value corresponding to a current LOC table value and a number of terminal nodes before a current node excluding a current node in a current LOC. The LOC information table stored in the memory search unit, A node type indicating whether a node indicated by a variable length code is a terminal node, a continuous node, or an invalid node, Each node type has a LOC information bit of N * {2} ^ {L} bits. And the LOC information bits are represented by four types of A, B, C, and D each consisting of N bits. The LOC information table stored in the memory search unit, When the variable length code is 0, 1, 00, 01, 10, 11, the node type indicated by the variable length code is a terminal node, and when the variable length code is present between 000 and 111, the variable length code indicates Node type is one of terminal node, continuous node and invalid node, If N is 2 bits and L is 3 bits, If the variable length code is 0, the upper 8 bits of the LOC information bits are represented by ABBB. If the variable length code is 1, the lower 8 bits of the LOC information bits are represented by ABBB. If the upper 4 bits of the LOC information bits are represented by AB, and the variable length code is 01, between the upper 5 bits and the 8 bits of the LOC information bits are represented by AB, and when the variable length code is 10, the LOC information bits When the upper 9 bits to 12 bits are represented by AB, and when the variable length code is 11, the upper 13 bits to 16 bits of the LOC information bit are represented by AB, If the variable length code is 000 to 111, the LOC information bit is represented by A when the node type indicated by the variable length code is a terminal node, and the LOC information bit is represented by C when the node is a continuous node, and LOC when the node is invalid. And an information bit is represented by D. The LOC information table stored in the memory search unit, When the variable length code is 0 or 1, the node type indicated by the variable length code is a terminal node. When the variable length code is present between 00 and 11, the node type indicated by the variable length code is a terminal node and a continuous node. And the invalid node, If N is 2 bits and L is 2 bits, If the variable length code is 0, the upper 4 bits of the LOC information bits are represented by A B. If the variable length code is 1, the lower 4 bits of the LOC information bits are represented by A B. If the variable length code is 00 to 11, the LOC information bit is represented by A when the node type indicated by the variable length code is a terminal node, and the LOC information bit is represented by C when the node is a continuous node, and is an invalid node. And a LOC information bit is represented by D. The method of claim 1, wherein the LOC table value stored in the memory, And a plurality of LOC information bits corresponding to a node type of the LOC information table indicated by a variable length code. The method of claim 1, wherein the selection unit, A variable length code decoding apparatus, characterized in that the multiplexer. A first through Mth lookup table address registers each having a predetermined LOC address, a LOC table value of K (K is a natural number) bits corresponding to the LOC address, a predetermined terminal value, and a fixed length code. A variable length code decoding method of a variable length code decoding apparatus, comprising: a memory retrieving unit having a memory to store and a LOC information table having information as a reference for decoding a variable length code; (a) receiving a data bit stream and generating a first or second selection signal for selecting one of the lookup table address registers according to a code value of the data bit stream; (b) selecting and outputting one of the outputs of the first to Mth lookup table address registers in response to the first selection signal or the second selection signal; (c) a third selection signal for selecting a terminal value for obtaining a predetermined symbol address corresponding to the LOC table value and the LOC table value stored in the memory by adding the output of step (b) and a predetermined next LOC address; Generating a; (d) outputting a selected LOC table value and a terminal value in response to the third selection signal; (e) receiving the selected LOC table value, the terminal value and the L bit of the data bit stream output from the memory, and using the LOC information table, whether the L bit of the data bit stream is a terminal node or a continuous node; Judging and generating a continuous node signal or a symbol address signal; (f) generating the next LOC address for selecting the LOC table value in response to the continuous node signal; (g) generating a fourth selection signal for obtaining the fixed length code in response to the symbol address signal; And and (h) outputting the fixed length code from the memory in response to the fourth selection signal. The method of claim 12, wherein step (a) comprises: (a1) generating a first selection signal for selecting one of the plurality of lookup table address registers according to the number of zeros or ones when zeros or ones are contiguous with the most significant bit (MSB) of the data bit stream; (a2) generating a second selection signal for selecting one of the plurality of lookup table address registers using N (N is a natural number) bit of the most significant bit (MSB) side of the data bit stream; And (a3) varying the length of the data bit stream by a predetermined bit in response to one of the first selection signal or the second selection signal and the continuous node signal; Code decryption method. The method of claim 12, wherein the next LOC address, A variable length code decoding method of a variable length code decoding apparatus, characterized by adding a current LOC address and a number of non-terminal nodes before a current node including a current node in a current LOC. The method of claim 12, wherein the symbol address, And a terminal value corresponding to a current LOC table value and the number of terminal nodes before the current node excluding the current node in the current LOC. The LOC information table stored in the memory search unit, A node type indicating whether a node indicated by a variable length code is a terminal node, a continuous node, or an invalid node, Each node type has a LOC information bit of N * {2} ^ {L} bits. And the LOC information bits are represented by four types of A, B, C, and D each consisting of N bits. The method of claim 16, wherein the LOC information table stored in the memory search unit, When the variable length code is 0, 1, 00, 01, 10, 11, the node type indicated by the variable length code is a terminal node, and when the variable length code is present between 000 and 111, the variable length code indicates Node type is one of terminal node, continuous node and invalid node, If N is 2 bits and L is 3 bits, If the variable length code is 0, the upper 8 bits of the LOC information bits are represented by ABBB. If the variable length code is 1, the lower 8 bits of the LOC information bits are represented by ABBB. If the upper 4 bits of the LOC information bits are represented by AB, and the variable length code is 01, between the upper 5 bits and the 8 bits of the LOC information bits are represented by AB, and if the variable length code is 10, the LOC information bits When the upper 9 bits to 12 bits are represented by AB, and when the variable length code is 11, the upper 13 bits to 16 bits of the LOC information bit are represented by AB, If the variable length code is 000 to 111, the LOC information bit is represented by A when the node type indicated by the variable length code is a terminal node, and the LOC information bit is represented by C when the node is a continuous node, and is an invalid node. And a LOC information bit is represented by D. The method of claim 16, wherein the LOC information table stored in the memory search unit, When the variable length code is 0 or 1, the node type indicated by the variable length code is a terminal node. When the variable length code is present between 00 and 11, the node type indicated by the variable length code is a terminal node and a continuous node. And the invalid node, If N is 2 bits and L is 2 bits, If the variable length code is 0, the upper 4 bits of the LOC information bits are represented by A B. If the variable length code is 1, the lower 4 bits of the LOC information bits are represented by A B. If the variable length code is 00 to 11, the LOC information bit is represented by A when the node type indicated by the variable length code is a terminal node, and the LOC information bit is represented by C when the node is a continuous node, and is an invalid node. And a LOC information bit is represented by D. The method of claim 12, wherein the LOC table value stored in the memory, And a LOC information bits corresponding to the node type of the LOC information table indicated by the variable length code.