KR20040009586A - Method and apparatus for eliminating glitch - Google Patents

Abstract

PURPOSE: A method and an apparatus for removing a glitch are provided to minimize the distortion of an input signal due to the increase of the pulse width by improving a process for removing the glitch. CONSTITUTION: An apparatus for removing a glitch includes an edge detector(21), an n-bit counter(22), an overflow generator(23), and a selector(24). The edge detector(21) is used for detecting an edge of an input signal and supplying a count start signal. The n-bit counter(22) performs a counting operation by synchronizing with a main clock according to count start signal and a count setup value. The overflow generator(23) is used for generating a count stop signal when a count output value of the n-bit counter(22) approaches a predetermined value. The selector(24) is used for outputting selectively the input signal and the output signal according to the count stop signal.

Description

Method and apparatus for eliminating glitch {Method and apparatus for eliminating glitch}

The present invention relates to a glitch removal method and apparatus, and more particularly, to a glitch removal method and apparatus for minimizing distortion of an input signal due to an increase in a pulse width recognized as a glitch during glitch removal.

Carriage Return (weak CR) of the inkjet printer The encoder sensor used to control the position or speed of the motor is pulsed along the strip bar while moving the upper part of the encoder strip bar in which a plurality of slits are formed at predetermined intervals. Output the signal. At this time, when the motor transitions to the stationary state in the deceleration section, a glitch having a period that is significantly shorter than the output signal of the encoder sensor of the previous period is generated by the repulsive force or the back-lash.

1 is a circuit diagram illustrating a conventional glitch elimination circuit, in which first to third D flip flops 11, 12 and 13 and first to third D flip flops 11, 12 and 13 are latched to latch an input signal. A clock generator 14 for generating a clock of the clock, an ora gate 15 and an AND gate 16 for gating the outputs of the first to third D flip-flops 11, 12 and 13 to the active level of the input signal. Is done.

The operation of the first to third D flip-flops 11, 12, and 13 may be based on the input signal and the first D flip-flop 11 according to the clock signal MCLK output from the clock generator 14, respectively. And the output signal of the second D flip-flop 12 are latched to supply the latched signal to the rear stage. The oragate 15 outputs a high active level signal from which glitches are removed by using the output signals of the first to third D flip-flops 11, 12, and 13 as inputs. On the other hand, the AND gate 16 inputs the output signals of the first to third D flip-flops 11, 12, and 13 to output a low active level signal from which glitches are removed.

With the above configuration, the glitches having a width smaller than the maximum value (Wm) of the glitch removal width, that is, (the number of flip flops (N1) * clock period (T1) of the flip flops) can be removed. By using the clock divided by the clock signal MCLK as the flip-flop clock, the desired glitch removal width can be increased. However, since the period is distorted by the sampling resolution, that is, the flip-flop clock, than the input signal, the glitch-reduced signal increases the amount of distortion in the period by using the divided clock.

On the other hand, if the clock of the flip-flop is used as the main clock (MCLK) and the glitch elimination width is increased, the number of flip-flops and the logic of the ora gate and the end gate are greatly increased. For example, if the glitch rejection width is 3us and the clock is 66MHz, 198 flip-flops are required, which increases the complexity of the system logic by requiring an oragate and an end gate with 198 inputs. .

However, in the case of the CR motor of the inkjet printer, since the period of the signal output from the encoder sensor is not only an important factor in controlling the speed of the CR motor but also a base of the window time, the distortion of the period of the signal output from the encoder sensor is This is an important factor in system performance degradation. In addition, as the system is developed in a direction that requires miniaturization and high-speed processing, errors caused by these glitches have a greater impact on the system.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method and an apparatus for removing glitches, which may be removed regardless of whether a glitch is included in a high or low level signal.

Another technical problem to be achieved by the present invention is to provide a method and apparatus for removing glitches such that a signal having a glitch removed has a minimum delay time corresponding to a set glitch removal width compared to an input signal.

1 is a circuit diagram illustrating a conventional glitch elimination circuit;

Figure 2 is a block diagram showing the configuration of a glitch removal apparatus according to an embodiment of the present invention,

3A and 3B are waveform diagrams of respective parts in FIG. 2, and

4 is a block diagram showing the configuration of a motor control system using the glitch removal device shown in FIG.

* Explanation of symbols for main parts of the drawings

21 ... edge detector 23 ... n-bit counter

25 ... overflow detection part 27 ... selection part

31 ... encoder strip bar 33 ... encoder sensor

35 ... glitch remover 37 ... motor-drive section

39 ... motor

In order to achieve the above technical problem, the glitch removing method according to the present invention includes the steps of: (a) determining a count setting value according to a main clock and a desired glitch removing width; (b) detecting an edge of the input signal; (c) starting counting in synchronization with the main clock according to the count start signal and the count setting value generated every time an edge is detected in step (b); (d) stopping counting according to a count stop signal generated whenever the count output value reaches a predetermined value in step (c); And (e) selectively outputting a current input signal when the count stop signal is generated and a previous output signal when the count stop signal is not generated.

In order to achieve the above technical problem, an apparatus for removing glitch according to the present invention may include: an edge detector detecting an edge of an input signal and supplying the count start signal every time the edge is detected; An n-bit counter that starts counting in synchronization with the main clock according to the count start signal and the count setting value and stops counting according to the count stop signal; An overflow generator for generating a count stop signal and supplying the count stop signal to the n-bit counter whenever the count output value of the n-bit counter reaches a predetermined value; And a selector configured to selectively output one of the input signal and the previous output signal according to the count stop signal.

Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 2 is a block diagram showing the glitch removing apparatus according to the present invention, which comprises an edge detector 21, an n-bit counter 23, an overflow detector 25, and a selector 27.

The edge detector 31 detects the rising edge and the falling edge of the input signal a and applies it to the counter 33 as the count start signal b.

The n-bit counter 33 is composed of a down counter or an up counter. In the case of the down counter, the n-bit counter 33 is set from the set count initial value K to the main clock MCLK according to the count start signal b output from the edge detector 31. Down counting is started in synchronization with the control signal, and counting ends in accordance with the count stop signal d output from the overflow detection unit 35. On the other hand, in the up counter, according to the count start signal b, up counting is started up in synchronization with the main clock MCLK up to the set count end value K, and the count stop signal output from the overflow detector 35 is output. Counting ends according to (d). The count initial value or count end value (K) is determined as the nearest integer from the product of the main clock (MCLK) and the desired glitch elimination width (W), multiplied by the main clock (MCLK) and the glitch elimination width (W). The number of bits n of the counter designed accordingly is determined. When the number of bits n of the counter is determined, the glitch having a width corresponding to a maximum of 2 ⁿ × (1 / MCLK) can be removed according to the count initial value or the count end value K.

The overflow detection unit 35 counts the count stop signal d when the output value c of the counter 33 becomes "0" for the down counter or reaches the count end value K for the up counter. Output to 33 and selector 35, respectively.

The selector 37 selects and outputs one of the previous output signal e and the input signal a according to the count stop signal d applied as the selection control signal. That is, when the count stop signal d is generated, the current input signal a is selected, and if not, the previous output signal e is selected and output.

The operation according to the above configuration will be described with reference to the waveform diagrams shown in FIGS. 3A and 3B.

3A and 3B illustrate an example in which the glitch is included in the low level and the high level, respectively, (a) is an input signal, (b) is an output signal of the edge detector 21, and (c) is a counter 23. ), (D) denotes the output signal of the overflow detection unit 25, and (e) denotes the output signal of the selection unit 27, respectively. Here, the set glitch removal width is W, the glitch width of the input signal is W1, the signal width of the low or high level after the glitch is W2, and the signal width of the high or low level is W3, and the counter 23 An example is an 8-bit down counter.

In FIG. 3A, when an input signal a including a glitch having a width equal to W1 is applied to the edge detector 21 in the low level signal, the edge detector 21 detects the rising and falling edges of the glitch. To output the signal (b). The counter 23 starts down counting from the count initial value K at the rising edge of the glitch, continues the previous counting at the falling edge of the glitch, and starts counting down from the count initial value K again. At this time, the overflow generator 25 does not generate the counter stop signal d, and the selector 27 continuously selects and outputs the previous output signal e having a low level, and the glitch is removed.

Next, looking at the low level signal having a width as wide as W2, the counter 23 starts counting down from the falling edge of the glitch, and the output value (c) becomes "0" in the section corresponding to the count initial value (K). If so, the overflow detector 25 detects this and applies the signal (d) to the counter 23 as a count stop signal. The counter 23 stops counting until the next count start signal is applied. The selector 27 selects the previous output signal at the low level until the count stop signal d is generated, and selects and outputs the current input signal a at the low level when the counter stop signal d is generated. The low level is maintained until the next count stop signal d is generated.

Next, looking at the high level signal having the width W3, the counter 23 starts down counting from the rising edge of the high level signal, and the output value c is "0" in the section corresponding to the count initial value K. If so, the overflow detection unit 25 detects this and applies the signal (d) to the counter 23 as a count stop signal. The counter 23 stops counting until the next count start signal is applied. The selector 27 selects the previous output signal at the low level until the count stop signal d is generated, and selects and outputs the current input signal a at the high level when the counter stop signal d is generated. The high level is maintained until the next count stop signal d is generated.

The above description of FIG. 3A applies equally to FIG. 3B of the input signal a including the glitch having a width equal to W1 in the high level signal.

When comparing the input signal a and the output signal e with reference to FIGS. 3A and 3B, glitches having a width W1 smaller than the glitch elimination width W are removed and larger than the glitch elimination width W. FIG. While the signals having the widths W2 and W3 are maintained, the output signal e is delayed by approximately the glitch removal width W with respect to the input signal a.

On the other hand, the glitch removal width W is determined according to the main clock MCLK of the counter 23 and the number of bits n or the count initial value or end value K of the counter 23 as described above. For example, if the main clock is 66MHz and using an 8-bit counter, the maximum glitch rejection width (W) is approximately 3.88us.

FIG. 4 is a block diagram showing the configuration of the motor control system using the glitch removing device shown in FIG. 2, which includes an encoder slit 41, an encoder sensor 43, a glitch removing unit 45, a motor driving unit 47, and a CR. It consists of a motor 49.

The encoder strip bar 41 has a plurality of slits formed at predetermined intervals, and the encoder sensor 43 is attached to the print head and moves the upper portion of the encoder strip bar 41 according to the printing operation of the print head. Output pulse signal according to

The glitch removal unit 45 removes the glitch below the set glitch removal width and delays the set glitch removal width with respect to the pulse signal output from the encoder sensor 43, and the motor driver 47 removes the glitch. The CR motor 49 is driven using the pulse signal.

As described above, according to the present invention, it is possible to remove a glitch smaller than the set glitch elimination width regardless of the signal level including the glitch, and to output a signal in which the glitch is removed is delayed by approximately the set glitch elimination width. Logic can minimize the period distortion of the input signal.

In addition, by eliminating the glitches while minimizing the period distortion of the input signal, it is possible to significantly improve the accuracy of the speed control of the carriage return (CR) motor of the system using this as an input.

Although the present invention has been described with reference to the above embodiments, it is merely illustrative, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. . Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (7)

(a) determining a count set value according to the main clock and the desired glitch rejection width; (b) detecting an edge of the input signal; (c) starting counting in synchronization with the main clock according to the count start signal and the count setting value generated every time an edge is detected in step (b); (d) stopping counting according to a count stop signal generated whenever the count output value reaches a predetermined value in step (c); And and (e) selectively outputting a current input signal when the count stop signal is generated, and outputting a previous output signal when the count stop signal is not generated. The method of claim 1, wherein the count stop signal is generated whenever the count output value becomes “0” when the count set value is an initial count value. The method according to claim 1, wherein the count stop signal is generated whenever the count set value is a count end value, and the count stop signal is generated whenever the count output value becomes a count end value. An edge detector which detects an edge of the input signal and supplies the count start signal at every edge detection; An n-bit counter that starts counting in synchronization with the main clock according to the count start signal and the count setting value and stops counting according to the count stop signal; An overflow generator for generating a count stop signal and supplying the count stop signal to the n-bit counter whenever the count output value of the n-bit counter reaches a predetermined value; And And a selector for selectively outputting one of the input signal and the previous output signal according to the count stop signal. 5. The apparatus of claim 4, wherein the count setting value is determined according to a desired glitch rejection width and a main clock of the n-bit counter. The apparatus of claim 4, wherein the n-bit counter comprises a down counter, the count setting value is a count initial value, and the count stop signal is generated when the count output value is "0". . 5. The apparatus of claim 4, wherein the n-bit counter comprises an up counter, the count setting value is a count end value, and the count stop signal is generated when the count output value is the count end value. .