KR20040008495A - Delay time control device for minimizing the delay time change - Google Patents

Abstract

PURPOSE: A delay circuit of an integrated circuit is provided to minimize the variation of a delay time according to temperature by compensating the variation of a bias voltage according to temperature variation of a delay unit. CONSTITUTION: A delay control unit(10,20) generates a control voltage to compensate bias voltage variations of delay units using current variation due to temperature variation. And a delay part(30) comprises a plurality of delay units which delays an input signal and then outputs it and its bias voltage is compensated by the above control voltage. The delay part comprises a plurality of delay units in multi stages in which a power supply voltage stage and a ground voltage stage are connected and receive the control voltage and the input signal from the delay control part through each gate.

Description

Delay time control device for minimizing the delay time change

The present invention relates to a delay apparatus of an integrated circuit, and more particularly, to a delay apparatus of an integrated circuit for minimizing a change in delay time due to a temperature environment by improving a voltage biased to a delay element to compensate for a temperature. .

In general, in an integrated circuit using a semiconductor, the electrical resistance changes with temperature.

As a result, the transistor used also changes its turn-on resistance and the mobility of electrons and holes.

As a result, an inverter logic chain is used as shown in FIG. 1 in order to exhibit a constant electrical delay effect. Such a delay element is also changed according to temperature.

At high temperatures, the delay component increases and the operation of the integrated circuit varies depending on the temperature.

In circuits requiring a constant delay, especially in frequency oscillators such as ring oscillators, this change in delay causes the oscillation frequency to vary.

Accordingly, an object of the present invention for solving the above problems is to minimize the change in delay time according to the temperature by compensating for the change in the bias voltage according to the temperature change of the delay element.

1 is a view showing a conventional inverter chain,

2 is a circuit diagram showing an embodiment of a delay apparatus of an integrated circuit according to the present invention;

3 is a waveform diagram of a simulation result in preparation for a conventional state and an application state of the present invention;

4 is a circuit diagram showing another embodiment of the present invention;

5 is a circuit diagram showing yet another embodiment of the present invention.

In the integrated circuit delay apparatus according to the present invention for achieving the above object, the bias voltage is compensated by the delay control unit and the control voltage for generating a control voltage for compensating for the bias voltage change by using the change in the amount of current caused by the temperature change. A plurality of delay elements for delaying and outputting an input signal for a predetermined time may include a delay unit including multiple stages.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 2, the delay apparatus of the present invention uses the first control unit 10 and the second control unit 20 to compensate for the bias voltage change of the delay element by using the change in the turn-on resistance of the MOS transistor according to the temperature change. Delay elements for delaying and outputting a signal for a predetermined time include a delay unit 30 connected in parallel.

The first control unit 10 includes a resistor R1 connected between the power supply voltage terminal and the A node, and an NMOS transistor M1 connected between the A node and the ground voltage terminal to which a gate and a drain terminal are commonly connected.

The second controller 20 includes an NMOS transistor M2 connected between a power supply voltage terminal and a B node and having a common gate and drain terminal connected thereto, and a resistor R2 connected between the B node and a ground voltage terminal.

In this case, the resistors R1 and R2 may be used as a poly resistor formed of a polycrystalline silicon layer or a diffusion resistor formed by diffusing impurities onto a substrate.

The delay unit 30 includes multiple stage inverters IV1, IV2, and IV3 connected in parallel between nodes A and B as delay elements.

Inverter IV1 has a PMOS transistor P1, P2 and NMOS transistors N1, N2 connected in series between the supply voltage terminal and the ground voltage terminal.

Here, the PMOS transistor P1 receives the voltage of the A node as a gate, and the gate terminal and the drain terminal of the PMOS transistor P2 and the NMOS transistor N1 are connected in common to form an input terminal and an output terminal. The NMOS transistor N2 receives the voltage of the B node as a gate.

Inverter IV2 has PMOS transistors P3, P4 and NMOS transistors N3, N4 connected in series between the supply voltage terminal and the ground voltage terminal.

Here, the PMOS transistor P3 receives the voltage of the A node as a gate, and the gate terminal and the drain terminal of the PMOS transistor P4 and the NMOS transistor N3 are connected in common, and the common terminal connected to the output terminal of the inverter IV1 and the drain connected in common. The terminal forms an output terminal. The NMOS transistor N4 receives the voltage of the B node as a gate.

Inverter IV3 has a PMOS transistor P5, P6 and NMOS transistors N5, N6 connected in series between the supply voltage terminal and the ground voltage terminal.

Here, the PMOS transistor P5 receives the voltage of the A node as a gate, and the gate terminal and the drain terminal of the PMOS transistor P6 and the NMOS transistor N5 are connected in common, and the common connected gate terminal is connected to the output terminal of the inverter IV2 and the drain connected in common. The terminal forms an output terminal. The NMOS transistor N6 receives the voltage of the B node as a gate.

As the temperature rises, the turn-on resistance of the MOS transistors increases.

Therefore, the bias voltages of the NMOS transistors N2, N4, N6 of the inverters IV1, IV2, IV3 are connected to the bias voltage when the temperature increases, and the bias of the gates of the PMOS transistors P1, P3, P5 is As the bias voltage goes up, the delay components of inverters IV1, IV2, and IV3 increase.

However, as the temperature rises, the turn-on resistance of the NMOS transistor M1 of the first control unit 10 and the NMOS transistor M2 of the second control unit 20 also increases, so that the current flowing through the NOMS transistor M1 and the resistor R1 and the NMOS transistor M2 and the resistor R2 are increased. The current flowing decreases.

Therefore, the voltage drop due to the resistor R1 decreases, so that the voltage of the node A increases, and the voltage applied to the resistor R2 decreases, so that the voltage of the node B decreases.

The voltage change of node A and node B is reversed to the bias voltage change due to the temperature rise of the inverters IV1, IV2, and IV3, resulting in mutual cancellation.

3 is a simulation result showing the change in the delay time of the delay unit 30 according to the temperature change before and after using the control unit 10, 20 of the present invention.

In FIG. 3, a thick line is a case where the control units 10 and 20 according to the present invention are used, and a thin line is not.

Line (a) shows the delay time of the conventional delay element when the temperature is 125 ° C, and line (b) shows the change in the delay time of the conventional delay element when the temperature is -10 ° C.

As such, it can be seen that the conventional delay device shows a difference in delay time of 183 ms when the temperature is 125 ° C and -10 ° C.

In contrast, in the case of using the controllers 10 and 20 of the present invention, a delay of 27 mu s between a line c representing a delay time at a temperature of 125 ° C and a line d representing a delay time at a temperature of -10 ° C. Only time difference is shown, which is only 15% of the conventional case.

4 is a view showing another embodiment of the present invention.

According to the present embodiment, at least one of the inverters of the delay unit 40 may use the conventional inverter IV4 which does not receive the outputs of the first and second controllers 10 and 30 as the bias voltage of the gate. Is showing.

In addition, in the above-described embodiment, the NMOS transistors M1 and M2 are used as the MOS transistors in the controllers 10 and 20, but they may also be implemented using the PMOS transistors.

FIG. 5 shows a case in which the controllers 10 and 20 are implemented using PMOS transistors P7 and P8 instead of NMOS transistors M1 and M2 according to another embodiment of the present invention.

The first controller 50 includes a PMOS transistor P7 connected between a power supply voltage terminal and a C node and having a gate and a drain terminal connected in common, and a resistor R3 connected between the C node and a ground voltage terminal.

The second controller 60 includes a resistor R4 connected between the power supply voltage terminal and the D node, and a PMOS transistor P8 connected between the D node and the ground power supply terminal to which a gate and a drain terminal are commonly connected.

Since the operation principle of FIG. 5 is the same as that of FIG. 2, description thereof will be omitted.

As described above, it is possible to minimize the delay time change of the delay element according to the temperature change by compensating the difference due to the temperature change of the voltage biased to the delay element.

Claims (10)

A delay controller configured to generate a control voltage for compensating for a bias voltage change of the delay elements by using a change in the amount of current caused by a temperature change; And A delay device of an integrated circuit comprising a delay unit having a plurality of delay elements configured to compensate for a bias voltage by the control voltage and to delay and output an input signal for a predetermined time. The method of claim 1, And the delay unit is connected in series to a power supply voltage terminal and a ground voltage terminal, and includes a plurality of delay elements configured to receive a control voltage and an input signal from the delay control unit through respective gates. The method of claim 1, wherein the delay control unit A first controller connected to the gate terminal of the PMOS transistors of the delay elements to output the control voltage; And And a second control unit connected to the gate terminal of the NMOS transistors of the delay elements to output the control voltage. The method of claim 3, wherein the first control unit A first resistor connected between a power supply voltage terminal and a first node to which gate terminals of the PMOS transistors of the delay device are commonly connected; And And a first NMOS transistor connected between the first node and a ground voltage terminal, and having a gate terminal and a drain terminal commonly connected to each other. The method of claim 3, wherein the second control unit A second NMOS transistor connected between a power supply voltage terminal and a second node having common gate terminals of the NMOS transistors of the delay device connected to each other, and having a gate terminal and a drain terminal connected in common; And And a second resistor connected between the second node and a ground voltage terminal. The method of claim 3, wherein the first control unit A first PMOS transistor connected between a power supply voltage terminal and a first node having common gate terminals of the PMOS transistors of the delay device connected to each other, and having a gate terminal and a drain terminal connected to each other; And And a first resistor connected between the first node and a ground voltage terminal. The method of claim 3, wherein the second control unit A second resistor connected between a power supply voltage terminal and a second node to which gate terminals of the NMOS transistors of the delay device are commonly connected; And And a second PMOS transistor connected between the second node and a ground voltage terminal, and having a gate terminal and a drain terminal commonly connected to each other. The method according to any one of claims 4 to 7, Any one of the first resistor and the second resistor is a poly resistor formed of a polycrystalline silicon layer. The method according to any one of claims 4 to 7, Any one of the first resistor and the second resistor is a diffusion resistor formed by diffusing impurities onto a substrate. The method of claim 1, And the delay control unit selectively outputs a control voltage only to delay elements located at an arbitrary position among the delay elements having the multi-stage.