KR20040006554A - a thin film transistor array panel and a liquid crystal display including the panel - Google Patents

Abstract

PURPOSE: A thin film transistor array substrate and a liquid crystal display including the same are provided to prevent gray scale inversion when a liquid crystal display is viewed from a lower part by coupling two pixel electrodes of neighboring pixel areas. CONSTITUTION: Gate lines(121) are formed on an insulating substrate in a horizontal direction. Maintenance capacity lines(131,132) are formed in parallel with the gate lines. A gate insulating film covers the gate lines and the maintenance capacity lines. A semiconductor layer(150), data lines(171), and coupling electrodes(177) are formed on the gate insulating film. Source electrodes(173) and first and second drain electrodes(1751,1752) are formed on the semiconductor layer. A passivation film is formed on the data lines. First pixel electrodes(191) formed on the passivation film are connected with the first drain electrodes. Second pixel electrodes(192) formed on the passivation film are connected with the second drain electrodes. The second pixel electrodes are connected with the coupling electrodes. The first pixel electrodes are overlapped with the coupling electrodes connected with the second pixel electrodes of neighboring pixels.

Description

A thin film transistor array panel and a liquid crystal display including the panel}

The present invention relates to a thin film transistor substrate and a liquid crystal display including the same.

In general, a liquid crystal display device injects a liquid crystal material between an upper substrate on which a common electrode, a color filter, and the like are formed, and a lower substrate on which a thin film transistor and a pixel electrode are formed. By applying a different potential to form an electric field to change the arrangement of the liquid crystal molecules, and through this to control the light transmittance is a device that represents the image.

However, it is an important disadvantage that the liquid crystal display device has a narrow viewing angle. In order to overcome these disadvantages, various methods for widening the viewing angle have been developed. Among them, liquid crystal molecules are oriented vertically with respect to the upper and lower substrates, and a method of forming a constant opening pattern or forming protrusions on the pixel electrode and the common electrode opposite thereto is performed. This is becoming potent.

As a method of forming the opening pattern, an opening pattern is formed in each of the pixel electrode and the common electrode, and the viewing angle is widened by adjusting the direction in which the liquid crystal molecules lie down using a fringe field formed by the opening patterns. .

The method of forming the protrusions is a method of controlling the lying direction of the liquid crystal molecules by using the electric field distorted by the protrusions by forming protrusions on the pixel electrode and the common electrode formed on the upper and lower substrates, respectively.

In another method, an opening pattern is formed on the pixel electrode formed on the lower substrate, and a protrusion is formed on the common electrode formed on the upper substrate, so that the liquid crystal lies down using a fringe field formed by the opening pattern and the protrusion. There is a way to form a domain by controlling.

In such a multi-domain liquid crystal display, a gray scale inversion reference viewing angle defined as a contrast ratio reference viewing angle based on a contrast ratio of 1:10 or a limit angle of luminance inversion between gray scales is very excellent in a horizontal direction of 80 ° or more. However, in the up and down direction, there remains a problem of gray level inversion (a phenomenon in which the brightness to be increased as the gray voltage is increased). In particular, the gray level inversion of the lower side is a very serious problem.

On the other hand, the liquid crystal display must secure a sufficient storage capacity to maintain the voltage transmitted to the pixel electrode for a predetermined time, for this purpose, to form a eugeneous electrode with a large area overlapping the pixel electrode, the sustain electrode This causes a decrease in the aperture ratio.

SUMMARY OF THE INVENTION The present invention provides a thin film transistor array substrate capable of preventing gray level inversion and a liquid crystal display including the same.

Another object of the present invention is to provide a thin film transistor array substrate and a liquid crystal display including the same, which can secure an aperture ratio while maintaining a storage capacitance.

1 is a layout view of a thin film transistor array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

2 and 3 are cross-sectional views taken along line II-II 'and line III-III' of FIG. 1, respectively.

FIG. 4 is an equivalent circuit diagram of a liquid crystal display device to which the thin film transistor array substrate of FIG. 1 is applied.

5A to 5C are graphs showing the change of the VT curve according to the change of the constant T as the VT curve when viewed from the front, the lower 40 degrees, and the lower 60 degrees, respectively.

6A to 6E are graphs showing changes in gamma curves according to viewing angles as gamma curves when T = 1, T = 0.9, T = 0.8, T = 0.7, and T = 0.65, respectively.

7A to 7D show gamma curves according to viewing angles as gamma curves when T = 0.7 is fixed and area ratios of a pixel electrode and b pixel electrode are 0.9: 0.1, 0.8: 0.2, 0.7: 0.3, and 0.3: 0.7, respectively. It is a graph showing the change of curve.

To solve this problem, one pixel is divided into two small pixels having two thin film transistors and two pixel electrodes, and a capacitive coupling is formed between pixel electrodes of neighboring pixels. In this case, the conductor pattern for capacitive coupling is disposed so as to overlap the eugeneous electrodes of neighboring pixels in order to sufficiently secure the storage capacitance.

More specifically, in the thin film transistor array according to the present invention, a first signal line is formed on the insulating substrate in the first direction, and a second signal line insulated from and intersects the first signal line in the second direction is formed. A first thin film transistor and a second thin film transistor connected to the first signal line and the second signal line are formed at a portion where the first signal line and the second signal line intersect, and the first pixel is formed on the first thin film transistor and the second thin film transistor. The electrode and the second pixel electrode are formed, respectively. Each pixel includes a sustain electrode that overlaps the first or second pixel electrode to form a storage capacitor, and is electrically connected to the first or second pixel electrode, and has a first or second pixel electrode of a neighboring pixel. The coupling capacitor is formed so as to overlap with each other, and the conductive capacitor pattern for overlapping with the storage electrodes of neighboring pixels is formed.

In addition, the liquid crystal display according to the present invention includes a common electrode substrate facing the thin film transistor substrate and the thin film transistor substrate, and a liquid crystal material injected between the thin film transistor substrate and the common electrode substrate. In this case, the liquid crystal material is preferably in a twisted nematic (TN) mode.

In another thin film transistor substrate according to the present invention, a gate wiring including a gate line extending in a horizontal direction and a gate electrode connected to the gate line is formed on an insulating substrate, and the storage electrode line extending in the horizontal direction and connected thereto. A sustain wiring including the sustain electrode is formed. A semiconductor layer is formed on the gate insulating layer covering the gate wiring and the sustain wiring, and a data line extending in the vertical direction, a source electrode connected to the data line and extending up on the semiconductor layer, and facing the source electrode on the semiconductor layer. Data wirings including first and second drain electrodes are formed. In the region defined by the intersection of the gate line and the data line, a conductive capacitance conductor pattern overlapping the storage electrodes of neighboring pixels is formed, and a protective film is formed on the data interconnection and the conductive capacitance conductor pattern. Has a first contact hole for exposing a part of the first and second drain electrodes, and a third contact hole for exposing a part of the conductor pattern for the coupling capacitance. The passivation layer is connected to the first drain electrode through the first contact hole, and is connected to the second drain electrode through the first pixel electrode and the second contact hole overlapping the conductive pattern for the coupling capacitance of the neighboring pixel. A second pixel electrode connected to the conductive capacitance conductor pattern is formed through the sphere.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only being "on top of" another part but also having another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A thin film transistor array substrate and a liquid crystal display including the same according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a layout view of a thin film transistor array substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views taken along lines II-II 'and III-III' of FIG. 1.

On the insulating substrate 110, a gate wiring and a sustain wiring formed of a single film made of silver or a silver alloy having a low resistance, or an aluminum or aluminum alloy or a multilayer film including the same are formed. The gate line is connected to the gate line 121 and the gate line 121 which extend in the horizontal direction, and is vertically moved from the gate pad 125 and the gate line 121 to receive the gate signal from the outside and transfer the gate signal to the gate line. It includes a gate electrode 123 of the thin film transistor protruding. The storage wiring includes the storage electrode lines 131 and 132 which are parallel to the gate line 121 and formed above and below the gate line 121, and the storage electrode 133 extending from the storage electrode line 131.

On the substrate 110, a gate insulating layer 140 made of silicon nitride (SiN _x ) covers the gate lines 121, 125, and 123 and the storage lines 131, 132, and 133.

A semiconductor layer 150 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 140 of the gate electrode 125, and n + is heavily doped with silicide or n-type impurities on the semiconductor layer 150. Resistive contact layers 163, 1651, and 1652 made of a material such as hydrogenated amorphous silicon are formed, respectively.

On the ohmic contacts 163, 1651, and 1652 or the gate insulating layer 140, a data line including a conductive film including a low resistance conductive material such as aluminum or silver is formed. The data line is formed in a vertical direction and intersects the gate line 121 to define a pixel region, and a source electrode connected to the data line 171 and the data line 171 and extending to an upper portion of the ohmic contact layer 163. 173, the data pad 179 connected to one end of the data line 171 and separated from the source electrode 173 and receiving the image signal from the outside, and the source electrode 173 with respect to the gate electrode 123. Drain electrodes 1751 and 1752 formed on upper and lower resistive contact layers 1651 and 1652, respectively. In addition, the data line overlaps the storage electrode 133 of the neighboring pixel in order to improve the storage capacitance, and the conductive capacitance conductor pattern 177 electrically connected to the pixel electrode 192 formed later. It may include. In this case, the ohmic contacts 163, 1651, and 1652 are formed only at the portion where the semiconductor layer 150 and the data lines 171, 173, 1751, and 1752 overlap each other.

The data wirings 171, 173, 175, and 179 and the semiconductor layer 150 that do not cover the semiconductor wires 150 are stacked by silicon nitride or an organic material having excellent planarization characteristics and a photosensitive or plasma enhanced chemical vapor deposition (PECVD) method. A protective film 180 made of a low dielectric constant CVD or the like containing a -Si: C: O film or a-Si: O: F is formed. Here, it is preferable to completely remove the organic insulating material from the pad portion where the gate pad 125 and the data pad 179 are positioned. This structure is formed on the pad portion on the gate pad 125 and the data pad 179. The present invention is particularly advantageous when applied to a COG (chip on glass) type liquid crystal display device in which a gate driving integrated circuit and a data driving integrated circuit are directly mounted on the thin film transistor substrate so as to transfer scan signals and image signals, respectively.

In the passivation layer 180, contact holes 1851, 1852, 187, and 189 exposing the drain electrodes 1751 and 1752, the conductive capacitor pattern 177, and the data pad 179 are formed, respectively. A contact hole 182 is formed to expose the gate pad 125 together with the 140.

The upper portion of the passivation layer 180 is electrically connected to the drain electrodes 1551 and 1752 through contact holes 1851 and 1852, respectively, and is disposed in two small pixel regions that are vertically separated from the gate line 121. The pixel electrodes 191 and 192 made of indium zinc oxide (IZO) or indium tin oxide (ITO), which are transparent conductive materials, are formed. In this case, the pixel electrode 192 is connected to the conductive capacitor pattern 177 through the contact hole 187 of the passivation layer 180. In addition, an auxiliary gate pad 92 and an auxiliary data pad 97 connected to the gate pad 125 and the data pad 179 are formed on the passivation layer 180 through the contact holes 182 and 189, respectively. Here, the auxiliary gate and data pads 92 and 97 are for protecting the gate and data pads 125 and 179, but are not essential.

The potential of the common electrode facing the pixel electrodes 191 and 192 is usually applied to the sustain wirings 131, 132, and 133.

In this case, the conductive capacitor pattern 177 is disposed in the lower small pixel region, but is arranged to be connected to the pixel electrode 191 of the upper small pixel region and the pixel electrode 192 of the lower small pixel region of the neighboring pixel. And overlap with the storage electrode 132 overlapping the same.

The liquid crystal display using the thin film transistor substrate has the following structure.

The common electrode substrate is disposed at a predetermined interval to face the thin film transistor substrate, and a liquid crystal material is injected between the thin film transistor substrate and the common electrode substrate. In this case, the liquid crystal material may be torsionally aligned from the lower substrate to the upper substrate with the liquid crystal molecules arranged almost parallel to the substrate with the TN mode liquid crystal, and have negative dielectric anisotropy with the vertical aligned mode liquid crystal (VA). The liquid crystal molecules oriented almost perpendicular to the substrate may be arranged almost perpendicular to the substrate until the voltage is sufficiently applied to the center plane of the two substrates. The common electrode substrate is provided with a common electrode for forming a liquid crystal capacitor between the pixel electrodes of the thin film transistor substrate. In addition, a compensation film such as a WV film may be attached on the common electrode substrate, and two polarizing plates are disposed outside the thin film transistor substrate and the common electrode substrate.

In this case, in the case of a liquid crystal display of a patterned vertically aligned (PVA) mode in which openings are formed by domain dividing means, the pixel electrode may have a plurality of openings, and the common electrode opposite thereto may also have a plurality of openings. The opening of the electrode and the opening of the common electrode may divide the pixel area into left and right domains and top and bottom domains.

Next, the liquid crystal display according to the exemplary embodiment of the present invention will be described through an equivalent circuit.

4 is an equivalent circuit diagram of a liquid crystal display device to which the thin film transistor array substrate of FIG. 1 is applied. Here, reference numerals appearing when describing an equivalent circuit refer to FIGS. 1 to 3.

As shown in FIG. 4, in the liquid crystal display according to the exemplary embodiment of the present invention, each unit pixel is divided into two small pixels P (n) -a and P (n) centered on the gate line 121. -b]. Each of the small pixels P (n) -a and P (n) -b is vertically disposed around the gate line 121 and electrically connected to the same gate line 121 and the data line 171. Driven by two thin film transistors TFT1 and TFT2, each of the small pixels P (n) -a and P (n) -b is a liquid crystal formed between the upper pixel electrode 191 and the common electrode. The capacitor Clca, the liquid crystal capacitor Clcb formed between the lower pixel electrode 192 and the common electrode, the storage capacitor Csta and the lower pixel electrode formed between the upper storage electrode line 131 and the upper pixel electrode 191. And a storage capacitor Cstb formed between 192 and the lower storage electrode line 132. Each of the unit pixels may include a coupling capacitor Cpp formed between the upper pixel electrode 191 and the lower pixel electrode 192 overlapping the upper pixel electrode 191 through the coupling capacitor conductor 177. Auxiliary storage capacitor formed between the conductive pattern 177 for the coupling capacitance of the lower small pixel [P (n) -b] and the sustain electrode 133 of the adjacent upper small pixel [P (n + 1) -a}. Has (Csp).

As described above, two thin film transistors and two pixel electrodes are formed per pixel area, and two pixel electrodes of neighboring pixel areas are capacitively coupled by using a coupling electrode, so that the gray scale when the liquid crystal display is viewed from below. The inversion can be prevented from appearing.

Then, the reason why the lower gray level inversion is eliminated will be explained in more detail by applying the present invention. Here, since the auxiliary storage capacitor Csp acts only on the size of the storage capacitor for the unit pixel, it will be omitted in the following equation to explain why the gray scale inversion is eliminated.

First, referring to FIG. 4, the potentials {V [P (n) -a] and V [P of two pixels P (n) -a and P (n) -b] disposed in one pixel area. (n) -b)]}.

Based on one data line 171, when the n-th gate line 121 is turned on, two thin film transistor (TFT) channels are turned on and thereby the first and second pixel electrodes P (n). ) -a, P (n) -b] is applied. However, P (n) -b is capacitively coupled to P (n + 1) -a so that P (n) -b is affected when P (n + 1) -a is on. Therefore, the voltages of P (n) -a and P (n) -b are given by

V [P (n) -a] = Vd (n)

In Equations 1 and 2, Vd (n) denotes a voltage applied to a data line to drive a P (n) pixel, and Vd (n + 1) denotes a data applied to drive P (n + 1). Means line voltage. In addition, V'd (n + 1) means a voltage applied to the P (n + 1) pixel of the previous frame.

As shown in Equations 1 and 2, the voltage applied to the P (n) -b pixel and the voltage applied to the P (n) -a are different from each other. In particular, when dot inversion driving or line inversion driving is performed, and the next pixel row displays the same gray scale as the previous pixel row (actually, most of the pixels have a lot of time in this case), Vd (n) =-Vd Since (n + 1) and Vd (n) =-V'd (n) (assuming that the common electrode voltage is a ground voltage), Equation 2 can be summarized as follows.

According to Equation 3, a voltage lower than P (n) -a is applied to P (n) -b. That is, two different gray voltages are transmitted to one pixel, and thus an image is displayed with luminance with respect to different gray voltages transmitted to two small pixels. Then, since one unit pixel displays an image through luminance of two gray voltages, it is possible to prevent a sudden increase or decrease of luminance due to a change in gray voltage, and in particular, to a change in gray voltage. It can be prevented that the gray scale reversal occurs at the lower viewing angle at which is rapidly increased or decreased.

The following describes in more detail what happens in view angle when different voltages are applied to the two pixels.

5A to 5C are graphs of VT curves of P (n) -b pixels when viewed from the front, lower 40 degrees, and lower 60 degrees, respectively, and simulated changes in the VT curve according to the change of the constant T. FIG.

The direction of the arrow in FIGS. 5A-5C indicates a decrease in the T value. Each curve in the graph is a TV curve when the T values are 1, 0.95, 0.90, ..., 0.65. Looking at these graphs, as the T value decreases, the VT curve of the P (n) -b pixel shifts toward higher voltages.

Then, we simulate what gamma curve is generated when the P (n) -a and P (n) -b pixels are summed.

6A to 6E are graphs showing changes in gamma curves according to viewing angles as gamma curves when T = 1, T = 0.9, T = 0.8, T = 0.7, and T = 0.65, respectively.

When T = 1, gray level reversal occurs distinctly at the lower side 60 degrees, and gray level reversal gradually decreases as T decreases, and gray level reversal disappears when T = 0.7. That is, the gray level inversion can be eliminated by adjusting the T value. At this time, when T reaches 0.65, which is smaller than 0.7, it starts to show signs of gray scale inversion. As a result, when T = 0.7, it is most effective for removing the gray level inversion, and when it is 0.5 to 0.9, it is shown to have some effect.

The value of T is adjusted by adjusting Cpp according to Equation 3, and Cpp is adjusted by adjusting the size of the coupling capacitor conductor 177 in FIG. 1, or adjusting the overlap width with the pixel electrode 191. It can be adjusted in a way.

Next, the change in the gamma curve according to the area ratio of the P (n) -a pixel and the P (n) -b pixel will be described.

7A to 7D are fixed at T = 0.7, and the area ratios of the pixel electrodes of P (n) -a and the pixel electrodes of P (n) -b are 0.9: 0.1, 0.8: 0.2, 0.7: 0.3, and 0.3 :, respectively. It is a graph which shows the change of a gamma curve with a viewing angle as a gamma curve at 0.7.

When the area ratio of the a pixel and the b pixel is 0.9: 0.1, gray level inversion is shown at the lower side 60 degrees. However, in the case of a: b = 0.8: 0.2 or a: b = 0.7: 0.3, gray level inversion is hardly seen. However, when the area of the P (n) -b pixel becomes larger and a: b = 0.3: 0.7, gray scale inversion occurs again. As a result, when the ratio of P (n) -b pixels is about 20% to 30% in the entire pixel area, it is most effective for removing grayscale inversion, and when it is 10% to 50%, it has some effect.

By dividing the unit pixel into two small pixels and connecting the pixel electrodes of neighboring pixels to the coupling capacitor, it is suitable as a structure to prevent the gray scale inversion. In this case, in order to overlap the neighboring pixel electrodes, a coupling capacitance electrode that commonly overlaps the pixel electrodes of two neighboring pixels, must be disposed in the center of the neighboring pixels. In this case, the aperture ratio is reduced. In addition, when dividing a pixel into two small pixels, the total capacitance of each pixel is reduced. In an exemplary embodiment of the present invention, in order to solve the problem at the same time, the pixel electrode 192 is electrically connected to one pixel, and overlaps the pixel electrode 191 of another pixel adjacent thereto while simultaneously overlapping the storage electrode 133. A coupling capacitance conductor pattern 177 is taken. In this structure, the coupling capacitor conductor 177 is overlapped with the neighboring pixel electrode 191 while the coupling capacitor conductor 177 is connected to the pixel electrode 192 so that the coupling capacitance can be sufficiently secured even with a narrow overlapping area. ) And the gate insulating layer 140 interposed therebetween, so that the auxiliary storage capacitor can be sufficiently secured, thereby increasing the total capacitance of the pixel. Therefore, in the structure of the present invention, the aperture ratio of the pixel can be sufficiently secured while the retention capacitance and the coupling capacitance of the pixel are sufficiently increased.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

In the present invention, two thin film transistors and two pixel electrodes are formed per pixel area, and when the two pixel electrodes of the neighboring pixel area are capacitively coupled, the coupling capacitive conductor pattern overlaps the pixel electrode of the neighboring pixel. At the same time, by overlapping with the sustain electrode, the aperture ratio of the pixel can be ensured and the sustain capacitance of the pixel can be sufficiently increased.

Claims (7)

Insulation board, A first signal line formed on the insulating substrate in a first direction, A second signal line formed on the insulating substrate in a second direction and insulated from and intersecting the first signal line; A first thin film transistor connected to the first signal line and the second signal line, A second thin film transistor connected to the first signal line and the second signal line to which the first thin film transistor is connected; A first pixel electrode connected to the first thin film transistor, A second pixel electrode connected to the second thin film transistor, A storage electrode overlapping the first or second pixel electrode to form a storage capacitor; A coupling capacitance electrically connected to the first or second pixel electrode and overlapping with the first or second pixel electrode of a neighboring pixel to form a coupling capacitance, and overlapping with the sustain electrode of the neighboring pixel Sieve pattern Thin film transistor array substrate. The thin film transistor substrate of claim 1, A common electrode substrate facing the thin film transistor substrate; A common electrode formed on the common electrode substrate, A liquid crystal material injected between the thin film transistor substrate and the common electrode substrate Liquid crystal display comprising a. In claim 2, And the liquid crystal material is twisted nematic (TN) mode. In claim 2, And the liquid crystal material is a vertical algned (VA) mode. In claim 4, A liquid crystal display device having openings in the first and second pixel electrodes or the common electrode as domain dividing means. Insulation board, A gate wiring including a gate line formed on the insulating substrate in a horizontal direction and a gate electrode connected to the gate line; A sustain electrode formed on the insulating substrate. A gate insulating film covering the gate wiring, A semiconductor layer formed on the gate insulating film on the gate electrode; A data line formed in a vertical direction on the gate insulating layer, a source electrode connected to the data line and extending up to the semiconductor layer, and first and second drain electrodes facing the source electrode on the semiconductor layer; Data wiring, A conductive capacitance conductor pattern formed in an area defined by the intersection of the gate line and the data line and overlapping the storage electrode of a neighboring pixel; A third contact hole formed on the data line and the coupling capacitor pattern and exposing a portion of the first and second drain electrodes, respectively; Protective film with contacts, A first pixel electrode formed on the passivation layer and connected to the first drain electrode through the first contact hole and overlapping the conductive capacitor conductor pattern of a neighboring pixel; A second pixel electrode formed on the passivation layer and connected to the second drain electrode through the second contact hole and connected to the conductor pattern for the coupling capacitance through the third contact hole; Thin film transistor array substrate comprising a. In claim 6, The thin film transistor array substrate of which the first or second pixel electrode has an opening as a domain dividing means.