KR20040005091A - Output buffer - Google Patents

Abstract

PURPOSE: An output buffer is provided, which turns off a pull-up transistor within a short time in a bidirectional I/O cell used for transferring bidirectional signal and has an immunity as to an excessive voltage. CONSTITUTION: A pre-driver circuit(100) receives a signal input and an output enable input and generates a pull-up voltage signal and a pull-down voltage signal. A transfer gate(107) has the first transistor connected to a power supply voltage(VDD) and the second transistor connected to the second node, and receives the pull-up signal from the pre-driver circuit and then transmits it to the first node. A pull-up driver has a gate connected to the first node and is connected between a pad(106) and the power supply voltage. The third transistor is connected between the first node and the pad, and the fourth transistor is connected between the pad and the second node. A pull-down driver receives the pull-down signal from the pre-driver circuit and is connected between the pad and a ground(VSS). And a bias generation circuit is connected between the second node and the ground and receives the output enable signal, and turns on the second transistor when an output buffer is in a normal operation state and turns off the second transistor when the output buffer is in a high impedance state.

Description

Output buffer {OUTPUT BUFFER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer of a semiconductor device. In particular, in a bidirectional I / O cell used for bidirectional signal transmission, the pull-up transistor can be turned off in a short time and has an output resistance against overvoltage. It is about a buffer.

With the development of CMOS technology, power supply voltages used in semiconductor devices have gradually decreased, and more and more CMOS integrated circuits having an operating voltage of 3.3 V or less are increasing. Therefore, a CMOS integrated circuit that is resistant to overvoltage is required for signal transmission with a conventional CMOS integrated circuit having a 5 V operating voltage.

When bidirectional signal transmission between two or more chips having different operating voltages, when the chip having the low operating voltage is used as the input mode and the chip having the high operating voltage is used as the output mode, the chip having the low operating voltage A voltage higher than the voltage used by the pad may be applied to the pad. In this case, the output buffer in the chip with the low operating voltage must be able to withstand the overvoltage. In order for the output buffer to be resistant to overvoltage, when a voltage higher than the power supply voltage (VDD) used by the output buffer is applied to the pad, no leakage current must flow through the pad, and the output buffer is prevented by the high voltage applied to the pad. The transistors that make up should not be damaged.

1 shows a conventional CMOS output buffer that is resistant to overvoltage, as described in US Pat. No. 5,151,619 and the like. As shown in FIG. 1, the output buffer includes a PMOS pull-up transistor 22 having a source connected to the power supply voltage VDD and a drain connected to the pad 24. PMOS pull-up transistor 22 is connected to a pre-driver circuit 10 through a transfer gate 15 formed by NMOS transistor 12 and PMOS transistor 14. The output buffer of FIG. 1 also has NMOS pull-down transistors 26 and 28 connected in series between pad 24 and ground (VSS). The NMOS transistor 26 has a gate connected to the power supply voltage VDD, and the NMOS transistor 28 has a gate connected to the pull-down voltage signal VPD generated by the predriver circuit 10. The PMOS trace transistor 20 is connected between the pad 24 and the gate of the PMOS pull-up transistor 22, and the gate of the PMOS trace transistor 20 is connected to the power supply voltage VDD. The gate of the NMOS transistor 12 forming the transfer gate 15 is connected to the power supply voltage VDD, and the gate of the PMOS transistor 14 is connected to the pad 24.

The PMOS transistors 14, 20, 22 are connected by n-well or substrate and generally have a floating n-well connection. Unlike the usual case, the floating well 30 is not directly connected to the power supply voltage VDD. Because of the physical nature of the semiconductor integrated circuit, there is a parasitic diode (substrate diode) between the floating n-well 30 and the pad 24. Therefore, the n-well or substrate of the PMOS transistors 14, 20, 22 need not be physically connected to each other as shown in FIG. 1. The n-well or substrate of the PMOS transistors 14, 20, 22 is electrically or virtually connected by parasitic diodes. The predriver circuit 10 has two inputs, a signal input SI and an output enable input OE. The predriver circuit 10 operates in response to the signal input SI and the output enable input OE and generates a pull-up voltage signal VPU and a pull-down voltage signal VPD. These signals drive the PMOS pull-up transistor 22 and the NMOS pull-down transistor 28 to supply an appropriate output signal voltage to the pad 24. The output buffer of Figure 1 has two operating states, a normal operating state and a high impedance state (also referred to as "tristate"). In normal operation the output enable signal is "low" and in the high impedance state the output enable signal is "high".

In the normal operating state, the predriver circuit 10 generates a pull-up voltage signal VPU that is "low" and a pull-down voltage signal VPD that is "low" to generate an output "high" to the pad 24. In order to generate an output " low " to the pad 24, the predriver circuit 10 generates a pull-up voltage signal VPU that is " high " and a pull-down voltage signal VPD that is " high. &Quot; In order to generate a high impedance tristate in the pad 24, the predriver circuit 10 generates a pull-up voltage signal VPU that is "high" and a pull-down voltage signal VPD that is "low". Under this condition, both the pull-up transistor 22 and the pull-down transistor 28 are turned off so that there is no leakage current through the pad 24. In addition, by configuring the pull-down transistors 26 and 28 in two stages, the voltage across the source-drain, gate-drain, and gate-source of the NMOS transistors 26 and 28 is maintained within VDD (eg, 3.3 V). Can be lowered. In addition, the gate voltage of the pull-up transistor 22 follows the voltage of the pad when the pad voltage is higher than VDD by the PMOS transistor 20, so that the pull-up transistor 22 drives the pull-up transistor 22 from the gate of the pull-up transistor 22. The transfer gate 15 is inserted between the predriver circuit 10 and the gate of the pull-up transistor 22 in order to prevent leakage current from occurring in the driver circuit 10. As such, the conventional output buffer as shown in FIG. 1 can withstand this even when an overvoltage is applied when the pad 24 is in a high impedance state.

However, in the conventional output buffer as shown in FIG. 1, an unwanted phenomenon may occur due to the transfer gate 15 composed of the NMOS transistor 12 and the PMOS transistor 14. The pull-up voltage signal VPU goes "low" to keep the pad 24 "high" while the pull-up voltage signal VPU goes "high" so the pad 24 goes into a high impedance tristate. In this case, there is a problem that it takes a long time for the pull-up transistor 22 to be completely turned off. That is, when the pad is in the "high" state and the output enable input OE becomes "high" and the pad 24 is in the high impedance state, the state of the gate terminal of the pull-up transistor 22 is "low". Should change to "high". In this case, since the PMOS transistor 14 constituting the transfer gate 15 is turned off by the pad voltage which is "high", the state of the gate terminal of the pull-up transistor 22 is the NMOS transistor 12 constituting the transfer gate 15. Only). For this reason, when the threshold voltage of the gate terminal of the pull-up transistor 22, that is, the NMOS transistor 12 is referred to as Vthn, the voltage level of the node N1 is limited to VDD-Vthn and thereafter, the sub-level of the NMOS transistor 12 The state of the node N1 is changed only by the sub-threshold current. In general, since the sub-threshold voltage of the transistor is very small, the voltage level of the node N1 rises very slowly to the power supply voltage VDD level. Therefore, the time taken for the pull-up transistor 22 to be completely turned off becomes long, during which the pull-up transistor 22 functions as a weak pull-up.

It is an object of the present invention to provide an output buffer that can turn off a pull-up transistor in a short time in a bidirectional I / O cell used for bidirectional signal transmission and is resistant to overvoltage.

1 shows a conventional CMOS output buffer that is resistant to overvoltage.

2 shows a CMOS output buffer according to the present invention which is resistant to overvoltage.

FIG. 3 is a diagram illustrating a CMOS output buffer according to the present invention in detail showing a portion of a predriver circuit in FIG. 2.

4 is a view showing the waveform of each signal in the CMOS output buffer according to the present invention in comparison with the prior art.

Figure 5 shows the waveform of the pad voltage when the pad of the output buffer outputs "high" and goes to a high impedance state when a load of 30 pF is placed on the VSS in parallel with a resistance of 100 kΩ on the pad. It is compared with the figure shown.

<Description of the symbols for the main parts of the drawings>

100: predriver circuit 106: pad

107: transfer gate 112: bias generator

The output buffer according to the present invention includes a predriver circuit for receiving a signal input and an output enable input and generating a pull-up voltage signal and a pull-down voltage signal, having a first transistor connected to a power supply voltage and a second transistor connected to a second node. A transfer gate that receives the pull-up signal from a predriver circuit and transmits the pull-up signal to a first node, a pull-up driver connected between a pad and a power supply voltage having a gate connected to the first node, and connected between the first node and the pad A third transistor, a fourth transistor coupled between the pad and the second node, a pulldown driver receiving the pulldown signal from the predriver circuit and coupled between the pad and ground, and the second node Connected between and ground and the output enable input can be And it characterized in that the output buffer is provided with a bias generation circuit for creating in the normal operating state to create the second transistor to an on state a high impedance state to the second transistor in the off state.

The bias generation circuit includes a fifth transistor having a drain connected to the second node and a gate connected to the power supply voltage, and a gate connected to the source of the fifth transistor and a source connected to ground and receiving an output enable input. It is characterized by including a sixth transistor having a.

Hereinafter, a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

2 shows a CMOS output buffer according to the present invention which is resistant to overvoltage. As shown in FIG. 2, the output buffer includes a PMOS pull-up transistor 103 having a source connected to the power supply voltage VDD and a drain connected to the pad 106. The PMOS pull-up transistor 103 is connected to the predriver circuit 100 through a transfer gate 107 formed by the NMOS transistor 108 and the PMOS transistor 109. The output buffer of FIG. 2 also has NMOS pull-down transistors 104 and 105 connected in series between pad 106 and ground (VSS). The NMOS transistor 104 has a gate connected to the power supply voltage VDD, and the NMOS transistor 105 has a gate connected to the pull-down voltage signal VPD generated by the predriver circuit 100. The PMOS trace transistor 110 is connected between the pad 106 and the gate of the PMOS pull-up transistor 103, and the gate of the PMOS trace transistor 110 is connected to the power supply voltage VDD. The gate of the NMOS transistor 108 forming the transfer gate 107 is connected to the power supply voltage VDD, and the gate of the PMOS transistor 109 is connected to the node N2. A PMOS transistor 111 having a gate connected to the power supply voltage VDD is connected between the pad 106 and the node N2. The NMOS transistors 113 and 114 connected in series are connected between the node N2 and the ground VSS, a power supply voltage is connected to the gate of the NMOS transistor 113, and an inverter is connected to the gate of the NMOS transistor 114. An output enable input OE is applied via 115. The NMOS transistor 113, the NMOS transistor 114, and the inverter 115 constitute a bias generator 112. Also connected between the power supply voltage VDD and the pad 106 are PMOS transistors 101 and 102 connected in series, the source of the PMOS transistor 101 being connected to the power supply voltage VDD and the gate of the pad 106. ) The source of the PMOS transistor 102 is connected to the drain of the PMOS transistor 101, the drain is connected to the pad 106, and the gate is connected to the power supply voltage VDD.

Hereinafter, an output buffer according to the present invention shown in FIG. 2 will be described.

The PMOS transistors 109, 110, 111, 101, 102, 103 are connected by an n-well or a substrate and generally have a floating n-well connection. The bulk (n-well or substrate) of the PMOS transistors 109, 110, 111, 101, 102, 103 is connected to the supply voltage VDD or the pad 106 through the PMOS transistors 101, 102. The leakage current through the transistor can be cut off. The PMOS trace transistor 110 is turned on when the voltage level of the pad 106 is higher than the power supply voltage VDD, thereby making the node N1 the voltage level of the pad 106. The predriver circuit 100 has two inputs, a signal input SI and an output enable input OE. The predriver circuit 100 operates in response to the signal input SI and the output enable input OE and generates a pull-up voltage signal VPU and a pull-down voltage signal VPD. These signals drive the PMOS pull-up transistor 103 and the NMOS pull-down transistor 105 to supply an appropriate output signal voltage to the pad 106. The output buffer of FIG. 2 has two operating states, a normal operating state and a high impedance state (also referred to as "tristate"). In the state in which the output buffer of FIG. 2 is in the normal operation mode, the pull-up transistor 103 is turned on so that the voltage level of the pad 106 becomes "high". That is, the pull-up transistor 103 should be turned off because the state of the node N1 is "high". Conventionally, when the pad of the output buffer is changed from the "high" state to the high impedance state, the node N1 is powered by the PMOS transistor 109 of the transfer gate 107 because only the NMOS transistor 108 is turned on. It took a long time to reach (VDD). In the present invention, such a problem is solved by providing the PMOS transistor 111 and the bias generator 112.

The output enable signal OE is "low" in the output mode, i.e., the normal operating state, and the output enable signal OE is "high" in the input mode, i.e., the high impedance state. In the normal operation state, since the output enable signal OE is " low ", the transistor 114 and the transistor 113 are turned on, so that the PMOS transistor 109 constituting the transfer gate 107 remains on. Therefore, since the PMOS transistor 109 is in an on state at the moment of the change from the normal operation state to the high impedance state, the time for transferring the pull-up voltage signal VPU to the node N1 is shortened. In the high impedance state, since the output enable signal OE is " high ", the transistor 114 and the transistor 113 are turned off, so that the PMOS transistor 109 constituting the transfer gate 107 is turned off. When the voltage level of the pad 106 is higher than the power supply voltage VDD, the PMOS transistor 111 functions to turn on the voltage of the node N2 to the same level as the voltage of the pad 106.

FIG. 3 is a view illustrating a CMOS output buffer according to the present invention specifically showing a predriver circuit portion in FIG. 2, wherein the predriver circuit portion includes an inverter 123 that receives a signal input (SI) and outputs an inverted signal; OR circuit 121 for receiving the output of the inverter 123 and the output enable input OE and performing a logical sum to generate a pull-up voltage signal VPU, and a signal input SI and an output enable input OE. And a NOR circuit 122 for receiving and performing an illogical sum to generate a pulldown voltage signal VPD.

If the output enable input OE is " low " and the signal input SI is " high ", the pull-up voltage signal VPU is in the " low " state and the pull-up transistor 103 is turned on to " high " Signal is output. At this time, the pull-down voltage signal VPD becomes a "low" state and the pull-down transistor 105 is turned off. When the output enable input OE is "low" and the signal input SI is "low", the pull-up voltage signal VPU is in a "high" state and the pull-up transistor 103 is turned off. At this time, the pull-down voltage signal VPD is in the "high" state and the pull-down transistors 105 and 104 are turned on to make the pad 106 a "low" state. When the output enable input OE is "high", the pull-up voltage signal VPU is "high" and the pull-down voltage signal VPD is "low" regardless of the signal input SI, thereby pulling up the transistor. Both the 103 and the pull-down transistors 104 and 105 are turned off. This is the high impedance state.

4 is a view showing the waveform of each signal in the CMOS output buffer according to the present invention in comparison with the prior art. 4 (a) shows the waveform of the signal input SI, FIG. 4 (b) shows the waveform of the output enable input OE, and FIG. 4 (c) shows the voltage waveform of the node N1 according to the prior art. 4 (d) shows the voltage waveforms of the node N1 according to the present invention, respectively. As shown in FIG. 4C, the voltage level of the node N1 slowly increases from VDD to Vthn to VDD in the output buffer of the prior art, but changes to VDD in the output buffer of the present invention. It can be seen that this rapidly changes to VDD. The reason is that in the output buffer according to the present invention, since the PMOS transistor 109 constituting the transfer gate is turned on at the moment when the output enable input OE changes from "low" to "high", the NMOS transistor 108 In addition, since the pull-up voltage signal VPU is transmitted to the node N1 through the PMOS transistor 109, the voltage level of the node N1 changes to VDD at a fast time.

Figure 5 shows the waveform of the pad voltage when the pad of the output buffer outputs "high" and goes to a high impedance state when a load of 30 pF is placed on the VSS in parallel with a resistance of 100 kΩ on the pad. It is compared with the figure shown. FIG. 5 (a) shows the waveform of the signal input SI, FIG. 5 (b) shows the waveform of the output enable input OE, and FIG. 5 (c) shows the voltage and pad of the node N1 according to the prior art. Fig. 5 (d) shows the voltage waveform of the node N1 and the voltage waveform of the pad according to the present invention, respectively. As shown in FIG. 5 (c), it is understood that in the output buffer of the prior art, it takes a long time for the voltage level of the node N1 to rise to VDD, so that it takes several tens of ms until the pad is pulled down by an external resistor. Can be. As shown in FIG. 5 (d), in the output buffer according to the present invention, since the voltage level of the node N1 does not take much time to rise to VDD, the time from the pad to the pulldown by the external resistor is several tens of us. It can be seen that it takes much less than in the output buffer of the prior art.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art various modifications and variations of the present invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

As described above, the output buffer according to the present invention can turn off the pull-up transistor in a short time in a bidirectional I / O device used for bidirectional signal transmission and is resistant to overvoltage.

Claims (6)

A predriver circuit receiving a signal input and an output enable input and generating a pull-up voltage signal and a pull-down voltage signal; A transfer gate having a first transistor connected to a power supply voltage and a second transistor connected to a second node, receiving the pull-up signal from the predriver circuit and transmitting the pull-up signal to a first node; A pull-up driver having a gate connected to the first node and connected between a pad and a power supply voltage; A third transistor coupled between the first node and the pad; A fourth transistor connected between the pad and the second node; A pull-down driver that receives the pull-down signal from the predriver circuit and is coupled between the pad and ground; And A bias connected between the second node and ground and receiving the output enable input such that the output buffer is turned on in normal operation and the second transistor is turned off in high impedance; An output buffer comprising a generation circuit. The method of claim 1, wherein the bias generation circuit A fifth transistor having a drain connected to the second node and a gate connected to the power supply voltage; And And a sixth transistor having a drain connected to the source of the fifth transistor and a source connected to ground and having a gate configured to receive an output enable input. The method according to claim 1 or 2, And the first transistor is an NMOS transistor and the second transistor is a PMOS transistor. The method of claim 1, wherein the output buffer A seventh transistor having a gate connected to the pad and connected between a bulk (n-well or substrate) of the pull-up driver and a power supply voltage; And And an eighth transistor having a gate connected to a power supply voltage and connected between a bulk (n-well or substrate) of the pull-up driver and a ground, Output buffer, characterized in that to cut off the leakage current through the pull-up driver. The method of claim 1, wherein the pull-down driver A ninth transistor having a drain connected to the pad and a gate connected to the power supply voltage; And And a tenth transistor having a drain connected to a source of the ninth transistor and a source connected to ground and having a gate configured to receive the pull-down voltage signal. The method of claim 1, wherein the predriver circuit is An inverter configured to receive the signal input and output an inverted signal; An OR circuit for receiving the output of the inverter and the output enable input and performing a logical sum to generate a pull-up voltage signal; And And output the pulldown voltage signal by receiving the signal input and the output enable input and performing an illogical sum.