KR20040004875A - Method for accessing register in amba apb bridge - Google Patents

Abstract

PURPOSE: A method for accessing to a register in an AMBA(Advanced Microcontroller Bus Architecture) APB(Advance Peripheral Bus) bridge is provided to prevent a wrong operation by sampling an external peri clock signal into an internal bus clock, creating/using a synchronized peri clock signal in the internal bus clock, sensing the both edges of the peri clock signal in advance, operating a waiting signal, thereby applying a peri strobe signal at a stable state. CONSTITUTION: An APB register access for an APB connection is requested(S201). A peri clock signal is sampled by an internal bus clock signal(S202). It is judged whether an edge of the peri clock signal is sensed(S203). If an edge of the peri clock signal is sensed, a waiting cycle is operated for making the peri strobe signal not be activated(S204). If an edge of the peri clock signal is not sensed(or, after operating a waiting cycle), a synchronized peri clock signal is completed and the peri strobe signal is activated by the completed peri clock signal, and an access to the APB register is achieved(S205).

Description

Register approach in the AMAPAAP bridge {METHOD FOR ACCESSING REGISTER IN AMBA APB BRIDGE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register access method in an Advanced Microcontroller Bus Architecture (APM) Advanced Peripheral Bus (APP) bridge. The present invention relates to a register access method in an AMVA AP bridge that drives a standby signal such that a Peri STroBe (PSTB) is not activated by a falling edge.

Recently, a large number of application chips based on ARM's CPU core series have been announced. This is because ARM is providing an effective, cost-effective core solution for many chip manufacturers that are in the race to develop low-power System on Chip (SoC). In this situation, ARM's Advanced Microcontroller Bus Architecture (AMBA) is expected to set the standard for product development using the ARM core.

1 is a block diagram illustrating a typical AMBA, which includes an Advanced System Bus (ASB) region connecting an external bus interface 110, an ARM processor 120, and a single chip RAM 130 within a chip; An APB connection bridge 140 for an Advanced Peripheral Bus (APB) connection; And an Advanced Peripheral Bus (APB) region connecting the Universal Asynchronous Receiver Transmitter (UART) 150, the timer 160, and the PIO 170. Here, the ASB plays the same role as a conventional general bus structure, and the APB is a dedicated bus for modules with less bus usage in the conventional bus structure. In addition, the less frequently used APB connection operation is implemented by accessing the APB register to realize a low power structure. The signal for accessing this APB register is PSTB.

However, since PSTB is not related to the ferry clock signal used for the internal operation of the APB, there is a problem that a malfunction occurs when the access to the APB register occurs at the edge of the ferry clock signal.

In order to solve the above problems, the present invention samples an external ferry clock signal with an internal bus clock BCLK, generates and uses a ferry clock signal synchronized with the internal bus clock BCLK, and simultaneously uses both of the ferry clock signals. It is an object of the present invention to provide a register access method in an AMBA APS bridge in which a PSTB is applied in a stable state by detecting an edge in advance and driving a wait signal.

1 is a block diagram showing a typical AMBA,

2 is a flowchart illustrating a register access method in an AMAP AP bridge according to an exemplary embodiment of the present invention.

3 is an exemplary view showing a waveform of a signal by a program implementing a register access method in an AMAP AP bridge according to an embodiment of the present invention;

4A and 4B are diagrams illustrating the operation of a program implementing a register access method in an AMAP bridge according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

110: external bus connection device 120: ARM processor

130: chip internal RAM 140: APB connection bridge

150: UART160: Timer

170: PIO

In order to achieve the above object, the register access method in the AMAP AP bridge of the present invention includes the steps of: APB register access required for APB connection; Sampling the ferry clock signal by an internal bus clock signal; Determining whether an edge of the ferry clock signal is detected; If an edge of the ferry clock signal is detected, driving a wait cycle; And if the edge of the ferry clock signal is not detected, or after performing the step of driving the standby cycle, completing the synchronized ferry clock signal and activating the ferry strobe signal according to the completed ferry clock signal to access the APB register. Steps.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

2 is a flowchart illustrating a register access method in an AMAP AP bridge according to an embodiment of the present invention.

First, APB register access for APB access is required (S201).

Thereafter, the ferry clock signal PCLK is sampled by the internal bus clock signal BCLK (S202). The ferry clock signal is sampled four times by the internal bus clock signal. Referring to FIG. 3, the first ferry clock signal PCLKraw is a first synchronous clock signal PclkSyn [0] and a second synchronous clock signal ( It is disclosed that PclkSyn [1], a third synchronous clock signal PclkSyn [2], a fourth synchronous clock signal PclkSyn [3] and a fifth synchronous clock signal PclkSyn [4] are disclosed.

Next, it is determined whether an edge of the ferry clock signal PCLK is detected (S203). Here, the edge sensing method may include a value different from the third synchronous clock signal PclkSyn [2] and the fourth synchronous clock signal PclkSyn [3], or the fourth synchronous clock signal PclkSyn [3]. ]) And the fifth synchronous clock signal PclkSyn [4], the first edge detection signal EdgeDetect1 or the second edge detection signal EdgeDetect2 is activated. In this regard, the following program code is possible.

"assign EdgeDetectl = PclkSyn [2] ＾ PclkSyn [3];

assign EdgeDetect2 = PclkSyn [3] ＾ PclkSyn [4]; "

If the edge of the ferry clock signal PCLK is detected, the standby cycle is driven to prevent the PSTB signal from being activated (S204). In this regard, the following program code is possible.

"dffnrnx2 uSA2state (S2_SA_StateD1, S2_SA_NextState, BCLK, BnRES);"

always @ (S2_SA_StateD1 or EdgeDetect1 or EdgeDetect2 or S1_SA_StateD1)

begin: SynWaitDecode

case (S2_SA_StateD1)

S2_SA_IDLE: // Idle cycle

if (S1_SA_StateD1 == S1_SA_WAIT)

begin

if (EdgeDetect1)

S2_SA_NextState = # GAT2 S2_SA_WAIT2;

else

if (EdgeDetect2)

S2_SA_NextState = # GAT2 S2_SA_WAIT1;

else

S2_SA_NextState = # GAT2 S2_SA_IDLE;

end

else

S2_SA_NextState = # GAT2 S2_SA_IDLE;

S2_SA_WAIT2: S2_SA_NextState = # GAT2 S2_SA_WAIT1;

S2_SA_WAIT1: S2_SA_NextState = # GAT2 S2_SA_IDLE;

default: S2_SA_NextState = # GAT2 S2_SA_IDLE;

endcase

end "

If the edge of the ferry clock signal PCLK is not detected, or after driving the standby cycle, by completing the synchronized ferry clock signal and activating the ferry strobe signal by the completed ferry clock signal, APB The register is accessed (S205).

The program as an example of the state switching program for implementing the register access method in the above-mentioned AMB AP chip of the present invention is as follows.

/ * ------------------------------------------------ ---------------------

Main APB state machine

* ------------------------------------------------- ------------------- * /

// State transition

dffnrnx2 uSA1state (S1_SA_StateD1, S1_SA_NextState, BCLK, BnRES);

// Output and next state logic generation

always @ (S1_SA_StateD1 or DSELSLowAPB or APBError or S2_SA_NextState)

begin: nextstatep

// Default assignments

S1_SA_NextState = S1_SA_IDLE;

case (S1_SA_StateD1)

S1_SA_IDLE: begin // If selected, insert wait cycle

if (DSELSLowAPB)

S1_SA_NextState = S1_SA_WAIT;

else

S1_SA_NextState = S1_SA_IDLE;

end

S1_SA_WAIT: begin // Wait cycle to set up address + data

if (APBError)

S1_SA_NextState = S1_SA_ERROR;

else // BCED

// Additional WAIT cycle needed for resynchronisation

// corner cases

if (S2_SA__NextState! = S2_SA_IDLE)

S1_SA_NextState = S1_SA_WAIT;

else

S1_SA_NextState = S1_SA_STROBE;

end

S1_SA_STROBE: begin // Strobe cycle to complete transaction

if (DSELSLowAPB)

S1_SA_NextState = S1_SA_WAIT;

else

S1_SA_NextState = S1_SA_IDLE;

end

S1_SA_ERROR: begin // undefined APB address area

if (DSELSLowAPB)

S1_SA_NextState = S1_SA_WAIT;

else

S1_SA_NextState = S1_SA_IDLE;

end

endcase

end

// Generate the BCLK-synchronized EDGE signals from PCLK

assign EdgeDetectl = PclkSyn [2] ＾ PclkSyn [3];

assign EdgeDetect2 = PclkSyn [3] ＾ PclkSyn [4];

// This adds another sub-state machine, to insert a further WAIT cycles

// to avoid PSTB becoming active with the setup and hold time

// before and after EITHER edge of PCLK

dffnrnx2 uSA2state (S2_SA_StateD1, S2_SA_NextState, BCLK, BnRES);

always @ (S2_SA_StateD1 or EdgeDetect1 or EdgeDetect2 or S1_SA_StateD1)

begin: SynWaitDecode

case (S2_SA_StateD1)

S2_SA_IDLE: // Idle cycle

if (S1_SA_StateD1 == S1_SA_WAIT)

begin

if (EdgeDetect1)

S2_SA_NextState = # GAT2 S2_SA_WAIT2;

else

if (EdgeDetect2)

S2_SA_NextState = # GAT2 S2_SA_WAIT1;

else

S2_SA_NextState = # GAT2 S2_SA_IDLE;

end

else

S2_SA_NextState = # GAT2 S2_SA_IDLE;

S2_SA_WAIT2: S2_SA_NextState = # GAT2 S2_SA_WAIT1;

S2_SA_WAIT1: S2_SA_NextState = # GAT2 S2_SA_IDLE;

default: S2_SA_NextState = # GAT2 S2_SA_IDLE;

endcase

end

// Re-synchronize PCLK to the BCLK domain

dffx5 uReSynPCLK ({PclkSyn [0], PclkSyn [1], PclkSyn [2], PclkSyn [3], PclkSyn [4]}, {PCLKraw, PclkSyn [0], PclkSyn [1], PclkSyn [2], PclkSyn [2] 3]}, BCLK);

3 is an exemplary view showing a waveform of a signal by the above-described program, and FIGS. 4A and 4B are state diagrams showing the operation of the above-described program.

First, the start is a state of S1_SA_IDLE, which represents an idle state in which a register access operation is not being performed. In this state, if the DSELSLowAPB is activated, the state goes to the state of S1_SA_WAIT, and if the DSELSLowAPB is not activated, the state remains in the state of S1_SA_IDLE. That is, if access to the APB register is required, the DSELSLowAPB is activated.

In the state of S1_SA_WAIT for generating the synchronized ferry clock signal, according to S2_SA__NextState, if S2_SA__NextState is not the state of S2_SA_IDLE, the state continues to the state of S1_SA_WAIT, and if the S2_SA__NextState is the state of S2_SA_IDLE, the state goes to S1_SA_STROBE state. In this case, when APBError is activated, an error has occurred, and therefore, the process moves to S1_SA_ERROR indicating an error. In the process of transitioning to the S1_SA_STROBE state, there is a lower state for detecting an edge. This will be described with reference to FIG. 4B.

First, the S2_SA_IDLE state is an idle state for transitioning to the standby state. When the EdgeDetect1 or EdgeDetect2 is not activated, no standby cycle is required, and thus the S2_SA_IDLE state is continuously in the S2_SA_IDLE state. If EdgeDetect1 is enabled, the state transitions to S2_SA_WAIT2 state, which inserts a wait cycle. Afterwards, when in the S2_SA_WAIT2 state, the S2_SA_IDLE state is always returned via the S2_SA_WAIT1 state. In addition, when EdgeDetect2 is activated, the state transitions to S2_SA_WAIT1 state and inserts a wait cycle. After that, when in the S2_SA_WAIT1 state, the state always returns to the S2_SA_IDLE state.

In the S1_SA_ERROR state indicating an error, when the DSELSLowAPB is activated, the state returns to the state of S1_SA_WAIT. When the DSELSLowAPB is not activated, the state is changed to the state of S1_SA_IDLE.

In the S1_SA_STROBE state, which accesses the APB register, when the DSELSLowAPB is activated, the state returns to the state of S1_SA_WAIT. If the DSELSLowAPB is not activated, the state is changed to the S1_SA_IDLE state.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited to the drawings shown.

The present invention has an advantage of preventing a malfunction when a register is accessed by driving a standby cycle so that the PSTB signal is not activated on the rising / falling edge of the ferry clock signal which is an internal operation clock when the AMBA APB register is accessed.

Claims (3)

Requiring APB register access for the APB connection; Sampling the ferry clock signal by an internal bus clock signal; Determining whether an edge of the ferry clock signal is detected; If an edge of the ferry clock signal is detected, driving a wait cycle; And If the edge of the ferry clock signal is not detected, or after performing the step of driving the standby cycle, completing the synchronized ferry clock signal and activating the ferry strobe signal according to the completed ferry clock signal to access the APB register. Register access method according to the AMAPA AP Bridge, characterized in that it comprises a. The method of claim 1, In the step of sampling the ferry clock signal by an internal bus clock signal, the ferry clock signal is divided into a first synchronous clock signal, a second synchronous clock signal, a third synchronous clock signal, a fourth synchronous clock signal and a fifth synchronous clock signal. 4-stage sampled A method of accessing a register in an AMAP AP bridge. The method of claim 2, In the determining whether an edge of the ferry clock signal is detected, when the value of the third synchronous clock signal and the fourth synchronous clock signal are different or the fourth synchronous clock signal and the fifth synchronous clock signal are different from each other. Judged by edge A method of accessing a register in an AMAP AP bridge.