KR20040002233A - Forming method for isolation of semiconductor device - Google Patents
Forming method for isolation of semiconductor device Download PDFInfo
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- KR20040002233A KR20040002233A KR1020020037680A KR20020037680A KR20040002233A KR 20040002233 A KR20040002233 A KR 20040002233A KR 1020020037680 A KR1020020037680 A KR 1020020037680A KR 20020037680 A KR20020037680 A KR 20020037680A KR 20040002233 A KR20040002233 A KR 20040002233A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Abstract
Description
본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로, 특히 트렌치를 형성하는 공정 중 소자분리영역과 활성영역의 경계면에 턱짐 ( moat ) 이 형성되는현상을 방지하여 소자의 전기적 특성을 향상시키는 기술에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a technique for improving the electrical characteristics of a device by preventing a phenomenon in which a moat is formed on the interface between the device isolation region and the active region during a trench formation process. It is about.
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디맨젼 ( dimension ) 을 축소하는 것과, 소자간에 존재하는 분리영역 ( isolation region ) 의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리기술이 메모리 셀 사이즈 ( memory cell size ) 를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of isolation regions existing between devices. Device isolation technology determines the memory cell size in terms of size.
소자분리절연막을 제조하는 종래기술로는 절연물 분리방식의 로코스 ( LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함 ) 방법, 실리콘기판상부에 산화막, 다결정실리콘층, 질화막 순으로 적층한 구조의 피.비.엘. ( Poly - Buffed LOCOS, 이하에서 PBL 이라 함 ) 방법, 기판에 홈을 형성한 후에 절연물질로 매립하는 트렌치 ( trench ) 방법 등이 있다.Conventional methods for manufacturing device isolation insulating films include LOCOS (LOCOS: LOCOS) method, and an oxide film, a polysilicon layer, and a nitride film stacked on the silicon substrate in this order. B.L. (Poly-Buffed LOCOS, hereinafter referred to as PBL) method, a trench method of embedding an insulating material after forming a groove in the substrate, and the like.
그러나, 상기 LOCOS 방법으로 소자분리산화막을 미세화할 때 공정상 또는 전기적인 문제가 발생한다. 그 중의 하나는, 소자분리절연막만으로는 전기적으로 소자를 완전히 분리할 수 없다는 것이다.However, a process or electrical problem occurs when the device isolation oxide film is miniaturized by the LOCOS method. One of them is that the device isolation insulating film alone cannot completely separate the devices.
그리고, 상기 PBL 을 사용하는 경우, 필드산화시에 산소의 측면확산에 의하여 버즈빅이 발생한다. 즉, 활성영역이 작아져 활성영역을 효과적으로 활용하지 못하며, 필드산화막의 두께가 두껍기 때문에 단차가 형성되어 후속공정에 어려움을 준다. 그리고, 기판상부의 다결정실리콘층으로 인하여 필드산화시 기판내부로 형성되는 소자분리절연막이 타기법에 비하여 상대적으로 작기 때문에 타기법에 비해 신뢰성을 약화시킬 수 있다.In the case of using the above-mentioned PBL, buzz big is generated by side diffusion of oxygen during field oxidation. In other words, the active area is small, so that the active area is not effectively utilized, and because the thickness of the field oxide film is thick, a step is formed, which causes difficulty in subsequent processes. Further, due to the polysilicon layer on the substrate, the device isolation insulating film formed inside the substrate during field oxidation is relatively smaller than that of the hitting method, thereby reducing the reliability of the hitting method.
이상에서 설명한 LOCOS 방법과 PBL 방법은 반도체기판 상부로 볼록한 소자분리절연막을 형성하여 단차를 갖게 됨으로써 후속공정을 어렵게 하는 단점이 있다.The LOCOS method and the PBL method described above have a disadvantage in that a subsequent step is made difficult by forming a convex element isolation insulating film on the semiconductor substrate and having a step.
이러한 단점을 해결하기 위하여, 반도체기판을 식각하여 트렌치를 형성하고 상기 트렌치를 매립한 다음, CMP 방법을 이용하여 상부면을 평탄화시키고 후속공정을 평탄화시킴으로써 후속공정을 용이하게 실시할 수 있도록 하였다.In order to solve this disadvantage, the semiconductor substrate is etched to form a trench, and the trench is buried, and then the CMP method is used to planarize the top surface and to planarize the subsequent process so that the subsequent process can be easily performed.
도시되지 않았으나, 종래기술에 따른 반도체소자의 소자분리막 형성방법을 설명하면 다음과 같다.Although not shown, a method of forming a device isolation film of a semiconductor device according to the prior art is as follows.
먼저, 반도체기판 상부에 패드산화막을 형성하고, 상기 패드산화막 상부에 질화막을 형성한다.First, a pad oxide film is formed over the semiconductor substrate, and a nitride film is formed over the pad oxide film.
그리고, 소자분리마스크를 이용한 식각공정으로 상기 질화막과 패드산화막 및 일정두께의 반도체기판을 식각하여 상기 반도체기판에 트렌치를 형성한다.In addition, a trench is formed in the semiconductor substrate by etching the nitride layer, the pad oxide layer, and the semiconductor substrate having a predetermined thickness by an etching process using an element isolation mask.
그 다음에, 상기 트렌치를 매립하는 산화막을 형성하고, 상기 산화막을 화학기계연마 ( chemical mechanical polishing, 이하에서 CMP 라 함 ) 하여 상부면을 평탄하게 형성한다.Next, an oxide film filling the trench is formed, and the oxide film is chemical mechanical polishing (hereinafter referred to as CMP) to form an upper surface flat.
그리고, 상기 질화막을 제거한다. 이때, 상기 질화막은 인산용액을 이용한 습식방법으로 제거한다.Then, the nitride film is removed. At this time, the nitride film is removed by a wet method using a phosphate solution.
그 다음에, 상기 패드산화막을 습식방법으로 제거하고, 상기 패드산화막이 제거된 반도체기판 상부에 게이트산화막을 형성하기 위하여 습식방법으로 세정공정을 실시한다.Next, the pad oxide film is removed by a wet method, and a cleaning process is performed by a wet method to form a gate oxide film on the semiconductor substrate from which the pad oxide film has been removed.
이때, 상기 트렌치를 매립하는 산화막과 반도체기판의 경계부, 다시말하면소자분리영역과 활성영역의 경계부에 위치한 상기 산화막이 상기 트렌치 안쪽으로 식각되는 턱짐 ( moat ) 이 발생하여 후속공정을 어렵게 할뿐만 아니라 반도체기판의 누설전류를 유발시킨다.At this time, the oxide layer filling the trench and the semiconductor substrate, that is, the oxide film located at the boundary between the device isolation region and the active region is etched into the trench, thereby making the subsequent process difficult. Cause leakage current of substrate.
최근에는 이러한 전기적 특성 열화를 방지하기 위하여 트렌치 형성후 소자분리영역과 활성영역의 경계부에 문턱전압 조절용 불순물을 임플란트하였다.Recently, in order to prevent such deterioration of electrical characteristics, an impurity for adjusting the threshold voltage is implanted at the boundary between the isolation region and the active region after trench formation.
그러나, 상기 임플란트 공정시 상기 트렌치 표면, 즉 측벽에 결함이 유발되고 후속 열처리공정시 상기 결함이 내부로 확산되어 소자의 특성 열화를 가속화하는 문제점이 있다.However, there is a problem in that defects are caused on the trench surface, that is, sidewalls during the implant process, and the defects are diffused inside during the subsequent heat treatment process, thereby accelerating deterioration of device characteristics.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 소자분리막과 반도체기판의 경계부에 턱짐 현상이 유발되지 않도록 하여 전계집중에 의한 접합 누설전류를 감소시킬 수 있도록 하는 반도체소자의 소자분리막 형성방법을 제공하는데 그 목적이 있다.The present invention provides a method of forming a device isolation film of a semiconductor device to reduce the junction leakage current due to electric field concentration so as not to cause a buckling phenomenon at the boundary between the device isolation film and the semiconductor substrate in order to solve the above problems of the prior art. The purpose is to provide.
도 1a 내지 도 1i 는 본 발명의 실시예에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도.1A to 1I are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11 : 반도체기판13 : 제1산화막11: semiconductor substrate 13: first oxide film
15 : 제1질화막17 : 제2산화막15: first nitride film 17: second oxide film
19 : 제2산화막21 : 산화막 스페이서19: second oxide film 21: oxide film spacer
23 : 트렌치25,ⓐ : 버즈빅23: trench 25, ⓐ: buzz big
27 : 제1열산화막,희생열산화막29 : 제2열산화막27: first thermal oxide film, sacrificial thermal oxide film 29: second thermal oxide film
31 : 제3질화막33 : 매립절연막31: third nitride film 33: buried insulating film
35 : 제3열산화막,희생열산화막37 : 게이트절연막35: third thermal oxide film, sacrificial thermal oxide film 37: gate insulating film
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 소자분리막 형성방법은,In order to achieve the above object, a device isolation film forming method of a semiconductor device according to the present invention,
반도체기판 상부에 제1산화막, 제1질화막, 제2산화막 및 제2질화막을 적층하는 공정과,Stacking a first oxide film, a first nitride film, a second oxide film, and a second nitride film on the semiconductor substrate;
소자분리마스크를 이용한 사진식각공정으로 상기 제2질화막 및 제2산화막을 식각하고 그 측벽에 산화막 스페이서를 형성하는 공정과,Etching the second nitride film and the second oxide film by a photolithography process using a device isolation mask and forming oxide spacers on sidewalls thereof;
상기 제2질화막 및 산화막 스페이서를 마스크로 하여 상기 제1질화막, 제1산화막 및 일정두께의 반도체기판을 식각하여 트렌치를 형성하고 상기 산화막 스페이서를 제거하는 공정과,Etching the first nitride film, the first oxide film and the semiconductor substrate having a predetermined thickness to form a trench by using the second nitride film and the oxide spacer as a mask, and removing the oxide spacer;
상기 트렌치 표면에 열산화막을 형성하되, 상기 트렌치 측벽 상측에 소정 크기의 버즈빅을 형성하는 공정과,Forming a thermal oxide film on the trench surface and forming a buzz beak on the trench sidewall;
전체표면상부에 제3질화막을 형성하고 그 상부에 상기 트렌치를 매립하는 매립절연막을 형성하는 공정과,Forming a third nitride film over the entire surface and forming a buried insulating film filling the trench thereon;
상기 매립절연막을 CMP 하고, 이를 상기 제1질화막보다 낮게 습식식각하는 공정과,CMP the buried insulating film, and wet etching the buried insulating film lower than the first nitride film;
상기 반도체기판 상부의 제3,2,1질화막과 제2,1산화막을 각각 인산용액과 불순용액을 이용하여 제거하는 공정을 포함하는 것과,Removing the third, second, and first nitride films and the second and the first oxide films on the semiconductor substrate by using a phosphoric acid solution and an impurity solution, respectively;
상기 제1산화막은 열산화공정을 이용하여 30 ∼ 300 Å 두께로 형성하는 것과,The first oxide film is formed to a thickness of 30 ~ 300 Å using a thermal oxidation process,
상기 제1질화막과 제2산화막은 각각 30 ∼ 300 Å 정도의 두께로 형성하는 것과,The first nitride film and the second oxide film are each formed in a thickness of about 30 to 300 kPa,
상기 제2산화막은 300 ∼ 3000 Å 정도의 두께로 형성하는 것과,The second oxide film is formed to a thickness of about 300 ~ 3000 Å,
상기 산화막 스페이서는 전체표면상부에 산화막을 50 ∼ 500 Å 두께로 형성하고 이를 이방성식각하여 형성하는 것과,The oxide film spacer is formed by forming an oxide film on the entire surface to 50 ~ 500 표 thickness and anisotropically etching it,
상기 트렌치는 1000 ∼ 5000 Å 깊이로 형성하는 것과,The trench is formed to a depth of 1000 ~ 5000 ,,
상기 열산화막은 산소가스 분위기에서 건식방법으로 열산화시켜 형성하는 것과,The thermal oxide film is formed by thermal oxidation in a dry method in an oxygen gas atmosphere,
상기 열산화막은 50 ∼ 300 Å 두께로 형성하는 것과,The thermal oxidation film is formed to a thickness of 50 to 300 kPa,
상기 제3질화막을 30 ∼ 300 Å 두께로 형성하는 것과,Forming the third nitride film in a thickness of 30 to 300 GPa;
상기 매립절연막은 CVD 절연막인 것과,The buried insulating film is a CVD insulating film,
상기 매립절연막의 습식식각공정은 상기 반도체기판보다 0 ∼ 500 Å 두껍게 남기는 것을 특징으로 한다.The wet etching process of the buried insulating film is characterized in that it is left 0 ~ 500 Å thicker than the semiconductor substrate.
한편, 본 발명의 원리는,On the other hand, the principle of the present invention,
패드산화막과 완충질화막의 사용으로 적절한 버즈빅을 형성하고 라이너 질화막을 연속 사용함으로써 패드산화막 식각시 모서리부분에서 침투하는 습식식각 용액의 침투를 줄이고 트렌치의 측벽과 기판 표면이 이루는 모서리를 라운딩지게 형성함으로써 전계집중에 의한 접합 누설전류를 감소시켜 소자의 전기적 특성을 향상시키는 것이다.By using a pad oxide film and a buffer nitride film to form an appropriate buzz big and continuous use of the liner nitride film to reduce the penetration of the wet etching solution that penetrates the edge portion during the pad oxide film etching and to form a rounded corner between the trench sidewall and the substrate surface It is to improve the electrical characteristics of the device by reducing the junction leakage current caused by the field concentration.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1i 는 본 발명의 실시예에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도이다.1A to 1I are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 실리콘으로 형성된 반도체기판(11) 상부에 패드산화막인 제1산화막(13), 제1질화막(15), 제2산화막(17) 및 마스크 질화막인 제2질화막(19)을 순차적으로 적층한다.Referring to FIG. 1A, a first oxide layer 13, a first nitride layer 15, a second oxide layer 17, and a second nitride layer 19, which is a mask nitride layer, are formed on a semiconductor substrate 11 formed of silicon. Laminate sequentially.
이때, 상기 제1산화막(13)은 열산화공정을 이용하여 30 ∼ 300 Å 정도의 두께로 형성한다.At this time, the first oxide film 13 is formed to a thickness of about 30 to 300 kPa using a thermal oxidation process.
상기 제1질화막(15)과 제2산화막(17)은 30 ∼ 300 Å 정도의 두께로 형성한다.The first nitride film 15 and the second oxide film 17 are formed to a thickness of about 30 to 300 Å.
상기 제2산화막(13)은 300 ∼ 3000 Å 정도의 두께로 형성한다.The second oxide film 13 is formed to a thickness of about 300 to 3000 GPa.
그 다음, 소자분리마스크(도시안됨)를 이용한 사진식각공정으로 상기 제2질화막(19) 및 제2산화막(17)을 식각하여 활성영역을 정의하는 소자분리영역을 정의한다.Next, the second isolation layer 19 and the second oxide layer 17 are etched by a photolithography process using a device isolation mask (not shown) to define a device isolation region that defines an active region.
도 1b를 참조하면, 상기 제2질화막(19)과 제2산화막(17) 측벽에 산화막 스페이서(21)를 형성한다.Referring to FIG. 1B, an oxide spacer 21 is formed on sidewalls of the second nitride layer 19 and the second oxide layer 17.
이때, 상기 산화막 스페이서(21)는 전체표면상부에 산화막을 50 ∼ 500 Å 두께로 형성하고, 이를 이방성식각하여 형성한다.At this time, the oxide film spacer 21 is formed on the entire surface of the oxide film with a thickness of 50 to 500 Å, and is formed by anisotropic etching.
도 1c를 참조하면, 상기 제2질화막(19) 및 산화막 스페이서(21)를 마스크로 하여 상기 제1질화막(15), 제1산화막(13) 및 일정두께의 반도체기판(11)을 순차적으로 식각하여 소자분리영역에 트렌치(23)를 형성한다. 여기서, 상기 트렌치(23)는 1000 ∼ 5000 Å 깊이로 형성한다.Referring to FIG. 1C, the first nitride film 15, the first oxide film 13, and the semiconductor substrate 11 having a predetermined thickness are sequentially etched using the second nitride film 19 and the oxide spacer 21 as a mask. The trench 23 is formed in the device isolation region. Here, the trench 23 is formed to a depth of 1000 ~ 5000 mm.
그리고, 상기 산화막 스페이서(21)를 습식방법으로 제거한다.Then, the oxide spacer 21 is removed by a wet method.
도 1d를 참조하면, 상기 트렌치(23) 표면을 700 ∼ 1100 ℃ 온도에서 열산화시켜 제1열산화막(27)을 30 ∼ 300 Å 두께로 형성한다.Referring to FIG. 1D, the surface of the trench 23 is thermally oxidized at a temperature of 700 to 1100 ° C. to form a first thermal oxide film 27 in a thickness of 30 to 300 kPa.
이때, 상기 트렌치(23) 측벽과 기판(11) 표면이 이루는 부분에 버즈빅(25)이 형성된다.In this case, a buzz bee 25 is formed at a portion formed between the sidewalls of the trench 23 and the surface of the substrate 11.
도 1e를 참조하면, 상기 제1희생산화막(27)을 습식식각공정으로 제거하고,노출된 기판을 산소가스 분위기에서 건식방법으로 열산화시켜 상기 트렌치(23) 표면에 제2열산화막(29)을 50 ∼ 300 Å 두께로 형성한다.Referring to FIG. 1E, the first rare oxidized film 27 is removed by a wet etching process, and the exposed substrate is thermally oxidized by a dry method in an oxygen gas atmosphere to form a second thermal oxide film 29 on the surface of the trench 23. To form a thickness of 50 to 300 mm 3.
이때, 소자분리영역과 활성영역의 경계부인 트렌치(23) 측벽과 기판(11) 표면이 이루는 모서리 부분에 제2열산화막(29)이 ⓐ 와 같이 라운딩되어 버즈빅 형상이 완성된다. 그리고, 상기 제1질화막(15)이 얇기 때문에 버즈빅의 형성이 용이하다.At this time, the second thermal oxide film 29 is rounded at an edge formed by the sidewalls of the trench 23, which is a boundary between the device isolation region and the active region, and the surface of the substrate 11, to form a buzz big shape. In addition, since the first nitride film 15 is thin, it is easy to form a bird's beak.
여기서, 상기 습식식각공정은 상기 제2산화막(17)을 일정두께 측면식각(도시안됨)하여 ⓐ 부분을 크게 형성된다.In the wet etching process, the second oxide layer 17 is side-etched (not shown) by a predetermined thickness to form a large ⓐ portion.
도 1f를 참조하면, 전체표면상부에 제3질화막(31)을 30 ∼ 300 Å 두께로 형성하여, 후속 열처리 공정에 의한 산소의 확산을 방지하는 역할을 한다.Referring to FIG. 1F, the third nitride film 31 is formed to have a thickness of 30 to 300 kPa over the entire surface, thereby preventing oxygen diffusion by a subsequent heat treatment process.
도 1g를 참조하면, 상기 트렌치(23)를 매립하는 매립절연막(33)을 전체표면상부에 형성하고, 상기 제3질화막(31)을 노출시키는 CMP 공정을 실시한다.Referring to FIG. 1G, a buried insulating film 33 filling the trench 23 is formed on the entire surface, and a CMP process of exposing the third nitride film 31 is performed.
이때, 상기 매립절연막(33)은 오존-테오스 ( O3-TEOS ) 나 고밀도플라즈마 CVD 산화막과 같이 CVD 방법을 이용하여 형성할 수 있는 산화막으로 형성한 것이다.In this case, the buried insulating film 33 is formed of an oxide film that can be formed by using a CVD method, such as ozone-theos (O 3 -TEOS) or high density plasma CVD oxide film.
그 다음, 습식방법으로 상기 매립절연막(33)을 식각하되, 상기 제1질화막(15)보다 낮고, 상기 반도체기판(11)보다 0 ∼ 500 Å 두껍게 실시한다.Subsequently, the buried insulating film 33 is etched by a wet method, but lower than the first nitride film 15 and 0 to 500 Å thicker than the semiconductor substrate 11.
이때, 상기 제3질화막(31)의 일부가 식각되어 상기 제2질화막(19) 상측의 제3질화막(31)이 제거될 수도 있다.In this case, a part of the third nitride film 31 may be etched to remove the third nitride film 31 above the second nitride film 19.
도 1h를 참조하면, 인산용액을 이용하여 노출된 제3,2질화막(31,19)를 제거하고, 불산용액으로 제2산화막(17)을 제거한 다음, 상기 제1질화막(15)을 인산용액으로 제거하고, 상기 제1산화막(13)인 패드산화막을 불산용액으로 제거한다.Referring to FIG. 1H, the exposed third and second nitride films 31 and 19 are removed using a phosphoric acid solution, the second oxide film 17 is removed with a hydrofluoric acid solution, and the first nitride film 15 is then replaced with a phosphoric acid solution. The pad oxide film, which is the first oxide film 13, is removed with a hydrofluoric acid solution.
이때, 소자분리영역과 활성영역의 경계부에 도 1e 의 ⓐ 와 같은 라운딩된 부분이 형성되어 턱짐 ( moat ) 현상이 유발되지 않는다.At this time, a rounded portion, such as ⓐ of FIG. 1E, is formed at the boundary between the device isolation region and the active region, so that a moat phenomenon does not occur.
그 다음, 상기 반도체기판(11) 표면에 제3열산화막(35)을 형성하고 반도체소자의 제조 공정에 필요한 이온주입공정을 실시한다.Next, a third thermal oxide film 35 is formed on the surface of the semiconductor substrate 11, and an ion implantation process necessary for the manufacturing process of the semiconductor device is performed.
도 1i를 참조하면, 상기 제3열산화막(35)을 불산용액으로 제거하고 상기 반도체기판(11)에 게이트산화막(37)을 형성함으로써 상기 트렌치(23)를 매립하는 매립절연막(33)으로 소자분리막을 형성한다.Referring to FIG. 1I, the buried insulating film 33 filling the trench 23 is formed by removing the third thermal oxide film 35 with a hydrofluoric acid solution and forming a gate oxide film 37 on the semiconductor substrate 11. A separator is formed.
본 발명의 실시예에 사용된 제1열산화막(27)과 제3열산화막(35)은 반도체소자의 특성 열화를 방지하기 위하여 제조 공정 중에 형성된 후 제거되는 희생 절연막이다.The first thermal oxide film 27 and the third thermal oxide film 35 used in the embodiment of the present invention are sacrificial insulating films that are removed after being formed during the manufacturing process to prevent deterioration of characteristics of the semiconductor device.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 소자분리막 형성방법은, 소자분리영역과 활성영역의 계면부에 형성되는 턱짐 ( moat ) 현상을 방지하기 위하여 적정한 버즈빅을 형성함으로써 소자의 전기적 특성을 향상시키는 효과를 제공한다.As described above, in the method of forming a device isolation film of a semiconductor device according to the present invention, the electrical characteristics of the device may be improved by forming an appropriate buzz big in order to prevent a moat phenomenon formed at the interface between the device isolation region and the active region. Provide the effect of improving.
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| KR100575343B1 (en) * | 2004-09-10 | 2006-05-02 | 주식회사 하이닉스반도체 | Method for manufacturing flash memory device |
| KR100713344B1 (en) * | 2005-12-28 | 2007-05-04 | 동부일렉트로닉스 주식회사 | Method for fabricating semiconductor device |
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| JP3519589B2 (en) * | 1997-12-24 | 2004-04-19 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor integrated circuit |
| KR19990086523A (en) * | 1998-05-28 | 1999-12-15 | 윤종용 | Semiconductor device manufacturing method |
| KR20010008607A (en) * | 1999-07-02 | 2001-02-05 | 김영환 | Method of forming isolation layer in semiconductor device |
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| KR100575343B1 (en) * | 2004-09-10 | 2006-05-02 | 주식회사 하이닉스반도체 | Method for manufacturing flash memory device |
| US7691721B2 (en) | 2004-09-10 | 2010-04-06 | Hynix Semiconductor Inc. | Method for manufacturing flash memory device |
| KR100713344B1 (en) * | 2005-12-28 | 2007-05-04 | 동부일렉트로닉스 주식회사 | Method for fabricating semiconductor device |
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