KR20040001866A - Method for fabricating capacitor - Google Patents
Method for fabricating capacitor Download PDFInfo
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- KR20040001866A KR20040001866A KR1020020037200A KR20020037200A KR20040001866A KR 20040001866 A KR20040001866 A KR 20040001866A KR 1020020037200 A KR1020020037200 A KR 1020020037200A KR 20020037200 A KR20020037200 A KR 20020037200A KR 20040001866 A KR20040001866 A KR 20040001866A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 캐패시터의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a capacitor.
최근에 반도체 소자가 고집적화됨에 따라 충분한 정전용량을 확보하기 위해 캐패시터의 구조를 실린더(Cylinder), 핀(Pin), 적층(Stack) 또는 반구형 실리콘(HSG) 등의 복잡한 구조로 형성하여 전하저장 면적을 증가시키거나, SiO2, SiON 또는 Si3N4에 비해 유전상수가 큰 Al2O3, Ta2O5, TaON, TiO2, SrTiO3, (Ba,Sr)TiO등의 고유전물질에 대한 연구가 활발히 진행되고 있다.In recent years, as semiconductor devices have been highly integrated, in order to secure sufficient capacitance, the capacitor structure is formed into a complex structure such as cylinder, pin, stack, or hemispherical silicon (HSG) to improve charge storage area. For high dielectric materials such as Al 2 O 3 , Ta 2 O 5 , TaON, TiO 2 , SrTiO 3 , (Ba, Sr) TiO, or higher dielectric constants compared to SiO 2 , SiON or Si 3 N 4 . Research is actively underway.
특히, Ta2O5는 유전율(ε)이 25 정도로 SiON(ε=7)보다 유전율이 3∼4배정도 높아 고집적 캐패시터에 적용 가능성이 크다.In particular, Ta 2 O 5 has a dielectric constant (ε) of about 25 and a dielectric constant of about 3 to 4 times higher than SiON (ε = 7), and thus is highly applicable to a high density capacitor.
도 1은 종래기술의 일예에 따른 캐패시터를 도시한 도면이다.1 is a view showing a capacitor according to an example of the prior art.
도 1을 참조하면, 하부전극인 제1 도우프드 폴리실리콘막(doped polysilicon)(11)상에 탄탈륨산화막(Ta2O5)(12)이 형성되고, 탄탈륨산화막(12)상에 상부전극인 제2 도우프드 폴리실리콘막(14)이 형성된다.Referring to FIG. 1, a tantalum oxide film Ta 2 O 5 12 is formed on a first doped polysilicon 11 as a lower electrode, and an upper electrode on a tantalum oxide film 12. The second doped polysilicon film 14 is formed.
그리고, 탄탈륨산화막(12)과 상부전극용 도우프드 폴리실리콘막(14) 사이에 확산방지막으로서 티타늄나이트라이드(TiN)(13)가 삽입된다.Then, titanium nitride (TiN) 13 is inserted between the tantalum oxide film 12 and the doped polysilicon film 14 for the upper electrode as a diffusion barrier.
상술한 종래기술의 일예에서는, 탄탈륨산화막(12) 증착후 후속 열처리 과정에서 하부전극인 제1 도우프드 폴리실리콘막(12)과의 계면반응을 통해 생성되는 계면 생성물(15)로 인해 기생캐패시터가 형성됨에 따라 전체 캐패시턴스값을 크게 저하시키는 문제가 있다.In the above-described example of the prior art, the parasitic capacitor is caused by the interfacial product 15 generated through the interfacial reaction with the first doped polysilicon film 12, which is the lower electrode, in the subsequent heat treatment process after the deposition of the tantalum oxide film 12. As it is formed, there is a problem of greatly lowering the total capacitance value.
즉, 탄탈륨산화막(12) 증착시 산소를 포함하고 있는 소스물질인 탄탈륨에칠레이트 [Ta(O(C2H5)2)5]와 반응가스로 추가되는 산소(O2)가 하부전극인 제1 도우프드 폴리실리콘막(12)을 산화시키게 되며, 탄탈륨산화막(12) 증착후 저온 N20 플라즈마처리와 고온 N20 열처리시 활성화된 산소가 제1 도우프드 폴리실리콘막과의 반응을 보다 촉진시킨다.In other words, tantalum acrylate [Ta (O (C 2 H 5 ) 2 ) 5 ], which is a source material containing oxygen when the tantalum oxide film 12 is deposited, and oxygen (O 2 ) added as a reaction gas are lower electrodes. After the first doped polysilicon layer 12 is oxidized, activated oxygen reacts with the first doped polysilicon layer during the low temperature N 2 0 plasma treatment and the high temperature N 2 0 heat treatment after the deposition of the tantalum oxide layer 12. It promotes more.
이때, 제1 도우프드 폴리실리콘막(11)과 탄탈륨산화막(12) 사이에 형성된 계면생성물(15)인 산화물[SiO2, ε=3.8]은 다음과 같이 캐패시턴스값을 낮추는 역할을 한다.At this time, the oxide [SiO 2 , ε = 3.8], which is an interfacial product 15 formed between the first doped polysilicon film 11 and the tantalum oxide film 12, serves to lower the capacitance value as follows.
먼저, 계면 생성물이 없을 경우, 전체 캐패시턴스(Ctot)는 C탄탈륨산화막인데 반해, 계면생성물인 산화물이 형성된 경우에는 전체 캐패시턴스(Ctot)가로 낮아진다.First, in the absence of an interfacial product, the total capacitance (C tot ) is a C tantalum oxide film , whereas in the case where an oxide, which is an interfacial product, is formed, the total capacitance (C tot ) is Lowers.
[수학식2]에서, 계면생성물이 형성된 경우에는, 전체 캐패시턴스의 감소량(ΔC)은 계면생성물의 유전상수와 계면생성물의 두께에 의존하게 됨을 알 수 있다.In Equation 2, when the interface product is formed, it can be seen that the decrease amount ΔC of the total capacitance depends on the dielectric constant of the interface product and the thickness of the interface product.
이와 같은 전체 캐패시턴스값의 감소를 최소화하기 위해, 제1 도우프드 폴리실리콘막(11) 형성후 계면층으로 실리콘나이트라이드막(SiN)을 50Å 두께로 형성시켜 산소의 제1 도우프드 폴리실리콘막(11)으로의 확산을 방지하는 확산방지막으로 사용하고 있다.In order to minimize the reduction of the total capacitance value, after forming the first doped polysilicon film 11, a silicon nitride film (SiN) is formed to a thickness of 50 μs as an interfacial layer to form a first doped polysilicon film of oxygen ( 11) It is used as a diffusion barrier to prevent diffusion into.
도 2는 종래기술의 다른예에 따른 캐패시터를 도시하고 있다.2 shows a capacitor according to another example of the prior art.
도 2를 참조하면, 하부전극인 제1 도우프드 폴리실리콘막(11)상에 탄탈륨산화막(Ta2O5)(12)이 형성되고, 탄탈륨산화막(12)상에 상부전극인 제2 도우프드 폴리실리콘막(14)이 형성된다.Referring to FIG. 2, a tantalum oxide film (Ta 2 O 5 ) 12 is formed on a first doped polysilicon film 11 as a lower electrode, and a second doped as an upper electrode on a tantalum oxide film 12. The polysilicon film 14 is formed.
그리고, 탄탈륨산화막(12)과 상부전극용 도우프드 폴리실리콘막(14) 사이에 확산방지막으로서 티타늄나이트라이드(TiN)(13)가 삽입되며, 제1 도우프드 폴리실리콘막(11)과 탄탈륨산화막(12) 사이에 산소확산방지막으로서 실리콘나이트라이드막(16)이 삽입된다.Then, a titanium nitride (TiN) 13 is inserted between the tantalum oxide film 12 and the doped polysilicon film 14 for the upper electrode, and the first doped polysilicon film 11 and the tantalum oxide film are inserted. A silicon nitride film 16 is interposed between the parts 12 as an oxygen diffusion preventing film.
그러나, 50Å 두께의 얇은 실리콘나이트라이드막(16)으로는 산소에 대한 확산방지막의 역할을 충분히 수행하지 못하며, 이로 인해 제1 도우프드 폴리실리콘막(11)이 산화되어 계면생성물(15)인 산화물이 여전히 형성되는 문제가 있다.However, the thin silicon nitride film 16 having a thickness of 50 Å does not sufficiently serve as a diffusion barrier against oxygen, and as a result, the first doped polysilicon film 11 is oxidized to form an oxide as an interfacial product 15. There is still a problem that is formed.
이를 해결하기 위해 실리콘나이트라이드막의 두께를 증가시켜 산소 확산에 대한 저항력을 증대시키는 방법이 제안되었으나, 유전상수값이 7∼8인 실리콘나이트라이드막의 두께가 증가함에 따라 역시 계면 캐패시턴스값으로 작용하여 전체 캐패시턴스를 감소시키게 되므로 두께를 증가시키는데 한계가 있다.In order to solve this problem, a method of increasing the silicon nitride film thickness to increase the resistance to oxygen diffusion has been proposed, but as the thickness of the silicon nitride film having a dielectric constant of 7 to 8 increases, it also acts as an interface capacitance value. Since the capacitance is reduced, there is a limit to increasing the thickness.
따라서, 산화에 대한 저항성이 큰 내열금속막(refractory metal)을 하부전극으로 사용하려는 시도가 이루어지고 있으나, 계면생성물인 금속산화물의 두께 조절이나 실린더 구조 형성 공정인 포토리소그래피 및 식각 작업에서 어려움을 겪고 있다.Therefore, attempts have been made to use refractory metals having high resistance to oxidation as lower electrodes, but have difficulties in photolithography and etching operations for controlling the thickness of metal oxides, which are interfacial products, and forming cylinder structures. have.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 후속 열처리 과정에서 유전막으로부터 하부전극으로의 산소확산을 방지하는데 적합한 캐패시터의 제조 방법을 제공함에 그 목적이 있다.The present invention has been made to solve the problems of the prior art, an object of the present invention is to provide a method of manufacturing a capacitor suitable for preventing oxygen diffusion from the dielectric film to the lower electrode in the subsequent heat treatment process.
도 1은 종래기술의 일예에 따른 캐패시터를 도시한 도면,1 is a view showing a capacitor according to an example of the prior art,
도 2는 종래기술의 다른예에 따른 캐패시터를 도시한 도면,2 illustrates a capacitor according to another example of the prior art;
도 3a 내지 도 3f는 본 발명의 실시예에 따른 캐패시터의 제조 방법을 도시한 공정 단면도,3A to 3F are cross-sectional views illustrating a method of manufacturing a capacitor according to an embodiment of the present invention;
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 제1 도우프드 폴리실리콘막 22 : 실리콘나이트라이드막21 first doped polysilicon film 22 silicon nitride film
23 : 비정질 제1 탄탈륨산화막 24 : 비정질 제2 탄탈륨산화막23 amorphous first tantalum oxide film 24 amorphous second tantalum oxide film
25 : 결정질 탄탈륨산화막 26 : 질소집적층25 crystalline tantalum oxide film 26 nitrogen accumulation layer
27 : 티타늄나이트라이드막 28 : 제2 도우프드 폴리실리콘막27: titanium nitride film 28: second doped polysilicon film
상기 목적을 달성하기 위한 본 발명의 캐패시터의 제조 방법은 하부전극상에 질소가 함유된 산소확산방지막을 형성하는 단계, 상기 산소확산방지막상에 제1 두께의 비정질 유전막을 형성하는 단계, 상기 비정질 유전막과 상기 산소확산방지막내에 질소원자를 함유시키는 단계, 상기 비정질 유전막상에 상기 제1 두께보다 두꺼운 제2 두께의 상기 비정질 유전막을 추가로 형성하는 단계, 상기 비정질 유전막을 결정화시키기 위한 열처리과정을 수행하는 단계, 및 상기 결정화된 유전막상에 상부전극을 형성하는 단계를 포함함을 특징으로 하고, 상기 질소원자를 함유시키는 단계는 질소를 함유한 가스 분위기에서 플라즈마처리하는 것을 특징으로 하며, 상기 플라즈마처리는, 암모니아, 질소 또는 암모니아와 질소의 혼합가스 분위기에서진행하되, 1torr∼2torr의 압력을 유지하는 것을 특징으로 한다.A method of manufacturing a capacitor of the present invention for achieving the above object is to form an oxygen diffusion barrier containing nitrogen on the lower electrode, the step of forming an amorphous dielectric film of a first thickness on the oxygen diffusion barrier, the amorphous dielectric film And incorporating a nitrogen atom into the oxygen diffusion preventing film, further forming the amorphous dielectric film having a second thickness thicker than the first thickness on the amorphous dielectric film, and performing a heat treatment process to crystallize the amorphous dielectric film. And forming an upper electrode on the crystallized dielectric film, wherein the step of containing nitrogen atoms is performed by plasma treatment in a gas atmosphere containing nitrogen. Is carried out in ammonia, nitrogen or a mixed gas atmosphere of ammonia and nitrogen, wherein It is characterized by maintaining the pressure of 2torr.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 3a 내지 도 3f는 본 발명의 실시예에 따른 캐패시터의 제조 방법을 도시한 공정 단면도이다.3A to 3F are cross-sectional views illustrating a method of manufacturing a capacitor according to an embodiment of the present invention.
도 3a에 도시된 바와 같이, 하부전극인 제1 도우프드 폴리실리콘막(21)상에 산소확산방지막으로서 실리콘나이트라이드막(22)을 형성한다.As shown in FIG. 3A, a silicon nitride film 22 is formed on the first doped polysilicon film 21 as a lower electrode as an oxygen diffusion preventing film.
이때, 제1 도우프드 폴리실리콘막(21)은 PH3가스를 이용한 인시튜도핑(in-situ doping)법으로 형성하되, 인(Phosphorous; P)의 농도는 3.0 ×1020atoms/cc로 유지한다. 한편, 제1 도우프드 폴리실리콘막(21)은 1000Å의 두께로 증착된다.In this case, the first doped polysilicon film 21 is formed by an in-situ doping method using a PH 3 gas, but the concentration of phosphorous (P) is maintained at 3.0 × 10 20 atoms / cc. do. On the other hand, the first doped polysilicon film 21 is deposited to a thickness of 1000 kPa.
그리고, 실리콘나이트라이드막(22)은 제1 도우프드 폴리실리콘막(21)을 형성한 후 급속질화처리(Rapid Thermal Nitridation) 공정을 수행하여 형성하는데, 급속질화처리공정 수행시 온도는 600℃∼1000℃이고, 실리콘나이트라이드막(22)은 20Å∼30Å 두께로 형성된다.The silicon nitride film 22 is formed by performing a rapid thermal nitridation process after forming the first doped polysilicon film 21. When the rapid nitriding process is performed, the temperature is 600 ° C. to At 1000 ° C., the silicon nitride film 22 is formed to a thickness of 20 to 30 Å.
도 3b에 도시된 바와 같이, 실리콘나이트라이드막(22)상에 비정질 제1 탄탈륨산화막(23)을 형성한다.As shown in FIG. 3B, an amorphous first tantalum oxide film 23 is formed on the silicon nitride film 22.
이때, 비정질 제1 탄탈륨산화막(23)은 탄탈륨에칠레이트[Ta(O(C2H5)2)5]를 소스물질로 하고 산소(O2)를 반응가스로 하는 금속유기화학기상증착법(Metal Organic Chemical Vapor Deposition; MOCVD)을 통해 20Å∼40Å의 두께로 형성된다.At this time, the amorphous first tantalum oxide film 23 is a metal organic chemical vapor deposition method using a tantalum acrylate (Ta (O (C 2 H 5 ) 2 ) 5 ) as a source material and oxygen (O 2 ) as a reaction gas. Metal Organic Chemical Vapor Deposition (MOCVD) to form a thickness of 20 ~ 40Å.
도 3c에 도시된 바와 같이, 비정질 제1 탄탈륨산화막(23)상에 질소원자를 포함하는 분위기가스에서 플라즈마처리한다.As shown in FIG. 3C, plasma treatment is performed on an amorphous first tantalum oxide film 23 in an atmosphere gas containing nitrogen atoms.
이때, 플라즈마처리시, 압력은 1torr∼2torr을 유지하며, 분위기가스는 암모니아(NH3), 질소(N2) 또는 암모니아(NH3)와 질소(N2)의 혼합가스를 이용한다.At this time, in the plasma treatment, the pressure is maintained at 1 tor to 2 torr, and the atmosphere gas uses ammonia (NH 3 ), nitrogen (N 2 ) or a mixed gas of ammonia (NH 3 ) and nitrogen (N 2 ).
전술한 플라즈마처리후, 비정질 제1 탄탈륨산화막(23)에 질소(N) 원자가 고용되며, 플라즈마처리후에도 비정질 제1 탄탈륨산화막(23)은 상변이없이 비정질상태를 유지한다. 그리고, 플라즈마처리후, 실리콘나이트라이드막(22)은 질소원자의 함유량이 증가된 질소부화(Nitrogen rich) 실리콘나이트라이드막(22a)으로 개질된다.After the plasma treatment described above, nitrogen (N) atoms are dissolved in the amorphous first tantalum oxide film 23, and the amorphous first tantalum oxide film 23 remains in an amorphous state without phase change even after the plasma treatment. After the plasma treatment, the silicon nitride film 22 is modified to a nitrogen rich silicon nitride film 22a having an increased content of nitrogen atoms.
도 3d에 도시된 바와 같이, 질소원자가 고용된 비정질 제1 탄탈륨산화막(23a)상에 비정질 제2 탄탈륨산화막(24)을 형성한다.As shown in FIG. 3D, an amorphous second tantalum oxide film 24 is formed on the amorphous first tantalum oxide film 23a in which nitrogen atoms are dissolved.
이때, 비정질 제2 탄탈륨산화막(24)은 탄탈륨에칠레이트[Ta(O(C2H5)2)5]를 소스물질로 하고 산소(O2)를 반응가스로 하는 금속유기화학기상증착법(MOCVD)을 통해 40Å∼60Å의 두께로 형성된다.At this time, the amorphous second tantalum oxide film 24 is a metal organic chemical vapor deposition method using a tantalum acrylate (Ta (O (C 2 H 5 ) 2 ) 5 ] as a source material and oxygen (O 2 ) as a reaction gas). MOCVD) to form a thickness of 40 kPa to 60 kPa.
한편, 비정질 제2 탄탈륨산화막(24)이 비정질 제1 탄탈륨산화막(23a)에 비해 두껍게 증착하기 위해서 장시간의 증착시간이 요구됨에 따라 산소가 확산할 수 있으나, 비정질 제1 탄탈륨산화막(23a)내에 질소원자가 고용되고 더욱이 질소부화 실리콘나이트라이드막(22a)이 존재하기 때문에 비정질 제2 탄탈륨산화막(24)의 장시간의 증착공정동안 반응가스인 산소가 제1 도우프드 폴리실리콘막(21)으로 확산하는 것을 방지할 수 있다.On the other hand, in order for the amorphous second tantalum oxide film 24 to be deposited thicker than the amorphous first tantalum oxide film 23a, oxygen may diffuse as a long deposition time is required, but the nitrogen source in the amorphous first tantalum oxide film 23a Because of the self-solubilization and furthermore, the nitrogen-enriched silicon nitride film 22a, the reaction gas, which is a reactive gas, diffuses into the first doped polysilicon film 21 during a long deposition process of the amorphous second tantalum oxide film 24. You can prevent it.
도 3e에 도시된 바와 같이, 비정질 제2 탄탈륨산화막(24)의 결정화를 위한 열처리 공정을 수행한다. 이때, 열처리 공정은 고온(800℃∼850℃)에서 산소 분위기로 30분동안 로열처리(furnace anneal)한다.As shown in FIG. 3E, a heat treatment process for crystallizing the amorphous second tantalum oxide film 24 is performed. At this time, the heat treatment process is a furnace (furnace anneal) for 30 minutes in an oxygen atmosphere at a high temperature (800 ℃ ~ 850 ℃).
상술한 열처리 공정후, 비정질 제2 탄탈륨산화막(24)은 물론 비정질 제1 탄탈륨산화막(23a)이 결정질로 상변이되고, 비정질 제1 탄탈륨산화막(23a)내에 고용된 질소 원자와 질소부화실리콘나이트라이드막(22a)내 질소원자가 비정질 제1 탄탈륨산화막(23a)과 질소부화 실리콘나이트라이드막(22a)의 계면에 집적되어 질소집적층(26)이 형성된다.After the above heat treatment process, the amorphous second tantalum oxide film 24 as well as the amorphous first tantalum oxide film 23a are phase-transformed into crystalline, and the nitrogen atom and nitrogen-enriched silicon nitride dissolved in the amorphous first tantalum oxide film 23a Nitrogen atoms in the film 22a are integrated at the interface between the amorphous first tantalum oxide film 23a and the nitrogen-enriched silicon nitride film 22a to form the nitrogen accumulation layer 26.
이하, 결정화된 비정질 제2 탄탈륨산화막(24)과 비정질 제1 탄탈륨산화막(23a)을 결정질 탄탈륨산화막(25)이라 약칭하며, 결정질 탄탈륨산화막(25)은 비정질 제1 탄탈륨산화막(23a)과 비정질 제2 탄탈륨산화막(24)을 합한 두께, 즉 60Å∼100Å 두께가 된다.Hereinafter, the crystallized amorphous second tantalum oxide film 24 and the amorphous first tantalum oxide film 23a are abbreviated as a crystalline tantalum oxide film 25, and the crystalline tantalum oxide film 25 is an amorphous first tantalum oxide film 23a and an amorphous agent. The total thickness of the tantalum oxide film 24 is obtained, that is, the thickness is 60 kPa to 100 kPa.
결국, 열처리 공정시 비정질 제1 탄탈륨산화막(23a)내에 고용된 질소 원자와 질소부화실리콘나이트라이드막(22a)내 질소원자가 결정질 탄탈륨산화막(25)과 질소부화 실리콘나이트라이드막(22a)의 계면에 집적되어 질소집적층(26)이 형성됨에 따라 산소확산을 방지한다.As a result, the nitrogen atom dissolved in the amorphous first tantalum oxide film 23a and the nitrogen atom in the nitrogen-enriched silicon nitride film 22a during the heat treatment process are located at the interface between the crystalline tantalum oxide film 25 and the nitrogen-enriched silicon nitride film 22a. As the nitrogen accumulation layer 26 is integrated to prevent oxygen diffusion.
도 3f에 도시된 바와 같이, 결정질 탄탈륨산화막(25)상에 확산방지막인 티타늄나이트라이드막(27)을 형성한 후, 티타늄나이트라이드막(26)상에 상부전극인 제2 도우프드 폴리실리콘막(28)을 형성한다.As shown in FIG. 3F, after the titanium nitride film 27 as a diffusion barrier film is formed on the crystalline tantalum oxide film 25, the second doped polysilicon film as the upper electrode on the titanium nitride film 26 is formed. Form 28.
이때, 티타늄나이트라이드막(27)은 결정질 유전막(25)과 후속 제2 도우프드 폴리실리콘막(28)간 상호확산을 방지하기 막으로서, 소스물질로 TiCl4를 이용하고 반응가스로 암모니아를 이용하는 화학기상증착법(CVD)을 통해 600℃∼800℃온도에서 200Å∼300Å의 두께로 증착된다.At this time, the titanium nitride film 27 is a film for preventing the mutual diffusion between the crystalline dielectric film 25 and the second doped polysilicon film 28, using TiCl 4 as a source material and ammonia as a reaction gas. It is deposited by a chemical vapor deposition (CVD) to a thickness of 200 kPa to 300 kPa at a temperature of 600 ℃ to 800 ℃.
그리고, 제2 도우프드 폴리실리콘막(28)은 PH3가스를 이용한 인시튜도핑법으로 형성하되, 인(P)의 농도는 3.0 ×1020atoms/cc로 유지한다. 한편, 제2 도우프드 폴리실리콘막(27)은 1000Å의 두께로 증착된다.The second doped polysilicon film 28 is formed by an in-situ doping method using PH 3 gas, but the phosphorus (P) concentration is maintained at 3.0 x 10 20 atoms / cc. On the other hand, the second doped polysilicon film 27 is deposited to a thickness of 1000 kPa.
상술한 실시예에서 설명한 바와 같이, 열처리공정을 통해 결정화된 탄탈륨산화막(25)을 형성할 때, 제1 탄탈륨산화막(23a)내에 고용된 질소 원자와 질소부화실리콘나이트라이드막(22a)내 질소원자가 제1 탄탈륨산화막(23a)과 질소부화 실리콘나이트라이드막(22a)의 계면에 집적됨에 따라 실리콘나이트라이드막의 두께를 증가시키지 않으면서도 산소확산에 대한 저항력을 증대시킬 수 있다.As described in the above embodiment, when the tantalum oxide film 25 crystallized through the heat treatment process, the nitrogen atom dissolved in the first tantalum oxide film 23a and the nitrogen atom in the nitrogen-enriched silicon nitride film 22a are formed. By being integrated at the interface between the first tantalum oxide film 23a and the nitrogen-enriched silicon nitride film 22a, the resistance to oxygen diffusion can be increased without increasing the thickness of the silicon nitride film.
그리고, 질소집적층(26)이 질소부화실리콘나이트라이드막(22a)과 탄탈륨산화막(25)간 계면반응을 억제함에 따라 탄타륨산화막(25) 두께의 조절이 가능해져 탄탈륨산화막(25)의 파괴전압(breakdown voltage)을 증가시키며, 그리고, 하부전극의 면적을 증가시키지 않으면서도 캐패시턴스값을 증가시키므로 이웃한 캐패시터간 공간 마진(space margin)을 확보한다.As the nitrogen accumulation layer 26 suppresses the interfacial reaction between the nitrogen-enriched silicon nitride film 22a and the tantalum oxide film 25, the thickness of the tantalum oxide film 25 can be controlled to destroy the tantalum oxide film 25. By increasing the breakdown voltage and increasing the capacitance value without increasing the area of the lower electrode, a space margin between neighboring capacitors is secured.
한편, 상술한 실시예에서는 하부전극과 유전막간 계면에 산소확산방지막으로서 질소부화 실리콘나이트라이드막을 삽입하여, 질소원자의 산소확산저항력이 우수한 특성을 이용하고 있으나, 산소확산방지막으로는 실리콘나이트라이드막외에도 질소가 함유된 전도성 박막을 이용할 수 있다. 예컨대, WN, TiSiN, TaSiN, TiAlN, TaAlN, TaN, TiN, TiZrN 및 TiHfN로 이루어진 그룹중에서 선택된 하나를 이용한다.On the other hand, in the above-described embodiment, the nitrogen-enriched silicon nitride film is inserted as an oxygen diffusion preventing film at the interface between the lower electrode and the dielectric film, so that the oxygen diffusion resistance of the nitrogen atom is excellent, but the silicon nitride film is used as the oxygen diffusion preventing film. In addition, a conductive thin film containing nitrogen may be used. For example, one selected from the group consisting of WN, TiSiN, TaSiN, TiAlN, TaAlN, TaN, TiN, TiZrN and TiHfN is used.
그리고, 하부전극 및 상부전극으로는 도우프드 폴리실리콘막외에도 내열금속인 노블계 금속막(Ru, Pt, Ir, Rh 등)을 이용할 수 있고, 유전막은 고유전상수를 갖는 Al2O3, TaON, TiO2, SrTiO3, (Ba,Sr)TiO을 이용할 수 있다.In addition to the doped polysilicon film, a noble metal film (Ru, Pt, Ir, Rh, etc.), which is a heat-resistant metal, may be used as the lower electrode and the upper electrode, and the dielectric film may be Al 2 O 3 , TaON, TiO 2 , SrTiO 3 , (Ba, Sr) TiO can be used.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 유전막 하부에 질소원자의 함유량이 증가된 실리콘나이트라이드막을 형성하므로써 유전막의 증착 및 고온 열처리공정에서 산소가 확산하는 것을 방지할 수 있는 효과가 있다.As described above, the present invention has an effect of preventing the diffusion of oxygen in the deposition of the dielectric film and the high temperature heat treatment process by forming a silicon nitride film having an increased nitrogen atom content under the dielectric film.
또한, 유전막과 산소확산방지막의 계면에 질소원자를 집적시키므로써 계면반응을 억제하여 누설전류를 감소시킬 수 있는 효과가 있다.In addition, by integrating nitrogen atoms at the interface between the dielectric film and the oxygen diffusion prevention film, there is an effect of reducing the leakage current by inhibiting the interfacial reaction.
그리고, 계면반응을 억제함에 따라 유전막의 두께의 조절이 가능해져 유전막의 파괴전압을 증가시킬 수 있는 효과가 있다.In addition, by suppressing the interfacial reaction, the thickness of the dielectric film can be controlled, thereby increasing the breakdown voltage of the dielectric film.
그리고, 하부전극의 면적을 증가시키지 않으면서도 캐패시턴스값을 증가시킬 수 있으므로 캐패시터간 공간 마진을 확보할 수 있는 효과가 있다.In addition, since the capacitance value can be increased without increasing the area of the lower electrode, the space margin between the capacitors can be secured.
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