KR20040001786A - Method for fabrication of semiconductor device - Google Patents

Method for fabrication of semiconductor device Download PDF

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Publication number
KR20040001786A
KR20040001786A KR1020020037108A KR20020037108A KR20040001786A KR 20040001786 A KR20040001786 A KR 20040001786A KR 1020020037108 A KR1020020037108 A KR 1020020037108A KR 20020037108 A KR20020037108 A KR 20020037108A KR 20040001786 A KR20040001786 A KR 20040001786A
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South Korea
Prior art keywords
etching
forming
photoresist pattern
hard mask
dti
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KR1020020037108A
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Korean (ko)
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차재한
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주식회사 하이닉스반도체
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Priority to KR1020020037108A priority Critical patent/KR20040001786A/en
Publication of KR20040001786A publication Critical patent/KR20040001786A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of forming isolation layers having different depths. CONSTITUTION: A pad oxide layer(21) and a nitride layer(22) are sequentially deposited at the upper portion of a semiconductor substrate(20). After forming the first photoresist pattern at the upper portion of the resultant structure, the first hard mask for a DTI(Deep Trench Isolation) is formed by selectively patterning the nitride layer and the pad oxide layer using the first photoresist pattern. After removing the first photoresist pattern, the second photoresist pattern is formed at the upper portion of the resultant structure. Then, the second hard mask for an STI(Shallow Trench Isolation) is formed at the resultant structure by selectively patterning the nitride layer using the second photoresist pattern as an etching mask. Then, dry etching processes are sequentially carried out at the resultant structure.

Description

반도체 소자의 제조 방법{METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE}Method for manufacturing a semiconductor device {METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 제조 방법 중 바리폴라 정션 트렌지스터의 소자분리막 형성을 위한 건식 식각 방법에 관한 것으로 DTI 공정 및 STI 공정을 진행하기위한 마스크 패터닝 및 기판 식각 공정 줄일수 있는 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a dry etching method for forming an isolation layer of a varipolar junction transistor in a method of manufacturing a semiconductor device, and to a method of manufacturing a semiconductor device capable of reducing mask patterning and substrate etching processes for a DTI process and an STI process. will be.

고성능 바이폴라 정션 트랜지스터(BJT)를 일반적인 CMOS 로직 회로 집적 공정과 기판상에 형성시키기는 BiCMOS 공정을 진행할 경우, BJT의 래치 업(Latch-up) 특성 개선 및 기판 기생 캐패시턴스 특성을 개선하기 위한 Deep Trench Isolation(DTI) 공정과 CMOS 트랜지스터의 소자 분리막을 위한 Shaiiow Trench Isolation(STI) 공정이 필요하다.Deep Trench Isolation to Improve LJ Latch-up and Substrate Parasitic Capacitance When Using BiCMOS Process to Form High Performance Bipolar Junction Transistor (DTI) process and Shaiiow Trench Isolation (STI) process for device isolation of CMOS transistors are required.

도1a 내지 도1d는 종래 기술에 의한 반도체 소자의 제조 방법을 나타낸 단면도들이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도1a를 참조하면, 반도체 기판(10) 상에 패드 산화막(11)및 하드 마스크로 질화막(12)을 증착한 후 질화막(12) 상부에 제 1 포토레지스트 패턴(13)을 형성하여 이를 이용하여 질화막(12)을 식각한다.Referring to FIG. 1A, after the nitride film 12 is deposited on the semiconductor substrate 10 using the pad oxide film 11 and the hard mask, a first photoresist pattern 13 is formed on the nitride film 12 to use the same. The nitride film 12 is etched.

도1b를 참조하면, DTI를 형성하기 위하여 질화막(12)을 하드마스크로 이용하여 반도체 기판(10)에 Deep Trench 식각을 진행한다.Referring to FIG. 1B, deep trench etching is performed on the semiconductor substrate 10 using the nitride film 12 as a hard mask to form a DTI.

도1c를 참조하면, STI를 형성하기 위해 제 2 포토레지스트 패턴(14)형성한 후 도1d에 도시된 바와 같이 Shallow Trench 식각을 진행한다.Referring to FIG. 1C, after forming the second photoresist pattern 14 to form an STI, a shallow trench etching process is performed as shown in FIG. 1D.

이때, Shallow Trench 식각과 Deep Trench 식각을 두차례 진행하면서 2번째 포토레지스트는 제거하지 않고 남겨두어야 하기 때문에 반도체 기판 식각 공정시 폴리머 생성을 억제할 수 없게된다.In this case, the second photoresist must be left without being removed while the Shallow Trench etching and the Deep Trench etching are performed twice, so that the formation of the polymer during the semiconductor substrate etching process cannot be suppressed.

이러한 방법은 DTI 형성을 위한 포토레지스트 패터닝&하드 마스크 식각공정&포토레지스트 제거 &반도체 기판 식각의 4차 공정과 STI를 형성하기 위한 포토레지스트 패터닝&하드 마스크 식각 공정& 반도체 기판 식각& 포토레지스트 제거 공정을 연속해서 진행해야 하기 때문에 소자 분리막 형성 공정이 길어지고, STI 건식 식각시 남겨진 포토레지스트에 의해 발생하는 폴리머의 제거 등 추가적인 세정 공정이 필요한 문제점이 있었다.These methods include photoresist patterning, hard mask etching, photoresist removal, semiconductor substrate etching, and photoresist patterning, hard mask etching, semiconductor substrate etching, and photoresist removal processes to form STIs. Since the process proceeds continuously, the device isolation film forming process is lengthened, and there is a problem in that an additional cleaning process is required, such as the removal of polymer generated by the photoresist left during STI dry etching.

상기와 같은 문제점을 해결하기 위한 본 발명은 DTI용 하드 마스크와 STI용 하드마스크를 연속적으로 형성한 후 서로 다르게 형성된 하드 마스크를 이용하여 동일 장비 내에서 플라즈마 소스를 다르게 적용하여 연속적인 건식 식각을 진행함으로써 서로 다른 깊이의 바이폴라 정션 소자의 소자 분리막 형성하고자 하는 것이다.In order to solve the above problems, the present invention continuously forms a hard mask for DTI and a hard mask for STI, and then continuously applies dry plasma etching by differently applying plasma sources in the same equipment by using different hard masks. As a result, device isolation layers of bipolar junction devices having different depths are formed.

도1a 내지 도1d는 종래 기술에 의한 반도체 소자의 제조 방법을 나타낸 단면도들이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도2a 내지 도2c는 본 발명에 의한 반도체 소자의 제조 방법을 나타낸 단면도 들이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-

20 : 실리콘 기판 21 : 패드 산화막20 silicon substrate 21 pad oxide film

22 : 질화막 23 : 제 1 포토레지스트 패턴22 nitride film 23 first photoresist pattern

24 : 제 2 포토레지스트 패턴24: second photoresist pattern

상기와 같은 목적을 실현하기 위한 본 발명은 반도체 기판 상에 하드 마스크로 사용될 패드 산화막 및 질화막을 증착하는 단계와, 상기 질화막 상부에 제 1 포토레지스트 패턴을 이용하여 질화막 및 패드 산화막을 패터닝하여 DTI용 하드 마스크를 형성하는 단계와, 상기 제 1 포토레지스트를 제거한 후 제 2 포토레지스트 패턴을 형성하고 제2 포토fp지스트 패턴을 이용하여 STI용 하드마스크를 형성하는 단계와, 동일 장비내에서 식각용 플라즈마 소스를 바꾸어주는 방식으로 연속 건식 식각을 통해 DTI 형성을 위한 식각과 패드 산화막 식각 및 STI를 형성하기 위한 식각 공정을 진행하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법에 관한 것이다.The present invention for achieving the above object is a step for depositing a pad oxide film and a nitride film to be used as a hard mask on a semiconductor substrate, and patterning the nitride film and the pad oxide film using a first photoresist pattern on the nitride film for DTI Forming a hard mask, forming a second photoresist pattern after removing the first photoresist, and forming a hard mask for STI using a second photofp resist pattern; and etching plasma in the same equipment The present invention relates to a method for manufacturing a semiconductor device, the method comprising: performing etching through a continuous dry etching to form a source, etching the pad oxide film, and forming an STI through a continuous dry etching.

이때, 상기 DTI 형성을 위한 식각 공정은 고선택적으로 식각될 수 있는 플라즈마 소스를 이용하여 이방성 식각으로 진행하고, STI를 형성하기 위한 식각 공정은 DTI 형성을 위한 플라즈마 소스와 동일 소스로 이방성 건식 식각으로 진행하는 것을 특징으로 한다.At this time, the etching process for forming the DTI proceeds to anisotropic etching using a plasma source that can be highly selectively etched, and the etching process for forming the STI is anisotropic dry etching with the same source as the plasma source for forming the DTI. It is characterized by proceeding.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

도2a 내지 도2c는 본 발명에 의한 반도체 소자의 제조 방법을 나타낸 단면도 들이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

도2a를 참조하면, 반도체 기판(20) 상에 하드 마스크로 사용될 패드 산화막(21) 및 질화막(22)을 증착 한 후 제 1 포토레지스트 패턴(23)을 이용하여 질화막(22) 및 패드 산화막(21)을 패터닝하여 DTI용 하드 마스크를 형성한다.Referring to FIG. 2A, after depositing a pad oxide film 21 and a nitride film 22 to be used as a hard mask on a semiconductor substrate 20, the nitride film 22 and the pad oxide film (using the first photoresist pattern 23) may be deposited. 21) to form a hard mask for DTI.

도2b를 참조하면, 제 1 포토레지스트(23)을 제거한 후 제 2 포토레지스트 패턴(24)을 이용하여 STI용 하드마스크를 형성한다.Referring to FIG. 2B, after removing the first photoresist 23, a hard mask for STI is formed using the second photoresist pattern 24.

이때, STI용 하드마스크는 패드산화막(21)은 남겨둔채 절연막(22)만을 제거하여 형성한다.At this time, the hard mask for STI is formed by removing only the insulating film 22 with the pad oxide film 21 remaining.

도2c를 참조하면, 동일 장비내에서 식각용 플라즈마 소스를 바꾸어주는 방식으로 연속 건식 식각을 진행하는데 먼저, (가)에서와 같이 DTI 형성을 위한 Deep Trench 식각을 고선택적으로 식각될 수 있는 플라즈마 소스를 이용하여 이방성 식각으로 진행하고, (나)에 도시된 바와 같이 플라즈마 소스를 이용한 이방성 건식 식각으로 패드 산화막(21)을 식각한다. 또한, (다)에 도시된 바와 같이 DTI 형성을 위한 플라즈마 소스와 동일 소스로 이방성 건식 식각으로 STI를 형성하기 위한 Shallow Trench 식각을 진행한다.Referring to FIG. 2C, the continuous dry etching is performed in a manner of changing the etching plasma source in the same equipment. Proceed to anisotropic etching using, and as shown in (b), the pad oxide film 21 is etched by anisotropic dry etching using a plasma source. In addition, as shown in (c), Shallow Trench etching is performed to form STI by anisotropic dry etching with the same source as the plasma source for DTI formation.

상기한 바와 같이 본 발명은 바이폴라 CMOS 소자의 DTI, STI 소자 분리 절연막을 형성하기 위한 반도체 기판의 건식 식각을 동이세 진행할 수 있으므로 공정 단계를 단축할 수 있을 뿐만 아니라 반도체 기판에 서로 다른 깊이로 식각이 가능하기 때문에 생산 시간을 단축시킬 수 있는 이점이 있다.As described above, the present invention can perform dry etching of a semiconductor substrate for forming DTI and STI isolation layers of bipolar CMOS devices at the same time, thereby shortening the process step and etching the semiconductor substrates at different depths. It is possible to reduce the production time because it is possible.

또한, STI 건식 식각 과정에서 포토레지스트가 남지 않기 때문에 식각 공정중에 발생할 수 잇는 기판 오염도 줄일 수 있어 반도체 소자의 신뢰성을 향상시킬 수 있는 이점이 있다.In addition, since no photoresist remains in the STI dry etching process, substrate contamination that may occur during the etching process may be reduced, thereby improving reliability of the semiconductor device.

Claims (2)

반도체 기판 상에 하드 마스크로 사용될 패드 산화막 및 질화막을 증착하는 단계와,Depositing a pad oxide film and a nitride film to be used as a hard mask on the semiconductor substrate; 상기 질화막 상부에 제 1 포토레지스트 패턴을 이용하여 질화막 및 패드 산화막을 패터닝하여 DTI용 하드 마스크를 형성하는 단계와,Patterning a nitride film and a pad oxide film on the nitride film by using a first photoresist pattern to form a hard mask for DTI; 상기 제 1 포토레지스트를 제거한 후 제 2 포토레지스트 패턴을 형성하고 제2 포토레지스트 패턴을 이용하여 STI용 하드마스크를 형성하는 단계와,Removing the first photoresist to form a second photoresist pattern and forming a hard mask for STI using the second photoresist pattern; 동일 장비내에서 식각용 플라즈마 소스를 바꾸어주는 방식으로 연속 건식 식각을 통해 DTI 형성을 위한 식각과 패드 산화막 식각 및 STI를 형성하기 위한 식각 공정을 진행하는 단계를In the same equipment, the etching process for forming the DTI, the etching of the pad oxide layer, and the forming of the STI through the continuous dry etching is performed by changing the plasma source for etching. 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.A method of manufacturing a semiconductor device, comprising. 제 1항에 있어서, 상기 DTI 형성을 위한 식각 공정은 고선택적으로 식각될 수 있는 플라즈마 소스를 이용하여 이방성 식각으로 진행하고, STI를 형성하기 위한 식각 공정은 DTI 형성을 위한 플라즈마 소스와 동일 소스로 이방성 건식 식각으로 진행하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the etching process for forming the DTI is performed by anisotropic etching using a plasma source that can be highly selectively etched, and the etching process for forming the STI is performed using the same source as the plasma source for forming the DTI. A method of manufacturing a semiconductor device, characterized in that it proceeds by anisotropic dry etching.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100824198B1 (en) * 2006-12-04 2008-04-21 주식회사 하이닉스반도체 Method of manufacturing a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100824198B1 (en) * 2006-12-04 2008-04-21 주식회사 하이닉스반도체 Method of manufacturing a semiconductor device

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