KR20040000576A - Filter circuit - Google Patents

Abstract

PURPOSE: A filter circuit is provided to be capable of reducing slice usage at the inner portion of FPGA(Field Programmable Gate Arrays). CONSTITUTION: A filter circuit is provided with the first storage parts(100,110) for storing input data, the first counter(120) for outputting the first clock to the first storage parts at the first speed, the second storage parts(130,140) for storing filter coefficients, an operation part for outputting the result of operation at the first speed after operating the input data and the filter coefficients, and the second counters(150,160) for outputting the second clock at the second speed to the first storage parts, the second storage parts, and the operation part. Preferably, the operation part includes multipliers(170,180) for multiplying the input data by filter coefficients, a plurality of adders(190,200,230) for adding the multiplied values supplied from the multipliers, and a plurality of buffers(210,220) for storing the added values supplied from the adders.

Description

Filter Circuits {FILTER CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a filter circuit, and more particularly, to a filter circuit capable of efficiently improving the use capacity of an FPGA when designing a filter in an FPGA that filters a digital signal in a mobile communication transmission system.

FPGA (FIELD PROGRAMMABLE GATE ARRAYS) is a chip that is widely used in related fields because of low development cost and low risk compared to ASIC, and is developing communication equipment using this in mobile communication field.

FPGAs in the mobile communication field contain various components. One of them is a filter that performs a filtering operation on a digital signal.

A filter in a real-time system in the mobile communication field is a causal filter that performs filtering using only past and present input signals.

1 shows a conventional basic digital filter circuit.

As shown in FIG. 1, the basic filter circuit includes a plurality of delay shifters 1 _{1 to} 1 _N-1 , a plurality of multipliers 2 ₀ to 2 _N-1 , and a plurality of adders ( adder) (3 ₁ to 3 _N-1 ).

Delay shifters 1 _{1 to} 1 _N-1 delay shift the incoming input signals x (k), k = 0, 1, 2,...

The multipliers 2 ₀ to 2 _N-1 each have a filter coefficient (a (n), n = 0, 1, 2, ..., N-1) and an input signal x (k )) And the output value (delay signal) from each delay shifter (1 _{1 to} 1 _N-1 ).

Adders 3 ₁ to 3 _N-1 calculate the final output signal y (k) by adding up respective multiplication values.

The operation of the filter circuit in real time is as follows.

First, at the predetermined time the input signal (x (k)) are input to the first delay shifter ₍₁₁₎ of the filter circuit. When the first input signal is called x (0), the next x (1), x (2), x (3),... Signal is continuously input to the first delay shifter 1 ₁ , and then sequentially moved to each of the following delay shifters 1 _{2 to} 1 _N-1 .

As the signal is continuously input to the filter as described above, if the number of input signals becomes equal to or greater than the number of filter coefficients (N), the filter can then perform a filtering operation to output the filtered signal.

The filter coefficient has a value and a number determined for each filter. As the number of filter coefficients increases, the performance of the filter improves.

The filtering operation performed in the filter circuit is represented by the following equation (1).

For example, suppose you design a filter with a number of filter coefficients of six. You need five delay shifters, six multipliers, and five adders.

In order to start output from this filter, at least the number of input signals must be 6 or more, so if the filter output starts from k = 10, that is, from the input value x (10), Equation (1) , k = 10, 11, 12,... Becomes

Therefore, the first value output from the filter is

y (10) = a (0) x (10) + a (1) x (9) + a (2) x (8) + a (3) x (7) + a (4) x (6) + a (5) x (5),

The following values are sequentially output.

y (11) = a (0) x (11) + a (1) x (10) + a (2) x (9) + a (3) x (8) + a (4) x (7) + a (5) x (6)

y (12) = a (0) x (12) + a (1) x (11) + a (2) x (10) + a (3) x (9) + a (4) x (8) + a (5) x (7)

‥‥‥

Thus, the filter output value is composed of the sum of the input values (current and past input values) and the convolution of the filter coefficients.

However, in the conventional filter circuit, since the number of filter coefficients is the same as the number of multipliers, when using many filter coefficients to improve the performance of the filter, the number of multipliers is required. There is a problem that the number is increased.

For example, Xlinx's FPGA (VERTEXII-XC2V1000) has 5120 total slices (capacity units of FPGAs), with about 150 slices per multiplier.

This figure takes about 3% of slices per multiplier. If the number of filter coefficients is 10, designing a filter with an FPGA will take up a very large 30% of the filter inside the FPGA. The internal usage of the FPGA is reduced, and there is a problem in that the part price increases because an FPGA having a large slice capacity is required to design a filter having a large filter coefficient.

Accordingly, an object of the present invention is to provide a filter circuit which can reduce the slice usage capacity in an FPGA, which is devised to solve the above problems.

1 is a block diagram showing a conventional basic filter circuit.

2 is a block diagram showing a filter circuit according to a first embodiment of the present invention.

3 is an exemplary diagram showing a mapping relationship between an input signal and a filter coefficient in the filter circuit according to the first embodiment of the present invention.

4 is a block diagram showing a filter circuit according to a second embodiment of the present invention.

5 is an exemplary diagram showing a mapping relationship between an input signal and a filter coefficient in the filter circuit according to the second embodiment of the present invention.

** Explanation of Signs of Major Parts of Drawings **

100, 110: RAM 120, 150, 160: Counter

130, 140: Rom 170, 180: Multiplier

190, 200, 230: Adder 210, 220: Buffer

To this end, the filter circuit according to the first embodiment of the present invention includes: first storage means for storing input data; A first counter for outputting a clock to the first storage means at a first speed; Second storage means for storing a filter coefficient; Calculating means for calculating the input data and the filter coefficient and outputting the same at a first speed; And a second counter for outputting a clock at a second speed to the first storage means, the second storage means, and the calculation means.

As a result, whenever the input data is stored in the first storage means at the first speed, the input data and the filter coefficient are output at the second speed from the first storage means and the second storage means, and the calculation means In step 1, the input data and the filter coefficients are multiplied in a one-to-one correspondence at each second speed, and their respective multiplication values are added together to output a final filtering value at the first speed.

A filter circuit according to a second embodiment of the present invention comprises: a plurality of first storage means for storing input data; A first counter for outputting a clock at a first speed to the plurality of first storage means; A plurality of second storage means for storing filter coefficients; A plurality of calculation means for calculating the input data and the filter coefficient and outputting the same at a first speed; Adding means for adding operation results of the plurality of calculation means; And a plurality of second counters outputting a clock at a second speed to the first storage means, the second storage means and the calculation means.

As a result, whenever the input data is stored in the plurality of first storage means at a first speed, the input data and the filter coefficient at the second speed in the plurality of first storage means and the plurality of second storage means. And a plurality of calculation means to multiply the input data and the filter coefficients at a second speed in a one-to-one correspondence, add their respective multiplication values, and output a total of the multiplication values at a first speed, and add the sum means. Adds all the sums of respective multiplication values output from the plurality of calculation means and outputs the final filtering value at the first speed.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 shows a filter circuit according to a first embodiment of the present invention.

Unlike in FIG. 1, the filter in FIG. 2 uses only one multiplier 50 and one adder 60, each of which includes a RAM 10, a ROM 20, two counters 30 and 40, and a buffer 70. It contains.

Here, the RAM 10 stores data at a rate of x2 and outputs data at a rate of x64. The ROM 20 stores the filter coefficients and outputs the filter coefficients at a rate of x64.

Counter_64 (40) repeats the count from 0 to 63 at a speed of x2 and designates a register of RAM 10 in which input data is stored. Counter_24 (30) repeats the count from 0 to 31 at a rate of x64, and outputs input data and filter coefficients of RAM 10 and ROM 20.

The multiplier 50 multiplies the input data and the filter coefficients output from the RAM 10 and the ROM 20, and the adder 60 transfers the multiplier value Mul_out from the multiplier 50 and the feedback fed back from the buffer 70. The addition value Add_temp is added to output the addition value Add.

The buffer 70 stores the add value Add output from the adder 60 and feeds it back to the adder 60 as a previous add value Add_temp.

In Fig. 1, since the input speed, the calculation speed, and the output speed of the signal are all the same, a multiplier is required as many as the filter coefficient. However, the filter of Fig. 2 performs the filtering with only one multiplier and an adder because the filter is operated at the system clock speed. can do.

Looking at the operation of the filter shown in Figure 2 as follows.

First, when counter_64 (40) sends clock to RAM 10 at the speed of x2, the RAM indicates that counter_64 (40) starts at the initial input signal x (0) and input signals are at the speed of x2. It is stored in each register of (10).

If data is continuously stacked in each register at a rate of x2 and the counter_64 (40) counts it and counts 31 (i.e. 32 data is input), the RAM 10 and ROM 20 Count_32 (30) is driven to output the stored value.

The ROM 20 stores filter coefficients, and the number of filter coefficients that can be used corresponds to the difference between the input speed of the signal and the system speed.

That is, since the input speed is 2 and the system clock speed is 64, the speed difference is 32 times, and thus the number of usable filter coefficients is 32. However, the coefficients of the filter actually used are 31 instead of 32, which will be described later.

Next, when count_32 (30) is driven, count_32 (30) starts to clock the RAM 10 and ROM 20 at a rate of x64.

The RAM 10 and the ROM 20 output the input signal and the filter coefficient at the speed of x64 by the clock of the count_32 (30), and send them to the multiplier 50.

The multiplier 50 multiplies the incoming input signal and the filter coefficient in order and sends the multiplier Mul_out to the adder 60 at a rate of x64.

In the adder 60, the multiplication value Mul_out from the multiplier 50 and the previous addition value Add_temp stored in the buffer 70 are added, and the add value Add is added to the buffer 70 at a rate of x64. Save it.

On the other hand, the counter_32 (30) also sends a clock to the adder 60 at a rate of x64. When the counter_32 (30) counts 31, the counter_32 (30) outputs the value stored in the current buffer 70 as the final filtering value. Reset the buffer 70 to zero.

In other words, after the count reaches 31, the count returns to zero to perform a new filtering operation. Therefore, at the count 31, the final filtering value is output and the buffer is initialized to zero.

By the initialization of the buffer 70, the previous addition value Add_temp becomes 0, and this previous addition value enters the adder 60, is added with the 32nd multiplication value Mul_out, and the addition value Add is added to the buffer 70. ), So the 32th multiplication value should be 0. For this purpose, since the 32 th filter coefficient stored in the ROM 20 should be 0, the number of filter coefficients actually used is 31.

FIG. 3 shows a mapping relationship between input signals and filter coefficients stored in the RAM 10 and the ROM 20 shown in FIG. 2.

3 (a) shows an input value (x (0) to x (31)) stored in the RAM 10 when the input value is to be filled in the register 32 or when 31 is counted in the counter_64 (40). And filter coefficients (a (0) to a (30)) and 0 stored in the ROM 20 are sequentially mapped as shown in order to perform multiplication.

3 (b) shows the input values (x (1) to x (32)) and the filter coefficient (a () when the input value is to be filled in register 33 or when the counter_64 (40) counts 32. 0) to a (30)) and 0 are sequentially mapped as shown to perform multiplication.

Meanwhile, as shown in FIG. 3, since the 32 multiplication results are added and outputted, if the bundle pushed forward or backward is calculated and outputted, the wrong filter operation may be performed.

In conclusion, each time the input signal comes in, multiplication and subtraction are performed 32 times faster than the input speed to output the filtering value at the same speed as the input speed. Therefore, filtering operation can be performed using only one multiplier and an adder. Will be.

However, in the filter circuit according to the first embodiment of the present invention, unlike the conventional filter circuit of FIG. 1, only one multiplier is used, but the number of filter coefficients may be limited according to the difference between the input speed and the system speed. .

That is, in FIG. 2, if the system speed is × 64 and the input speed is × 2, there is a 32 times speed difference. Therefore, 32 filter coefficients that can be used (the actual filter coefficients are 31 because 0 is included for initialization) are used. Limited.

For example, the input speed and system speed used in FIG. 2 are used in a CDMA system. In IMT-2000, data input speed is × 1 (3.84MHz) and system speed is × 24 (92.16MHz). Since the number of filter coefficients is 40 or more, this cannot be realized by the filter circuit according to the first embodiment of the present invention.

4 shows a filter circuit according to a second embodiment of the present invention.

As shown in FIG. 4, the filter circuit according to the second embodiment of the present invention includes two RAMs 100 and 110, two ROMs 130 and 140, three counters 120, 150 and 160, and two. It includes three multipliers (170, 180), three adders (190, 200, 230) and two buffers (210, 220).

The first RAM 100 sequentially stores the input data at a speed of × 1 and outputs the input data at a system clock speed (× 24). The second RAM 110 operates in the same manner as the first RAM.

The counter _64 120 counts the number of data stored in the first RAM 100 and the second RAM 110 at a speed of x1, and the first RAM 100 and the second RAM 100 in which input data is stored. Register 110).

The first ROM 130 stores coefficients of the upper half among the number of filter coefficients, and the second ROM 140 stores coefficients of the lower half among the number of filter coefficients.

The first counter_24 (150) counts from 0 to 23 at the system clock speed, and designates a register in which input data and filter coefficients output from the first RAM 100 and the first ROM 130 are located. The second counter_24 (160) counts from 0 to 23 at the system clock speed, and similarly designates a register in which the input data and filter coefficients output from the second RAM 110 and the second ROM 140 are located. .

The first multiplier 170 multiplies the input data and the filter coefficients output from the first RAM 100 and the first ROM 130, and the second multiplier 180 uses the second RAM 110 and the second ROM ( The filter coefficients are multiplied by the input data outputted at 140).

The first adder 190 adds the multiplication value Mul_out1 of the first multiplier 170 and the feedback previous add value Add_temp1 to output the add value Add1, and the first buffer 210 outputs the first adder ( The added value Add output from 190 is stored and fed back to the first adder 190 as a previous add value Add_temp.

The second adder 200 adds the multiplication value Mul_out2 of the second multiplier 180 and the feedback previous add value Add_temp2 to output the add value Add2, and the second buffer 220 outputs the second adder ( The added value Add2 output from 200 is stored and fed back to the second adder 200 as a previous add value Add_temp2.

The third adder 230 adds the values Sum1 and Sum2 output from the first buffer 210 and the second buffer 220 to output the finally filtered value.

Unlike the filter of the first embodiment, the filter circuit of FIG. 4 has a split structure in which filter coefficients are divided and stored in two different ROMs.

In FIG. 4, the speed of the input data and the system clock speed are used in the IMT-2000. The speed of the input data is x1 and the system clock speed is x24.

Under this speed difference (24 times speed difference), when a filter using 40 filter coefficients (up to 46 filter coefficients except 0 for initialization) is designed, the second embodiment of the present invention By applying the partitioning scheme proposed in, it is possible to implement these filters.

First, since the speed difference is 24 times, 20, which is half of the number of filter coefficients, are stored in two ROMs 130 and 140 having 24 tables (registers) accordingly. Twenty-four tables in each ROM are filled with 20 filter coefficients and the remaining four tables are filled with zeros (see Figure 5).

When the counter_64 120 starts to operate, input data is simultaneously filled in the same table (register) of the first RAM 100 and the second RAM 110 at a speed of x1.

The first counter when the input data is continuously input and the input data is filled in the 44th registers of the first RAM 100 and the second RAM 110, that is, the counter_64 120 counts 43. 24_ and second counter_24 (160) operate to start sending clocks of 24 to RAM (100, 110) and ROM (130, 140), respectively.

Input data and filter coefficients are output from the RAMs 100 and 110 and the ROMs 130 and 140 by the two counters 24 and 150, respectively, and supplied to the multipliers 170 and 180.

In this case, a method of accessing and outputting input data stored in the first RAM 100 and the second RAM 110 is different, which will be described with reference to FIG. 5.

5 shows a mapping relationship between outputs of the RAMs 100 and 110 and the ROMs 130 and 140.

FIG. 5A illustrates a mapping relationship between the first RAM 100 and the first ROM 130, and FIG. 5B illustrates a mapping relationship between the second RAM 110 and the second ROM 140. Indicates.

The first multiplier 170 multiplies the input data and the filter coefficient by the mapping relationship as shown in FIG. 5 (a), and sends the multiplier value to the first adder 190.

The first adder 190 adds the multiplication value and the previous addition value and sends the addition value to the first buffer 210. The first buffer 210 stores the addition value and feeds it back to the first adder 190 as a previous addition value so as to be added to the next multiplication value.

Similarly, the second multiplier 180 multiplies the input data and the filter coefficient by the mapping relationship as shown in FIG. 5 (b), and sends the multiplier value to the second adder 200.

The second adder 200 adds the multiplication value and the previous addition value and sends the addition value to the second buffer 220. The second buffer 220 stores the addition value and feeds it back to the second adder 200 as a previous addition value so that the second buffer 220 can be added with the next multiplication value.

In the case of FIG. 5A, multiplication is performed sequentially from the first input data x (0) to the 23rd input data x (23), whereas in the case of FIG. 5B, the multiplication is started. The register position where the input data is stored is different.

That is, as shown in FIG. 5 (b), the position where the input data first accessed in the second RAM 110 is stored is register 20 (21st register).

This is because the input data are stored in the two RAMs 100 and 110 in the same manner, and if the access positions of the input data are the same, they are multiplied and the correct filtering operation cannot be performed.

Accordingly, for this purpose, the second counter_24 (160) can designate the 21st register as the first accessed register differently from the first counter_24 (150).

As such, the position of the input data initially output from the second RAM 110 may vary depending on the number of filter coefficients.

The first multiplier 170 and the second multiplier 180 continuously multiply the input data and the filter coefficient as described above, and send the multiplier value to the first adder 190 and the second adder 200, and the first adder. 190 and the second adder 200 continuously adds the multiplication value and the feedback previous addition value and sends the addition value to the first buffer 200 and the second buffer 210.

In this way, when the multiplication and addition are continued and the counts of the two counters 24 (150 and 160) become 23, the first buffer 210 and the second buffer 220 are stored in the first addition value ( Add1) and the second addition value Add2 are sent to the third adder 230 as the final addition values Sum1 and Sum2, and the first buffer 210 and the second buffer 220 are reset to zero.

The third adder 230 adds input final sum values Sum1 and Sum2 to calculate a final filtered output value.

The next counter_24 (150, 160) starts counting again from 0 and outputs the filtered value continuously by the same process as above.

In mathematical terms,

y (39) = a (0) x (39) + a (1) x (38) + a (2) x (37) +. + a (37) x (2) + a (38) x (1) + a (39) x (0)

y (40) = a (0) x (40) + a (1) x (39) + a (2) x (38) +. + a (37) x (3) + a (38) x (2) + a (39) x (1)

y (41) = a (0) x (41) + a (1) x (40) + a (2) x (39) +. + a (37) x (4) + a (38) x (3) + a (39) x (2)

‥‥‥ to be.

The second embodiment is a structure in which the filter coefficient is divided and stored in two ROMs. The first embodiment is expanded, but the present invention is not limited thereto, and the partition structure can be expanded in three or more ROMs. .

Accordingly, the number of filter coefficients that can be used can be increased.

As described above, according to the first embodiment of the present invention, the multiplier and the adder are outputted at the same speed as the input speed by multiplying and subtracting the input signal once at a speed higher than the input speed. Filtering operation can be performed using only one.

Further, according to the second embodiment of the present invention, as an extension of the first embodiment of the present invention, a partition structure is formed in which input data is simultaneously stored in different RAMs and filter coefficients are distributed and stored in different ROMs. Input data and filter coefficients can be matched 1: 1 by different RAM access methods, so that even in systems where the number of filter coefficients is large and the difference of input data rate and system clock speed is not large as in IMT-2000 The effect is that the filter can be implemented without increasing the FPGA usage.

Claims (8)

First storage means for storing input data; A first counter for outputting a clock to the first storage means at a first speed; Second storage means for storing a filter coefficient; Calculating means for calculating the input data and the filter coefficient and outputting the same at a first speed; And a second counter for outputting a clock at a second speed to the first storage means, the second storage means, and the calculation means. The method of claim 1, The calculating means includes: a multiplier that multiplies the input data by the filter coefficient; An adder for adding a multiplication value output from the multiplier; Including a buffer for storing the addition value output from the adder, And said adder sends a new addition value obtained by adding the addition value stored in said buffer and the multiplication value output from said multiplier, to said buffer. The method of claim 1, And the number of filter coefficients is smaller than the number corresponding to the speed difference between the first speed and the second speed. A plurality of first storage means for storing input data; A first counter for outputting a clock at a first speed to the plurality of first storage means; A plurality of second storage means for storing filter coefficients; A plurality of calculation means for calculating the input data and the filter coefficient and outputting the same at a first speed; Adding means for adding operation results of the plurality of calculation means; And a plurality of second counters for outputting a clock at a second speed to the first storage means, the second storage means and the calculation means. The method of claim 4, wherein And the plurality of second counters differently designate initial access positions of the plurality of first storage means so that the multiplication corresponding to the input data and the filter coefficient by one-to-one correspondence does not overlap. The method of claim 5, The first access position of the N-th first storage means in the plurality of first storage means is equal to the filter coefficient stored in the N-1-th second storage means by the input data stored in the N-first first storage means. : 1, wherein the filter circuit is from the position after the corresponding last position. The method of claim 4, wherein The calculating means includes: a multiplier that multiplies the input data by the filter coefficient; An adder for adding a multiplication value output from the multiplier; Including a buffer for storing the addition value output from the adder, And said adder sends a new addition value obtained by adding the addition value stored in said buffer and the multiplication value output from said multiplier, to said buffer. The method of claim 4, wherein And a number of filter coefficients stored in each of the plurality of second storage means is smaller than a number corresponding to a speed difference between the first speed and the second speed.