KR200357330Y1 - The thin film transistor liquid crystal display - Google Patents

The thin film transistor liquid crystal display Download PDF

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KR200357330Y1
KR200357330Y1 KR20-2004-0012200U KR20040012200U KR200357330Y1 KR 200357330 Y1 KR200357330 Y1 KR 200357330Y1 KR 20040012200 U KR20040012200 U KR 20040012200U KR 200357330 Y1 KR200357330 Y1 KR 200357330Y1
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film
thin film
film transistor
liquid crystal
crystal display
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KR20-2004-0012200U
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Korean (ko)
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민태석
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(주)비전인텍
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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136227Through-hole connection of the pixel electrode to the active element through an insulation layer
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40Arrangements for improving the aperture ratio

Abstract

본 고안은 소비전력을 감소시킨 박막 트랜지스터 액정표시장치에 관한 것으로, 본 고안에 따른 저소비전력의 박막 트랜지스터 액정표시장치는 소스 전극, 드레인 전극 및 게이트 전극이 유리기판상에 구비된 박막 트랜지스터에 P-TEOS막, SOG막 및 P-TEOS 막이 순차적으로 적층된 절연1막이 도포되고, 상기 절연1막 상에 상기 박막 트랜지스터에 대응되어 형성된 차광막 패턴의 결과물 상의 전면에 절연2막이 형성되며, 상기 절연1,2막을 관통하고 상기 드레인 전극을 노출시키는 콘택홀을 통하여 상기 드레인 전극과 연결된 화소 전극이 구비됨을 특징으로 한다.The present invention relates to a thin film transistor liquid crystal display device having reduced power consumption. The low power consumption thin film transistor liquid crystal display device according to the present invention includes a P-TEOS in a thin film transistor having a source electrode, a drain electrode, and a gate electrode provided on a glass substrate. An insulation 1 film is formed by sequentially stacking a film, an SOG film, and a P-TEOS film, and an insulation 2 film is formed on the entire surface of the light shielding film pattern formed corresponding to the thin film transistor on the insulation 1 film, and the insulation 1, 2 And a pixel electrode connected to the drain electrode through a contact hole penetrating a film and exposing the drain electrode.

본 고안에 따른 저소비전력의 박막 트랜지스터 액정표시장치는 TFT기판에 차광막 패턴을 형성함으로써 개구율과 유지용량을 증가시켜 백 라이트의 소비전력이 감소되며, 백 라이트의 소비전력을 증가시키지 아니하고도 화질이 증가되는 효과를 얻는다.In the low power consumption thin film transistor liquid crystal display device according to the present invention, by forming a light shielding film pattern on a TFT substrate, the power consumption of the backlight is reduced by increasing the aperture ratio and the holding capacity, and image quality is increased without increasing the power consumption of the backlight. Get the effect.

Description

저소비전력의 박막 트랜지스터 액정표시장치{The thin film transistor liquid crystal display}The thin film transistor liquid crystal display with low power consumption

본 고안은 TFT-LCD(Thin Film Transistor Liquid Crystal Display)에 관한 것으로, 특히 TFT기판에 차광막을 형성하여 소비전력이 감소되며 화질이 개선되도록 한 저소비전력의 박막 트랜지스터 액정표시장치에 관한 것이다.The present invention relates to a thin film transistor liquid crystal display (TFT-LCD), and more particularly, to a thin-film transistor liquid crystal display device having a low power consumption by forming a light shielding film on a TFT substrate to reduce power consumption and improve image quality.

액티브 매트릭스형 액정 표시(active matrix-type liquid crystal display, AM-LCD) 박막으로서 액티브 매트릭스형 액정표시 소자(LCD)에 있어서 각 화소마다 화상신호를 스위칭 하기 위한 스위칭 소자로 널리 사용되고 있다. 이러한 AM-LCD에 있어서 개개의 화소전극들이 독립적으로 구동되기 때문에 duty rate의 감소에 의한 contrast가 감소되지 않으며 디스플레이 용량이 증가하여 라인수가 증가되어도 시야각이 감소되지 않는다.As an active matrix liquid crystal display (AM-LCD) thin film, an active matrix liquid crystal display (LCD) is widely used as a switching element for switching image signals for each pixel. Since the individual pixel electrodes in the AM-LCD are driven independently, contrast due to a decrease in duty rate is not reduced, and the viewing angle is not reduced even if the number of lines is increased due to an increase in display capacity.

통상 TFT-LCD는 TFT매트릭스가 배치된 TFT기판에 칼라필터 및 공통전극을 배치한 칼라필터기판을 상호 대향되도록 고정하고, 그 사이 수 ㎛의 공간에 액정을 봉입한 패널(panel)을 2매의 편광판으로 끼운 구조로 형성된다. TFT기판 상에는 복수의 신호선과 주사선이 매트릭스 형태로 배열되며, 상기 신호선과 주사선에 의해 포위된 부분이 하나의 화소(pixel)로 정의된다. 화소전극 및 공통전극에는 투명전도막이 사용되므로 TFT기판의 후면에 후광을 조사시켜 칼라 필터에서 산출되는 광을 식별하는 방식으로써 이용된다.In general, a TFT-LCD fixes a color filter substrate and a color filter substrate on which a TFT matrix is disposed so as to face each other, and two panels containing liquid crystal in a space of several μm therebetween. It is formed into a structure sandwiched by a polarizing plate. A plurality of signal lines and scanning lines are arranged in a matrix form on the TFT substrate, and a portion surrounded by the signal lines and the scanning lines is defined as one pixel. Since a transparent conductive film is used for the pixel electrode and the common electrode, it is used as a method of identifying the light produced by the color filter by irradiating a back light to the rear surface of the TFT substrate.

이때, 후광이 통과될 시 칼라필터기판의 각 칼라필터패턴 경계지역에서 빛의 난반사가 발생하여 화질이 저하되는 문제가 발생하는데, 종래에는 이를 방지하기 위하여 칼라필터패턴의 경계지역에 차광막을 형성하였다. 그러나 이는 칼라필터기판과 TFT기판을 배열할 시 오차를 고려하여 차광막 패턴의 폭을 상당량으로 크게 형성하여야 하며, 이는 LCD의 개구율을 감소시킨다. 또한 차광막으로 인해 개구율이 작으므로 후광의 소비전력을 증가시키지 아니하면 화질이 저하된다.In this case, when the halo passes, there is a problem in that the image quality is deteriorated due to diffused reflection of light in the boundary area of the color filter pattern of the color filter substrate. . However, in consideration of an error in arranging the color filter substrate and the TFT substrate, the width of the light shielding film pattern should be formed to a large amount, which reduces the aperture ratio of the LCD. In addition, since the aperture ratio is small due to the light shielding film, the image quality deteriorates unless the power consumption of the back light is increased.

또한 수소화된 비정질 실리콘(Hydrogenated amorphous silicon)과 같은 반도체 레이어(layer)를 이용하여 형성된 액티브층이 형성되는 TFT-LCD에 있어서, 상기 반도체 레이어는 상대적으로 저하된 전계 효과 이동도를 가지며, 신호가 인가될 시 채널이 단지 절연막과 액티브층 사이에서만 형성되므로 온전류(on current)가 낮은 단점이 있다.Also, in a TFT-LCD in which an active layer formed using a semiconductor layer such as hydrogenated amorphous silicon is formed, the semiconductor layer has a relatively reduced field effect mobility and a signal is applied. When the channel is formed only between the insulating film and the active layer has a disadvantage of low on current (on current).

본 고안은 상술한 문제점을 해결하기 위하여 안출된 것으로, 본 고안의 목적은 소비전력이 감소되고 화질을 개선시키도록 한 저소비전력의 박막 트랜지스터 액정표시장치를 제공하는 것이다.The present invention has been made to solve the above problems, and an object of the present invention is to provide a low power consumption thin film transistor liquid crystal display device to reduce power consumption and improve image quality.

도 1은 본 고안에 의한 TFT-LCD를 나타내는 단면도.1 is a cross-sectional view showing a TFT-LCD according to the present invention.

도 2 내지 도 5는 본 고안의 TFT-LCD의 각각의 제조공정을 나타내는 단면도.2 to 5 are cross-sectional views showing respective manufacturing processes of the TFT-LCD of the present invention.

상기 과제를 달성하기 위하여 본 고안에 따른 저소비전력의 박막 트랜지스터 액정표시장치는, 소스 전극, 드레인 전극 및 게이트 전극이 유리기판상에 구비된 박막 트랜지스터에 P-TEOS(Plasma-based TetraEthyl OrthoSilicate)막, SOG(Spin On Grass)막, SOG막 및 P-TEOS 막이 순차적으로 적층된 절연1막이 도포되고, 상기 절연1막 상에 상기 박막 트랜지스터에 대응되어 형성된 차광막 패턴의 결과물 상의 전면에 절연2막이 형성되며, 상기 절연1,2막을 관통하고 상기 드레인 전극을 노출시키는 콘택홀을 통하여 상기 드레인 전극과 연결된 화소 전극이 구비됨을 특징으로 한다.In order to achieve the above object, a low power consumption thin film transistor liquid crystal display device includes a P-TEOS (Plasma-based TetraEthyl OrthoSilicate) film, a SOG, in a thin film transistor having a source electrode, a drain electrode, and a gate electrode provided on a glass substrate. (Spin On Grass) an insulation 1 film is formed by sequentially stacking a film, an SOG film, and a P-TEOS film, and an insulation 2 film is formed on the entire surface of the light shielding film pattern formed corresponding to the thin film transistor on the insulation 1 film. And a pixel electrode connected to the drain electrode through a contact hole penetrating the insulation 1 and 2 films and exposing the drain electrode.

본 고안에 따른 저소비전력의 박막 트랜지스터 액정표시장치는 상기 차광막 패턴이 Ti 또는 TiN 로 형성되고, 상기 차광막 패턴의 두께가 300 내지 3000Å로 형성됨을 특징으로 한다.In the low power consumption TFT LCD according to the present invention, the light shielding layer pattern is formed of Ti or TiN, and the thickness of the light shielding layer pattern is 300 to 3000 kV.

이하 본 고안의 바람직한 실시예를 첨부한 도면을 참조하여 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

본 고안에 따른 저소비전력의 박막 트랜지스터 액정표시장치는 차광막(Black Matrix) 패턴을 칼라필터기판이 아닌 TFT기판에 형성하여 TFT-LCD의 개구율이 증가하고, 백 라이트(Back Light)의 소비전력이 감소되며, 차광막과 화소 전극 사이에 수용적이 형성되어 화질이 개선된다.In the low power consumption thin film transistor liquid crystal display device according to the present invention, a black matrix pattern is formed on a TFT substrate instead of a color filter substrate, thereby increasing the aperture ratio of the TFT-LCD and reducing power consumption of the back light. As a result, a water receptacle is formed between the light blocking film and the pixel electrode, thereby improving image quality.

도 1은 본 고안에 의한 TFT-LCD를 나타내는 단면도로, 본 고안에 따른 TFT-LCD의 TFT기판에는 유리기판상에 비정질 실리콘(a-Si)막으로 이루어진 반도체막 패턴(1,3)이 형성된다. 상기 반도체막 패턴(1,3)은 각각 TFT의 활성층으로, 스토리지 커패시터의 하부전극으로 사용된다. 위 반도체막 패턴들(1,3) 상에는 이들을 절연시키는 절연막(5)이 예컨대 CVD 산화막으로 형성되어 있으며, 위 절연막(5)상에는 공히 알루미늄(Al) 등으로 이루어진 게이트 전극(7) 및 스토리지 커패시터의 상부전극(9)이 형성된다. 상기 절연막(5)은 TFT의 게이트 절연막으로 사용되고, 상기 하부전극용 반도체막 패턴(3)과 상부전극(9)은 이들 사이에 위치한 절연막(5)과 아울러 스토리지 커패시터를 형성한다.1 is a cross-sectional view showing a TFT-LCD according to the present invention, wherein a semiconductor film pattern (1,3) consisting of an amorphous silicon (a-Si) film is formed on a glass substrate of a TFT-LCD according to the present invention. . Each of the semiconductor film patterns 1 and 3 is used as an active layer of a TFT and is used as a lower electrode of a storage capacitor. An insulating film 5 for insulating them is formed on the upper semiconductor film patterns 1 and 3, for example, by a CVD oxide film, and on the upper insulating film 5, the gate electrode 7 and the storage capacitor are made of aluminum (Al) or the like. The upper electrode 9 is formed. The insulating film 5 is used as a gate insulating film of the TFT, and the lower electrode semiconductor film pattern 3 and the upper electrode 9 together with the insulating film 5 positioned therebetween form a storage capacitor.

이들 결과물 상에 이들을 덮는 절연막(11)으로써 저온산화막(LTO)이 형성되어 있다. 콘택홀은 위 절연막(11) 상에는 상기 절연막(5, 11)들을 연속적으로 식각하여 TFT의 활성층으로 사용되는 반도체막 패턴(1)을 노출시키도록 마련된다. 위 콘택홀 매립하여 형성된 소스 전극(13)과 드레인 전극(15)은 위 콘택홀을 매립함으로써 형성되고, 위 소스 전극(13)과 드레인 전극(15)은 크롬(Cr) 등과 같은 금속막으로 이루어져 있다. 이들 결과물의 전면에는 이들을 덮는 절연1막(17)이 형성되어 있고, 위 절연1막은 P-TEOS막, SOG(Spin On Grass)막 및 P-TEOS막이 순차적으로 적층된 구조로써 마련된다.The low-temperature oxide film LTO is formed as the insulating film 11 covering these on these products. The contact hole is formed on the upper insulating film 11 to expose the semiconductor film pattern 1 used as the active layer of the TFT by continuously etching the insulating films 5 and 11. The source electrode 13 and the drain electrode 15 formed by filling the contact hole are formed by filling the contact hole, and the source electrode 13 and the drain electrode 15 are made of a metal film such as chromium (Cr) or the like. have. An insulating one film 17 covering them is formed on the entire surface of the resulting product, and the insulating one film is provided as a structure in which a P-TEOS film, a spin on grass (SOG) film, and a P-TEOS film are sequentially stacked.

위 절연1막(17) 상에는 차광막 패턴(19)이 형성되며, 위 차광막(19)은 티타늄(Ti) 또는 티타늄 나이트라이드(TiN)로 이루어지고 그 두께는 300 내지 3000Å 정도로 구비됨이 바람직하다. 이들 결과물의 전면에는 P-TEOS막으로 이루어진 절연2막(21)이 형성된다.The light shielding film pattern 19 is formed on the insulating layer 1, and the light shielding film 19 is made of titanium (Ti) or titanium nitride (TiN) and has a thickness of about 300 to 3000 kPa. Insulating 2 film 21 made of a P-TEOS film is formed on the entire surface of these results.

이들 결과물 상에는 드레인 전극의 일부를 노출시키도록 형성된 콘택홀을 통하여 드레인 전극과 연결된 화소전극(25)이 형성되고, 위 화소전극(25)은 예컨대 ITO(Indium Tin Oxide) 등과 같은 투명 도전막으로 형성된다.On these products, a pixel electrode 25 connected to the drain electrode is formed through a contact hole formed to expose a portion of the drain electrode, and the pixel electrode 25 is formed of a transparent conductive film such as indium tin oxide (ITO), for example. do.

본 고안에 따른 저소비전력의 박막 트랜지스터 액정표시장치는 다음과 같은 공정으로 형성된다.The low power consumption thin film transistor liquid crystal display device according to the present invention is formed by the following process.

유리기판상에 소스 전극(13), 드레인 전극(15) 및 게이트 전극(7)으로 이루어진 TFT와 하부전극(3), 절연막(5) 및 상부전극(9)으로 이루어지는 스토리지 커패시터를 형성하는 단계가 도 2에 도시되었다. 유리기판상에 비정질 실리콘(a-Si)막을 증착한 후 결정화하여 반도체막을 형성하고, 위 반도체막을 패터닝함으로써 TFT의 활성층과 스토리지 커패시터의 하부전극으로 사용될 반도체막 패턴(1,3)을 형성한다.A step of forming a storage capacitor including a TFT consisting of a source electrode 13, a drain electrode 15, and a gate electrode 7 and a lower electrode 3, an insulating film 5, and an upper electrode 9 on a glass substrate is shown in FIG. 2 is shown. After depositing an amorphous silicon (a-Si) film on a glass substrate, crystallization is performed to form a semiconductor film, and the upper semiconductor film is patterned to form semiconductor film patterns (1, 3) to be used as an active layer of a TFT and a lower electrode of a storage capacitor.

위 반도체막 패턴(1,3)이 형성된 기판 상에 산화막을 증착하여 절연막(5)을 형성하며, 위 절연막(5)은 TFT의 게이트 절연막과 스토리지 커패시터의 유전막으로 사용된다.An insulating film 5 is formed by depositing an oxide film on a substrate on which the upper semiconductor film patterns 1 and 3 are formed. The insulating film 5 is used as a gate insulating film of a TFT and a dielectric film of a storage capacitor.

위 절연막(5) 상에 알루미늄(Al)을 증착하고 이를 패터닝하여 게이트 전극(7) 및 스토리지 커패시터의 상부전극(9)을 형성한다. 다음으로, TFT부의 상기 반도체막을 dope하여 TFT의 소스 및 도시되지 아니한 드레인을 형성한다. 계속하여 상기 결과물의 전면에 산화막을 증착하여 상기 게이트 전극(7)과 상부전극(9) 또는 다른 도전막을 절연하고, 위 절연막(5, 11)들을 연속 식각하여 상기 소스 및 드레인을 노출시키는 콘택홀을 형성한다. 이 결과물의 전면에 예컨대 크롬(Cr) 등을 증착한 후 패터닝하여 소스 전극(13)과 드레인 전극(15)을 형성한다.Aluminum (Al) is deposited on the upper insulating layer 5 and patterned to form the gate electrode 7 and the upper electrode 9 of the storage capacitor. Next, the semiconductor film of the TFT portion is dope to form a source of the TFT and a drain not shown. Subsequently, an oxide film is deposited on the entire surface of the resultant to insulate the gate electrode 7 and the upper electrode 9 or another conductive layer, and continuously etch the insulating layers 5 and 11 to expose the source and drain. To form. For example, chromium (Cr) or the like is deposited on the entire surface of the resultant and then patterned to form a source electrode 13 and a drain electrode 15.

차단막 패턴(19)으로는 도 3에서, 위 결과물 상의 전면에 절연1막(17)을 형성하는데, 플라즈마 CVD를 이용하여 P-TEOS(TetraEthyl OrthoSilicate)막을 5000Å의 두께로 증착하고, SOG막을 2200Å의 두께로 도포한 후 상기 SOG막을 베이킹하되, 위 SOG막 두께의 균일도를 얻기 위하여 다수회 반복할 수 있다. 상기 SOG막을 에치백(etch back)하여 절연1막(17)의 표면을 평탄화한다. 후속 차광막 패턴을 형성하기 위한 식각공정시 SOG막이 노출되지 아니하도록 플라즈마 CVD를 이용하여 P-TEOS 막을 2000Å 더 증착하는데, 이는 후속 드레인 전극과 투명도전막을 연결시키기 위한 습식식각시 식각액에 의하여 SOG막이 용융되는 문제를 제지하기 위함이다.As the blocking film pattern 19, an insulating film 1 is formed on the entire surface of the upper product in FIG. 3. After coating with a thickness, the SOG film is baked, but may be repeated many times to obtain a uniformity of the thickness of the SOG film. The SOG film is etched back to planarize the surface of the insulating film 1 17. The P-TEOS film is further deposited by using plasma CVD to prevent exposure of the SOG film during the etching process to form a subsequent light shielding pattern. To restrain the problem.

위 절연1막(17) 상의 전면에 차광용 Ti 또는 TiN 등을 300 내지 3000Å의 두께로 증착하여 패터닝함으로써 빛의 난반사를 방지하는 차광막 패턴(19)을 형성한다.A light shielding film pattern 19 for preventing diffuse reflection of light is formed by depositing and patterning light shielding Ti or TiN to a thickness of 300 to 3000 Å on the entire surface of the insulating layer 1 17.

위 차광막 패턴(19)을 형성하기 위한 패터닝 공정은 Ti 또는 TiN에 대해 식각율이 높은 BCl3+ Cl2+ CHF3의 혼합가스 또는 BCl3+ Cl2의 혼합가스 등을 이용하는 건식식각으로 행하여진다. 차광막 패턴(19)이 칼라필터기판이 아닌 하판에 설치되면 차광막 패턴의 폭을 크게 할 필요가 없으므로, 개구율이 증가하여 백 라이트의 소비전력이 감소되며 화질을 개선할 수 있다.Patterning step for forming the above light-shielding film pattern (19) is performed through dry etching using such a mixture gas of the etching rate is high BCl 3 + Cl 2 + CHF 3 gas mixture, or BCl 3 + Cl 2 relative to the Ti or TiN . When the light shielding film pattern 19 is installed on the lower plate instead of the color filter substrate, it is not necessary to increase the width of the light shielding film pattern, so that the aperture ratio is increased, power consumption of the backlight is reduced, and image quality can be improved.

도 4 내지 도 5에서 상기 결과물 상의 전면에 4000Å 두께의 P-TEOS막을 증착하여 절연2막(21)을 형성한다. 위 절연1막(17)과 절연2막(21)을 연속적으로 사진식각하여 드레인 전극(15)의 일부를 노출시키는 콘택홀(23)을 형성한다. 위 콘택홀(23)을 매립하면서 위 결과물 상의 전면에 ITO(Indium Tin Oxide)를 증착하고, 위 ITO를 패터닝하고 식각함으로써 투명도전막(25)을 완성한다. 마지막으로, 차광막 패턴이 없는 칼라필터기판과 본 고안의 TFT 기판을 얼라인한 후 액정을 주입하여 TFT-LCD를 완성한다. 여기서, 화소 전극(25)과 차광막 패턴(19)의 사이에 추가적으로 커패시터가 형성되어 유지용량(Cst)이 증가하고, TFT 스위치가 ON되어 유지용량에 충전된 전하가 TFT 스위치가 OFF 된 동안에도 다음 신호 인가전압을 위한 TFT ON 시까지 충실히 유지되어 화질이 향상된다.4 to 5, a P-TEOS film having a thickness of 4000 에 is deposited on the entire surface of the resultant product to form an insulating second film 21. The first insulating layer 17 and the second insulating layer 21 are successively photographed to form a contact hole 23 exposing a part of the drain electrode 15. While filling the contact hole 23, ITO (Indium Tin Oxide) is deposited on the entire surface of the resultant product, and the ITO is patterned and etched to complete the transparent conductive film 25. Finally, after aligning the color filter substrate without the light shielding film pattern and the TFT substrate of the present invention, liquid crystal is injected to complete the TFT-LCD. Here, an additional capacitor is formed between the pixel electrode 25 and the light shielding film pattern 19 to increase the holding capacitor Cst, and the charge charged to the holding capacitor due to the TFT switch is turned on while the TFT switch is turned off. It is faithfully maintained until the TFT ON for the signal application voltage, thereby improving the image quality.

이상으로 본 고안의 실시예를 상세하게 설명하였으나, 본 고안은 이에 한정되지 아니하고 본 고안의 기술적 사상의 범위 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능하다.Although the embodiments of the present invention have been described in detail above, the present invention is not limited thereto and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention.

본 고안에 따른 저소비전력의 박막 트랜지스터 액정표시장치는 TFT기판에 차광막 패턴을 형성함으로써 개구율과 유지용량을 증가시켜 백 라이트의 소비전력이 감소되며, 백 라이트의 소비전력을 증가시키지 아니하고도 화질이 증가된다.In the low power consumption thin film transistor liquid crystal display device according to the present invention, by forming a light shielding film pattern on a TFT substrate, the power consumption of the backlight is reduced by increasing the aperture ratio and the holding capacity, and image quality is increased without increasing the power consumption of the backlight. do.

Claims (3)

소스 전극, 드레인 전극 및 게이트 전극이 유리기판상에 구비된 박막 트랜지스터에 P-TEOS막, SOG막 및 P-TEOS 막이 순차적으로 적층된 절연1막이 도포되고, 상기 절연1막 상에 상기 박막 트랜지스터에 대응되어 형성된 차광막 패턴의 결과물 상의 전면에 절연2막이 형성되며, 상기 절연1,2막을 관통하고 상기 드레인 전극을 노출시키는 콘택홀을 통하여 상기 드레인 전극과 연결된 화소 전극이 구비됨을 특징으로 하는 저소비전력의 박막 트랜지스터 액정 표시장치.Insulating 1 film in which a P-TEOS film, an SOG film, and a P-TEOS film are sequentially stacked is coated on a thin film transistor having a source electrode, a drain electrode, and a gate electrode on a glass substrate, and the thin film transistor corresponds to the thin film transistor on the insulating 1 film. The insulating film 2 is formed on the entire surface of the resultant light-shielding film pattern, and the pixel electrode connected to the drain electrode is provided through a contact hole for penetrating the insulating films 1 and 2 and exposing the drain electrode. Transistor Liquid Crystal Display. 청구항 1에 있어서,The method according to claim 1, 상기 차광막 패턴이 Ti 또는 TiN 로 형성됨을 특징으로 하는 저소비전력의 박막 트랜지스터 액정 표시장치.The thin film transistor liquid crystal display of claim 1, wherein the light blocking layer pattern is formed of Ti or TiN. 청구항 1에 있어서,The method according to claim 1, 상기 차광막 패턴의 두께가 300 내지 3000Å로 형성됨을 특징으로 하는 저소비전력의 박막 트랜지스터 액정 표시장치.The thin-film transistor liquid crystal display device having a low power consumption, characterized in that the light shielding film pattern has a thickness of 300 to 3000 300.
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