KR200356468Y1 - Inverter stack having multi-layer bus plate - Google Patents

Abstract

In order to minimize stray inductance in a large capacity power converter, an inverter stack apparatus having an integrated multilayer bus plate is disclosed. Such an inverter stack device includes: a capacitor unit configured to receive an applied DC voltage and perform noise filtering; An inverter unit having a plurality of insulated gate bipolar transistor elements, converting a DC voltage output through the capacitor unit into an AC voltage by performing a switching operation according to a driving voltage applied to a gate of the transistor element; A cooling unit configured to cool the inverter unit by absorbing and radiating heat generated in a switching operation of the transistor element; A driving unit for applying the driving voltage to a gate of the transistor element to control an AC voltage output through the inverter unit; The negative electrode plate, an insulating plate formed between the positive and negative plates to insulate between the positive and negative plates, one of the positive or negative plates and the insulating plate perpendicularly to the plate length direction And a bus plate portion including an interconnecting plug in contact with a lower surface of the positive electrode plate and having an inner through hole formed therein, and a molding portion integrally fixing the plates and the interconnection plug and molding the insulation plates.

Description

Inverter stack device with integrated multi-layer bus plate {INVERTER STACK HAVING MULTI-LAYER BUS PLATE}

The present invention relates to a large capacity power converter, and more particularly, to an inverter stack device having a bus plate for minimizing stray inductance.

In recent years, the inverter has been widely used as a variable voltage or variable frequency power converter in an industrial field. Inverters are widely known as devices for converting direct current into alternating current through fast switching of transistor elements as one of power converters.

Important considerations in the design of such inverters include: In other words, an expression indicating the spike voltage at the time of switching is given as VS = L · di / dt. VS is a spike voltage at the time of switching, and L represents an inductance component. In general, the faster the switching in the inverter, as can be seen from the above equation, the clean AC waveform can be obtained while the spike voltage becomes larger. As a method for solving this problem, the design of the snubber circuit and the reduction of the stray inductance value are roughly classified.

More specifically, the IGBT module, which is a switching semiconductor device currently used in a converter or inverter system of less than 1MW class, is capable of high-speed switching of 10KHz or more.

Shorter current rise and fall times are advantageous to reduce switching losses in the device. As a result, the current flowing between the switching module and the DC link in the converter or inverter changes rapidly over a very short time. As a result, very large di / dt and parasitic inductance, called stray inductance, occur at the bus bar, resulting in overshoot voltage spikes that have a significant effect on the device. To get up.

In practice, such spikes can cause catastrophic effects on the switch module. To prevent such spikes, the conventional method is to first attach an RCD snubber circuit across the switch, or secondly, a current path. Instead of using wires to reduce the stray inductance of the bus, a bus bar or a planar bus is used. The first method is disadvantageous in that the device is compact in size and light weight, and the manufacturing cost of equipment is high.

On the other hand, the use of a bus bar or a flat-panel is difficult to minimize the inductance value due to difficulty in maximizing the power connection area and minimizing the distance between electrodes, but there is room for improvement.

Since the MOS gate device is a high-speed switching device, the current rising rate or falling rate (di / dt) of the main current (Ic: collector current) is very high at the time of turn-on or turn-off switching. On the other hand, parasitic inductance always exists in the wiring of the main circuit. Therefore, during IGBT switching, the switching surge voltage V _CE is generated at the main terminal as shown below.

V _CE = L (di / dt) ---- Formula (1)

As shown in Equation (1), the surge voltage applied to the IGBT is proportional to the stray inductance and current change rate di / dt present in the main circuit wiring. In other words, to protect the IGBT from surge voltage breakdown, the wiring inductance may be reduced or the current change rate may be lowered. However, lowering the current rate of change impairs high-speed switching performance, and thus has a limitation that it cannot be used fundamentally for high frequency applications.

Referring to Fig. 5, the generation form of the surge voltage in the conventional IGBT switching is shown.

Referring to the drawing showing the waveform of the overshoot voltage, the turn-off surge voltage V _CE is determined by -di / dt ₍₁₎ and -di / dt ₍₂₎ , which are determined by the fall time t _f of the device. ₍₁₎ , V _{CE (2)} is generated. These -di / dt ₍₁₎ and -di / dt ₍₂₎ can be controlled somewhat by the gate resistance R _G of the device, but it can be seen that lowering di / dt has a limit because it increases switching loss. have.

In order to reduce the system loss, the inverter system using the IGBT, which is a high-speed switching device, operates the rise time and fall time of the current at about 300 nsec or less. As a result, the current flowing between the inverter switch module and the DC link changes rapidly in a very short time. If the current of 300A changes for 300nsec (1A / nsec), even if there is only a few hundred nH of stray inductance between the switch module and the DC link, a voltage spike of 1V per nH will occur. Therefore, if the device exceeds the rating due to spikes of several hundred volts at the moment of high current off such as OC protection, the device may be destroyed. Therefore, measures to minimize the stray inductance are urgently needed.

As described above, there is a problem in that the stray inductance cannot be minimized due to a problem in the bus connection structure when the inverter stack STACK, which is a large-capacity power converter, is formed. Therefore, it is difficult to sufficiently reduce the overshoot voltage spike, there is a problem that the reliability of the inverter stack is lowered.

Accordingly, an object of the present invention is to provide an inverter stack device capable of minimizing stray inductance of an inverter stack.

Another object of the present invention is to provide a bus connection structure of an inverter stack capable of maximizing each power connection area in the inverter stack and minimizing the distance between electrodes.

Still another object of the present invention is to provide an inverter stack device and a method of minimizing stray inductance, which can significantly reduce an overvoltage generated in a device without employing a separate snubber circuit.

It is another object of the present invention to provide a bus plate structure of an inverter stack device that is easy to assemble and minimize spray inductance.

According to an aspect of the present invention for achieving some of the above objects, an inverter stack device includes: a capacitor unit for receiving noise by applying an applied DC voltage; An inverter unit having a plurality of insulated gate bipolar transistor elements, converting a DC voltage output through the capacitor portion into an AC voltage by performing a switching operation according to a driving voltage applied to a gate of the transistor element;

A cooling unit configured to cool the inverter unit by absorbing and radiating heat generated in a switching operation of the transistor element; A driving unit for applying the driving voltage to a gate of the transistor element to control an AC voltage output through the inverter unit; An anode plate for connecting between the collector of the transistor element and the anode of the capacitor portion, a cathode plate for connecting between the emitter of the transistor element and the cathode of the capacitor portion, and an anode for insulating between the anode and the cathode plate And an interconnection plug formed between the cathode plates and one of the anode or cathode plates and the insulation plate perpendicular to the plate length direction to be in contact with the bottom surface of the cathode or anode plate and having an inner through hole formed therein. And a bus plate portion including a molding portion for molding the plates and the interconnection plug integrally and insulated from each other.

1 is a block diagram of a large-capacity power inverter stack device according to the present invention

2 is an equivalent circuit diagram of a main block of FIG.

3 is a basic cross-sectional view of the bus plate of FIG. 1

4 is an enlarged cross-sectional view of the bus plate of FIG. 1

5 is a view for explaining the generation form of the surge voltage in the conventional IGBT switching

6 is a view showing the Vce voltage waveform when the IGBT turn off in the device according to the present invention

FIG. 7 is a view showing a photo of the apparatus of FIG. 1 actually manufactured.

* Explanation of symbols for main parts of the drawings

10: capacitor 20: inverter

30 bus plate part 40 cooling part

50: drive unit 60: induction motor

31: anode plate 33: cathode plate

32: interconnection plug 35: mold part

Hereinafter, an inverter stack apparatus having an integrated multilayer bus plate according to an embodiment of the present invention will be described with reference to the accompanying drawings. Although shown in different drawings, components having the same or similar functions are represented by the same or similar reference numerals.

1 is a block diagram of a large-capacity power inverter stack device according to the present invention. Referring to the drawings, the inverter stack device, the capacitor unit 10, the inverter unit 20, the cooling unit 40 in order to adjust the rotational force or the rotational speed of the three-phase AC motor 60 for moving a railway vehicle or the like. ), A drive unit, and a bus plate unit 30. The rotational force (torque) is adjusted by controlling the voltage of the three phases (U, V, W), and the rotational speed is adjusted by controlling the frequency of the three phases (U, V, W).

2 shows an electrical equivalent circuit of the critical functional blocks in FIG.

Referring to FIG. 1 and FIG. 2 showing an equivalent circuit, the capacitor unit 10 performs noise filtering by receiving a direct current (DC) voltage applied with polarities of a positive electrode (+) and a negative electrode (−). The inverter unit 20 includes a plurality of insulated gate bipolar transistor (IGBT) elements 21 and performs the switching operation according to a driving voltage applied to the gate of the transistor element 21 to thereby provide the capacitor unit 10. It converts the DC voltage output through to 3 phase (U, V, W) AC voltage and outputs it. The plurality of transistor elements 21 shown in FIG. 2 constitute three arms 24 in which each emitter and collector are connected to each other. The reflux antiparallel diode 22 allows the current in the device to circulate normally when the transistor element 21 is operated. A snubber capacitor that protects the transistor element 21 by attenuating an overvoltage generated when the transistor element 21, which is a switching element, is turned off may be installed between the nodes ND1 and ND2 of each arm 24. have.

The cooling unit 40 shown only in FIG. 1 typically includes a cooling fan, and allows the inverter unit 20 to cool by absorbing and radiating heat generated in the switching operation of the transistor element. The driving unit 50 applies a driving voltage to the gate of the transistor element 21 to control the AC voltage output through the inverter unit 20. Here, the level of the driving voltage is determined depending on the sensing output of the sensing unit for sensing the driving state of the induction motor 60.

The bus plate portion 30 includes an anode plate 31 for connecting the collector C of the transistor element 21 and the anode (+) of the capacitor portion 10, and the transistor element 21. It basically includes a cathode plate 33 for connecting between the emitter (E) and the cathode (-) of the capacitor unit (10). In addition, the bus plate portion 30 includes an insulating plate, an interconnection plug, and a molding portion, which will be described with reference to FIGS. 3 and 4.

3 is a basic cross-sectional structural view of the bus plate of FIG. Referring to the drawings, an insulating plate 37 formed between the positive and negative plates 31 and 33 and the positive or negative plates 31 and 33 to insulate between the positive and negative plates 31 and 33. An interconnection plug 32 in which one of the insulating plates 37 passes perpendicular to the plate length direction and contacts lower surfaces of the cathode or anode plates 33 and 31 and has an inner through hole 32h formed therein; A molding part 35 is shown for molding the plates 31, 33, 37 and the interconnect plug 32 insulated from one another while being integrally fixed. By the molding action of the molding part 35, the plates and the interconnection plug are integrally formed without deviating from each other, thereby achieving the basic purpose according to the present invention, as well as convenience of handling and assembly. Here, the molding may be implemented through conventional insulating epoxy coating and drying. Reference numerals 39A and 39B which are not described in FIG. 3 are collector and emitter fastening screws, respectively. According to the above structure, the collector C of the transistor element is electrically connected to the positive electrode plate 31 through the interconnection plug 32 while being insulated from the negative electrode plate 33. Is connected to the positive (+) of.

FIG. 4 is an enlarged cross-sectional structure diagram of the bus plate part of FIG. 1, in which an output plate is stacked on top of the anode plate 31 via another insulating plate. Referring to the drawings, reference numerals 36 and 37 denote insulating sheets and insulating plates, 33 is a negative plate, 31 is a positive plate, and 34 is an output plate. The output plate 34 is shown as the same reference numeral in the equivalent circuit of FIG. The plates 31, 33, 36, 37 have a generally rectangular pattern, and the patterns have fastening holes 39a, 39b, 39c and receiving holes 33A for accommodating the interconnection plug. Is formed. Here, the receiving holes 33A are shown only in FIG. 3, and are shown to be formed only in the negative electrode plate 33. Here, the insulating sheet 36 is very thin than the thickness of the insulating plate 37, it may be implemented as an insulating film sheet.

In this way, the bus connection structure is formed into a plate (flat plate) and laminated in a multi-layer to perform shielding and molding, thereby maximizing the area of each power source and minimizing the distance between electrodes. Thus, the overvoltage generated in the device can be significantly reduced without employing a separate snubber circuit.

On the other hand, when DC current flows on an infinitely wide plate, the formula for calculating the magnetic inductance value is given by

Lself = 2l [ln (2l / W + t) + 1/2 +2/9 (W + t / l) ---- becomes (2).

Where l is length (cm), W is width (cm), t is thickness (cm), and Lself is magnetic inductance (nH).

As can be seen from the above equation, the wider, thicker and shorter the magnetic inductance value becomes. However, the effective current is limited by the skin effect because the current flowing contains a high frequency component proportional to the switching frequency. Here, if an insulator is inserted between the P side and the N side bus plate and attached as close as possible, the effect of spread capacitance can be seen. For reference, the capacitance between two adjacent flat conductors with an insulator interposed is calculated according to the following formula.

C = 0.255KWl / d [pF] ---- becomes equation (3).

Where K is the specific permittivity constant and d is the spacing between the two flat conductors.

Therefore, the stray inductance generated by the multilayer structure in which the anode and cathode plates are stacked is minimized compared to the bus bar structure.

Fabrication of the integrated bus plate portion of FIG. 3 including the output plate 34 of FIG. 4 is as follows. First, a cathode plate 33, which forms a plurality of holes in a generally rectangular pattern, is formed by a copper plate. This operation can be achieved in a minimal process by processing patterns and holes by placing them in a press die. In addition, the cathode plate 31 and the output plate 34 are also formed in the same size as the cathode plate 33.

Here, when the cathode plate 33 is located at the bottom, the diameters of the holes 33A formed in the cathode plate 33 are larger than the diameters of the holes 32h formed in the anode plate 31. do. This is because the outer diameter of the conductive interconnect plug 32 can be easily accommodated. Accordingly, the interconnection plug 32 having the set outer diameter and inner diameter size is also prepared in advance, and the insulating film, that is, the insulating plates 37 for electrical insulation, is also prepared by processing holes accordingly. When all of the above preparations are completed, the plates are stacked in the form of inserting the conductive interconnect plug 32 in the order of lamination shown in FIG. 4 on the working die. In such a state, a mold for molding processing slightly larger than the rectangular size of the plates is placed outside, and the prepared epoxy is poured to form a molding 25 as shown in FIG. Thereafter, curing the epoxy through natural drying or oven drying yields an integral bus plate structure in which the multilayer plates are bonded to each other. The bus plate part is integral so that all the plates can be handled at the same time during assembly or disassembly.

FIG. 5 is a diagram for explaining a generation form of surge voltage during IGBT switching. FIG. 6 is a diagram showing voltage waveforms between Vce at turn-off of an insulated gate bipolar transistor (IGBT) element. This is the waveform when the multi-layer bus plate structure is integrated and assembled into a large capacity inverter stack. As a result of measuring the Vce voltage waveform of the transistor element in the inverter stack, it can be seen that Vce = 80V when Vdc = 600V, which demonstrates that the stray inductance drop action of the bus plate according to the present invention exhibits excellent characteristics. do.

FIG. 7 is a view showing the actual fabrication of the apparatus of FIG. 1, in which the external structure of the integrated multilayer bus plate portion including the output plate shown in FIG. 4 is fastened to the upper portion of the capacitor by fastening screws. have.

According to the structure of the integrated bus plate described above, the assembly workability of the device is also easy due to the minimized stray inductance and the integrated configuration.

In the above description, the embodiments of the present invention have been described with reference to the drawings, for example, but it is apparent to those skilled in the art that the present invention can be variously modified or changed within the scope of the technical idea of the present invention. . For example, in the case of different matters, the detailed structure of the data output multiplexer can be changed into various forms.

According to the present invention as described above, by applying an integrated multilayer bus plate structure, there is an effect that can ultimately significantly reduce the stray inductance. Therefore, the overshoot voltage generated when the IGBT element is turned off is suppressed, thereby simplifying or eliminating snubber circuits and preventing damage to the IGBT due to voltage spikes. In addition, the IGBT device has a shorter current rise time and fall time due to the high frequency orientation, and thus the problem of voltage spike due to stray inductance is expected to be further exacerbated. In this case, the problem of voltage spikes is largely solved, and stable device characteristics can be obtained, thereby increasing reliability. In addition, the integrated multilayer plate structure maximizes the convenience of assembly and dismantling operations.

Claims (7)

In the inverter stacker: A capacitor unit for performing noise filtering by receiving an applied DC voltage; An inverter unit having a plurality of insulated gate bipolar transistor elements, converting a DC voltage output through the capacitor portion into an AC voltage by performing a switching operation according to a driving voltage applied to a gate of the transistor element; A cooling unit configured to cool the inverter unit by absorbing and radiating heat generated in a switching operation of the transistor element; A driving unit for applying the driving voltage to a gate of the transistor element to control an AC voltage output through the inverter unit; An anode plate for connecting between the collector of the transistor element and the anode of the capacitor portion, a cathode plate for connecting between the emitter of the transistor element and the cathode of the capacitor portion while overlapping the anode plate, the anode and cathode plate An insulation plate formed between the anode and cathode plates to insulate the liver, and one of the anode or cathode plates and the insulation plate perpendicular to the plate length direction to contact the lower surface of the cathode or anode plate and penetrate therein And a bus plate portion including an interconnection plug having a hole formed therein and a molding portion integrally fixing the plates and the interconnection plug and molding the insulation plugs. The inverter stack device of claim 1, wherein the plates have a generally rectangular pattern, and the receiving holes are formed in the pattern to accommodate the fastening holes and the interconnection plug. The inverter stack device according to claim 2, wherein a diameter of the receiving holes is larger than a diameter of the fastening holes. The inverter stack device of claim 2, wherein a diameter of an inner through hole of the interconnection plug is equal to a diameter of the fastening holes so that an outer diameter of the fastening element is insertable. The inverter stacking apparatus of claim 1, wherein an output plate is further formed on the anode plate or the cathode plate via another insulation plate to provide an AC voltage output of the inverter unit. The inverter stack device according to claim 1, wherein the plurality of transistor elements constitute three arms in which each emitter and collector are connected to each other. (delete)