KR200334695Y1 - Driving control apparatus for controling light emitting diode display panel - Google Patents

Abstract

The LED driving control apparatus includes a video data memory for receiving and storing image data to be displayed on a dot matrix panel from a shift register, and control data for receiving and storing control data for determining an operation mode of the driving control apparatus through a shift register. Contains memory. And a PWM counter for performing pulse width modulation control on the image data of the video data memory, and a PWM amplitude controller for separating data stored in the video data memory into image data and luminance data and inputting the image data into the PWM counter. .

The 10-bit input data is stored in the video data memory, and the PWM amplitude controller may separate the input data into 8-bit image data and 2-bit luminance data and input the same to the PWM counter. Therefore, the brightness of the LED panel can be easily adjusted.

Description

A driving control device for adjusting the brightness of the LED display panel {DRIVING CONTROL APPARATUS FOR CONTROLING LIGHT EMITTING DIODE DISPLAY PANEL}

The present invention relates to a drive control device for driving a light emitting diode (LED) display panel used for an electronic display plate and an LED display module including such a drive control device. It relates to a drive control device that can be adjusted.

The electronic signboard system displays LEDs, small fluorescent tubes, etc. in a matrix, and displays information such as various characters and pictures, and is generally composed of red, green, and blue (R, G, B) LED elements. The combination of LED display modules displays multiple colors.

There are many ways to drive the LED display module of the electronic display system, but it can be classified into a dynamic method and a static method, and a dynamic method with a small number of driving elements and a low manufacturing cost is used on a large screen. Since it is effective, it is widely used for an electronic sign board system.

1 shows an example of a conventional dynamic drive control circuit for driving a 16x16 LED dot matrix panel.

In FIG. 1, input data (R_DATA, G_DATA, B_DATA) for turning on / off three LEDs of red, green, and blue (R, G, B) is input to each shift register 11, 12, 13, The output terminal may be connected to the next driving control circuit in a cascade form, and output data R_DATA_O, G_DATA_O, and B_DATA_O may be output to the input terminal of the next driving control circuit. In addition, the clock signal CLK is input to each of the shift registers 11, 12, and 13, and the data is sequentially stored in each of the shift registers 11, 12, and 13.

The input data stored in the shift registers 11, 12, 13 are latched to the latch element 14 by the latch signal LATCH_I, and the LED dot matrix panel 10 is passed through the output enable circuit 17. Drive. That is, vertical line data driving to the LED dot matrix panel 10 is performed. At the same time, the address signals AO to A3 are input to the address decoder 18 and decoded to drive the panel 10, thereby driving the horizontal line data driving of the LED dot matrix 10. Is executed. Subsequently, by performing vertical line data driving for the next data while sequentially changing the address input to the address decoder 18, the LED of the LED dot matrix 10 is turned on / off to display an image.

The output enable circuit 17 turns on the vertical line driving data by using the output enable signal OUT_EN at the time when the address is changed to solve the problem that an afterimage occurs due to the horizontal line driving. Control the time appropriately.

In addition, like the input data R_DATA, G_DATA, and B_DATA, the clock signal CLK, the latch signal LATCH_I, and the output enable signal OUT_EN are respectively a clock output signal CLOCK_O, a latch output signal LATCH_O, and an output. As the enable output signal OUT_EN_O, it is output to the drive control circuit of the next LED module connected in cascade form.

In the conventional dynamic driving control circuit, a separate luminance adjusting element is required to adjust the luminance of the LED on the panel, and the clock of the PWM circuit for pulse width modulation of the image data is fixed. Therefore, there is a problem that it is difficult to adjust the brightness of the LED panel.

The present invention is to solve the problems of the conventional drive control device of the LED panel, and to provide a drive control device that can easily adjust the brightness of the LED panel.

1 is a block diagram showing an example of a conventional LED driving control circuit.

2 is a block diagram showing a light emitting diode driving control apparatus according to an embodiment of the present invention.

Figure 3 is a partial block diagram of Figure 2 for explaining the duty ratio variable function of the present invention.

LED drive control device of the present invention for achieving the above object

A shift register for receiving and storing input data for displaying and controlling an image on a dot matrix panel, a video data memory for receiving and storing image data to be displayed on the dot matrix panel from the shift register, and the shift register through the shift register. A control data memory for receiving and storing control data for determining an operation mode of the drive control device, a PWM counter for performing pulse width modulation control on the image data of the video data memory, and a clock for driving the PWM counter And a gradation clock generator for generating a signal and a PWM amplitude controller for separating the data stored in the video data memory into image data and luminance data and inputting the image data into the PWM counter.

The 10-bit input data is stored in the video data memory, and the PWM amplitude controller may separate the input data into 8-bit image data and 2-bit luminance data and input the same to the PWM counter.

In addition, the driving control apparatus according to the present invention can be easily mounted on a light emitting diode display module (LED display module) used in the display board.

Hereinafter, with reference to Figure 2 will be described a preferred embodiment of the present invention.

2 is a block diagram showing an LED driving control apparatus according to an embodiment of the present invention. In FIG. 2, the drive control apparatus which drives the 16x16 LED dot matrix 20 is shown as an example.

In the driving control apparatus of FIG. 2, first, setting signals for determining the overall operation of the driving control are input to the external input mode selector 23, and basic control signals and address signals A0 and A1 for controlling the operation of the driving control apparatus. , A3 and A3 are input to the control signal buffer 22.

The signals input to the external input mode selector 23 include PIN / REGISTER and PRE1 / TEST signals for determining the input method of control data, and LINEOUT_N / P for determining the method of applying data to the line driver. There are a COLOUT_N / P signal, a POSITION0 to POSITION3 signal for determining an address corresponding to the position of each drive control device according to the duty ratio, and a DRIVE_MTRX signal for selecting an output drive to the panel of the drive control device.

The control data is input and set through one of the external pin PIN, the external controller PRE1, and the internal register REGISTER according to the PIN / REGISTER and PRE1 / TEST signals. Here, the TEST signal is for testing the drive control device. Input through the external pin (PIN) is when some of the control data 30 bits are set by the external pin (PIN) and the rest is set in advance internally, input through the external controller (PRE1) is 30 bits control data All of them are stored in the internal memory through the shift register 21 to be described later, and an input through the internal register (REGISTER) represents a case where all 30 bits of control data are set in advance.

According to the LINEOUT_N / P signal, the driving element drives the output logic of the horizontal line to active low or active high, and likewise activates the output logic of the vertical line according to the COLOUT_N / P signal. Drive to active low or active high.

The DRIVE_MTRX signal determines whether the output drive is 1x16 drive or 2x8 drive.

The POSITION0 to POSITION3 signals are for varying the duty ratio of the driving control device, which will be described later.

After the control signal for determining the overall operation of the drive control is input as described above, the input data R_DATA, G_DATA, B_DATA for turning on / off the LEDs of R, G, and B is 10 bits by the shift clock S_CRK. The input is input to the x3x16 shift register 21. In addition, control data to be stored in the internal memory of the drive control device is also input through the shift register 21.

The shift register 21 may be set to shift registers of 1x3x16, 2x3x16, 4x3x16, 6x3x16, 8x3x16, and 10x3x16 bits in accordance with the control data. In addition, the input method can be converted in series and in parallel by the control data. In case of serial, all R, G, B data is input through R input terminal, and G, B input terminal is not used. Therefore, in this case, the number of input terminals (input pins) can be reduced.

In addition, the input data of the shift register 21 can be selected from 1 bit up to 10 bits. That is, data of 1, 2, 4, 6, 8, 10 bits can be selected according to the control data value stored in the control data memory 26. Therefore, by appropriately changing and inputting control data, only LED on / off driving is required to display only characters, and signals up to 10 bits (1024 gray scales) can be driven to display high quality video signals. Can be.

The data input through the shift register 21 are stored in the video data memory 26 and the control data memory 27, which are internal memories, in accordance with control signals VD / CRTL and LATCH.

Here, the control signal VD / CTRL is a signal for selecting the video data memory 26 and the control data memory 27, and LATCH is a signal for writing data to the memory.

The video data memory 26 is a memory in which 30x16x16 bits of data for displaying an image on an LED is stored. Preferably, the video data memory 26 uses dualport RAM in which data read / write is executed independently.

On the other hand, the control data memory 27 is a memory in which 30-bit control data for determining the operation mode of the drive control device is stored.

The memory write address generator 24 generates a data write address for the video data memory 26 according to the address signals A0 to A3, and writes the data write address to the control signal VD / CRTL according to the generated address. The data is stored in the selected memory.

The data buffer 28 buffers the data stored in the video data memory 26 to be suitable for 1x16 driving or 2x8 driving.

The pulse width modulation (PWM) counter 29 performs pulse width modulation control on the data output from the data buffer 28 in accordance with the clock of the gradation clock generator 40 described later.

The gradation clock generator 40 is a circuit for generating a clock for driving the PWM counter 29 and includes a gradation clock generator 41, a gradation clock divider 42, and a gradation clock selector 43. The gray clock generator 40 selects an appropriate basic clock according to the clock of the self-oscillator and the external clock G_CLK input to the control signal buffer 22. The gradation clock generator 40 may increase or decrease the clock of the PWM counter 29 in multiples of 5 MHz to 80 MHz. Since the overall brightness of the LED panel 20 can be changed by such a clock change, the brightness of the LED panel can be easily adjusted by changing only the control data.

The PWM amplitude controller 50 uses the 10-bit input data stored in the video data memory 26 to separate the 8-bit image data and the 2-bit luminance data and input the same to the PWM counter 29. That is, the upper two bits of MSB are used to express the difference in brightness. Therefore, the lower image signal shows the same value as the data value, but the 256 or more image signal is displayed with more emphasis on the brightness. In other words, by using the PWM amplitude controller 50 in the second video mode, luminance correction can be simplified with only 10-bit image data, which is gamma correction generally used in image processing.

The output of the PWM counter 29 is applied to the LED dot matrix panel 20 through the output enable circuit 30 and the 16 dot x 3 color LED driving element 31, so that vertical line driving for the LED is executed.

At the same time, the memory read address generator 25 generates a memory read address in accordance with the 30-bit control data of the control memory. At this time, the memory read address is automatically generated in accordance with the control signal LOAD.

The memory read address is decoded by the display line address decoder 32 and applied to the LED dot matrix panel 20 through the 16-line driving element 33, so that the horizontal line driving for the LED is executed.

At this time, in order to solve the problem that an afterimage occurs due to the horizontal line driving, the output enable circuit 30 turns on the vertical line driving data by using the output enable signal OUT_EN at the time when the address is changed. control the turn on time appropriately. In addition, the watchdog timer 44 is for turning off the output of the driving element when the basic clock and other important signals for operating the PWM counter are not input.

Next, the duty ratio variable function of the drive control device will be described.

The number of driving control devices is determined according to the duty ratio. When the duty ratio is 1/16 in a 16x16 dot matrix, one driving control device scans the horizontal line. When the duty ratio is 1/8, two driving is performed. The control device is applied, i.e., if the duty ratio is 1/8, one drive control device is responsible for displaying the upper 8 lines, and the other displays the lower 8 lines. Similarly, when the duty ratio is 1/4, four driving control devices are applied to display four lines each. When 16 drive control devices are applied and display one line each, the drive control device operates in the same manner as the static drive.

As shown in Fig. 3, the POSITION0 to POSITION3 signals and duty mask data (4 bits are used here) of the control data are input to the memory read address generator 25, and each drive control is performed in accordance with the LOAD signal. The read address for the device is determined. The determined address is input to the display line address decoder 32 and decoded to drive the corresponding line of the panel 20.

As described above, the read line corresponding to each driving control device is automatically determined by using the duty mask data of the POSITION0 to POSITION3 signals and the control data, thereby driving the horizontal line of the panel according to the duty ratio. Therefore, the duty ratio can be freely changed in one chip.

Next, the overall operation of the LED driving control apparatus according to the embodiment of the present invention described above.

First, signals for determining an operation method of the driving control apparatus are input to the external input mode selector 23, input data is stored in the shift register 21, and various control signals are input to the control signal buffer 22. Then, control data is input to the control data memory 27 to set the duty ratio of the drive control device and the like.

That is, by the signal input to the external input mode selector 23 and the control data input to the control data memory 27, various operations for driving are selected and set.

Next, image data is input and stored in the video data memory 26 and input to the PWM amplitude controller 50 through the data buffer 28. The PWM amplitude controller 50 separates the input 10-bit data into 8-bit image data and 2-bit luminance data and inputs it to the PWM counter 29. The PWM counter 29 is provided by the gradation clock generator 40. The PWM clock is appropriately divided using the generated clock to perform PWM control on the input data.

Next, the vertical line driving to the panel 20 is executed using the output of the PWM counter 29, and the horizontal line driving is also performed by the display line address decoder 32 at the same time. To display the image.

LED driving control device according to the present invention is preferably manufactured by ASIC. As described above, the LED driving control device of the present invention made of the ASIC can be easily mounted on the LED display module, which is a basic unit of the display board, and can provide a standardized control method to the LED display board for displaying an image.

As described above, in the LED drive control device of the present invention, by using the PWM amplitude controller, there is an effect that the brightness can be simply adjusted by only 10-bit image data without using a separate luminance correction circuit.

In addition, the LED drive control apparatus of the present invention can select the clock for the internal PWM circuit by using the gray scale clock generator, and thus, the overall brightness of the LED panel can be easily adjusted by changing the clock.

Although the present invention has been described with reference to the above-described preferred embodiments and the accompanying drawings, different embodiments may be constructed within the spirit and scope of the present invention. Accordingly, the scope of the present invention is defined by the appended claims, and should be construed as not limited to the specific embodiments described herein.

Claims (1)

A light emitting diode driving control apparatus for displaying an image on a light emitting diode dot matrix panel, A shift register for receiving and storing input data for displaying and controlling an image on the dot matrix panel; A video data memory for receiving and storing image data to be displayed on the dot matrix panel from the shift register; A control data memory for receiving and storing control data for determining an operation mode of the driving control apparatus through the shift register; A PWM counter for performing pulse width modulation control on the video data of the video data memory, A gradation clock generator for generating a clock for driving the PWM counter; And a PWM amplitude controller for separating the data stored in the video data memory into image data and luminance data and inputting the same to the PWM counter. The gradation clock generator may increase or decrease the clock of the PWM counter in multiples of 5 MHz to 80 MHz, and 10-bit input data is stored in the video data memory, and the PWM amplitude controller converts the input data into 8-bit image data. And dividing the data into 2-bit luminance data and inputting the same to the PWM counter.