KR200331154Y1 - Semiconductor memory - Google Patents

Abstract

The present invention relates to a semiconductor memory device receiving a row address and a column address using the same address buffer. When the number of row addresses and column addresses input is different, N + K row addresses are input using a RASE signal. When + K address buffers are enabled and N column addresses are input, the present invention relates to a semiconductor memory device capable of reducing unnecessary power consumption by having an address buffer structure in which only N address buffers are enabled.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device receiving a row address and a column address using the same address buffer. In particular, when the number of row addresses and column addresses to be input is different, the unnecessary address buffer is disabled to reduce the current caused by unnecessary operation. The present invention relates to a semiconductor memory device having an input address buffer.

1 is a block diagram of a conventional semiconductor memory device.

Hereinafter, the structure and operation of a semiconductor memory device including a conventional address buffer will be described with reference to the drawings.

A conventional semiconductor memory device receives an input address buffer 10 consisting of N + K inverters for receiving N + K addresses and outputs a coded signal and a column address strobe (CASB) signal to receive a column address latch enabie. A column address latch control block 20 for outputting a signal), a row address latch control block 30 for receiving a Row Address Strobe (RASB) signal and outputting a Row Address Latch Enabie (RALE) signal, and the coded row Inputs the address (N + K), the coded column address (N), the RALE (Row Address Latch Ennabie) signal and the CALE (Column Address Latch Ennabie) signal, and then selects the row address selection signal and the column address selection signal from the memory array. The address multiplex 40 outputs to 50 is comprised.

The address multiplex 40 receives a column address latch enabie (CALE) signal and coded column addresses (N) and outputs a column address selection signal and a column address latch block 41 and a row address latch enabie (RALE). And a row address latch block 42 for receiving a signal and coded row addresses (N + K) and outputting a row address selection signal.

The operation of the conventional semiconductor memory device will be described with reference to FIG. 3.

The input address buffer 10 is enabled to receive N + K address signals and output N + K coded address signals to the address multiplex 40.

At time tR1, a RASB (Row Address Strobe) signal is applied, and the row address latch control block 30 outputs a RALE (Row Address Latch Enabie) signal to the row address latch block 42. The row address latch block 42 receiving the N + K coded address signals and the RALE (Row Address Latch Enabie) signal outputs the N + K row address selection signals to select the row addresses of the memory array 50. do.

After outputting the N + K row address selection signals, the input address buffer 10 is disabled.

The input address buffer 10 is then enabled to accept N address signals and output N coded address signals to the address multiplex 40.

At time tC1, a CASB (ColumnRow Address Strobe) signal is applied, and the column address latch control block 20 outputs a CALE (Column Address Latch Enabie) signal to the column address latch block 41. The column address latch block 41 receiving the N coded address signals and the CALE (Column Address Latch Enabie) signal outputs N column address selection signals to select the column addresses of the memory array 50.

However, in the conventional semiconductor memory device, when the number of row addresses and column addresses are different, that is, when K ≠ 0, when only N column addresses are selected after enabling all N + K inverters in the input address buffer, the input address buffer is selected. There is a problem of increasing power consumption by operating the K inverters in the inside unnecessarily.

Accordingly, an object of the present invention is to configure a semiconductor memory device including an input address buffer which can be enabled only when there is an input address signal, thereby reducing unnecessary power consumption.

A semiconductor memory device receiving N + K row addresses and N column addresses using the same address buffer according to the present invention for achieving the above object has N + K addresses when the N + K row addresses are input. When the buffer is enabled and the N column addresses are input, only the N address buffers are configured with the input address buffer having the structure enabled.

Hereinafter, a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a conventional semiconductor memory device

2 is a block diagram of a semiconductor memory device according to the present invention.

3 is an operation timing diagram of FIGS. 1 and 2.

Explanation of symbols on the main parts of the drawings

10, 100. Input address buffer section 20, 200. Column address latch control block

30, 300. Row address latch control block 40, 400. Address multiplex

41, 401. column address latch block 42, 402. row address latch block

50, 500. Memory Array

2 is a block diagram of a semiconductor memory device according to the present invention.

The semiconductor memory device according to the present invention receives an input address buffer 100 for inputting N + K addresses and outputs a coded signal and a column address strobe (CASB) signal to output a column address latch enabie (CALE) signal. A column address latch control block 200, a row address latch control block 300 for receiving a Row Address Strobe (RASB) signal and outputting a Row Address Latch Enabie (RALE) signal, and the coded N + K address signals And an address multiplex 400 that receives a column address latch enabie (CALE) signal and outputs a row address selection signal and a column address selection signal to the memory array 500.

The input address buffer 100 includes N inverters 101 that receive only an address and K NAND gates 102 that receive an address signal and a RALE (Row Address Latch Enabie) signal.

The address multiplex 400 receives a column address latch enabie (CALE) signal and coded column addresses (N) and outputs a column address selection signal and a column address latch block 401 and a row address latch enabie (RALE). And a row address latch block 402 for receiving a signal and coded row addresses (N + K) and outputting a row address selection signal.

The operation of the semiconductor memory device according to the present invention will be described with reference to FIG. 3.

After the N + K address signals are input to the input address buffer 100 and a RASB (Row Address Strobe) signal is applied at time tR1, the row address latch control block 30 outputs a RALE (Row Address Latch Enabie) signal. .

The N inverters 101 of the input address buffer 100 output N coded address signals, and the K NAND gates 102 receive the RALE (Row Address Latch Enabie) signal and enable the K coded addresses. Outputs

The row address latch block 402 receiving the coded address signal and the RALE (Row Address Latch Enabie) signal outputs N + K row address selection signals to select a row address of the memory array 500.

After outputting the N + K row address selection signals, the input address buffer 100 is disabled.

After the N address signals are input to the address buffer 100, the N inverters 101 output N coded address signals, and the K NAND gates 102 are disabled because of the RALE (Row Address Latch Enabie) signal. Maintain state.

When a CALE (Column Address Strobe) signal is applied to the time time tC1, the column address latch control block 200 outputs a CALE (Column Address Latch Enabie) signal to the column address latch block 401. The column address latch block 401 receiving the N coded address signals and the CALE (Column Address Latch Enabie) signal outputs N column address selection signals to select the column addresses of the memory array 500.

Therefore, the present invention has an advantage of reducing unnecessary power consumption by disabling unnecessary address buffers.

Claims (2)

In a semiconductor memory device receiving N + K row addresses and N column addresses using the same address buffer, An input address buffer having a structure in which N + K address buffers are enabled when the N + K row addresses are input, and only N address buffers are enabled when the N column addresses are input; And the input address buffer disables an unnecessary address buffer by using a low address strobe enable signal. In a semiconductor memory device receiving N + K row addresses and N column addresses using the same address buffer, An input address buffer having a structure in which N + K address buffers are enabled when the N + K row addresses are input, and only N address buffers are enabled when the N column addresses are input; And the input address buffer comprises N inverters that receive only an address and K NAND gates that receive an address signal and a RASE (Row Address Strobe Enable) signal.