KR100284239B1 - Address decode circuit - Google Patents

Abstract

SUMMARY OF THE INVENTION An object of the present invention is to provide an address decode circuit capable of optimizing output timing of a decoded result and achieving both a reduction in decoding operation time and prevention of malfunction.

(Solution means) The present invention adopts a configuration for activating a signal for selecting a word line in response to a decoded result of making the word line unselected.

Description

Address decode circuit

The present invention relates to the speed-up of an address decode circuit, and is particularly suitable for use in a row decoder of a synchronous high speed memory.

In the memory device, the row decoder in the address decode circuit selects one of the plurality of word lines of the memory array from the input address signal to activate the memory cell. For this reason, since the output of the row decoder determines the timing of activation of the memory cell, which also affects the read timing of data in the sense amplifier, speeding up the address decoding circuit is very important for speeding up memory access.

4 shows a conventional address decode circuit, and FIG. 5 shows its operation waveform.

This address decoding circuit decodes the 7-bit row address signal to select the word line 107 of the 128-row memory array 100. The address decode circuit is composed of a predecode section 101, a main decode section 102, and a word line buffer section 103. The predecode unit 101 decodes an address by 2 bits, 2 bits, and 3 bits by using an AND gate, and outputs 4 bits, 4 bits, and 8 bits of predecode signals, respectively. In the main decode section 102, a predecode signal corresponding to the address of the word line 106 is input to the AND gate 104 provided for each word line 106, and the decode result is output. In this manner, the decoding is performed in two stages, so that decoding is performed without using a multi-input CMOS gate to achieve high speed.

In the decoded word line buffer section 103, the word line 106 selected by the main decode section 102 is activated by the input of the clock signal. The word line buffer section 103 activates the word line 106 in synchronization with the clock signal by the AND gate 105 which receives the decoding result of the main decoding section 102 and the clock signal. This is necessary because the memory cell 107 is not activated at the time of precharging the bit line of 100. In such a word line buffer section 103, in order to prevent grit from occurring in the word line 106, as shown in the operation waveform of Fig. 5, the input timing of the clock signal must be after the decoding is completed.

In such an address decode circuit, activation of the word line 106 must be made after the selection / non-selection of the decode output is confirmed. For this reason, in order to shorten the decoding time, it is necessary to speed up both the rise and fall of the decode output, and the restriction for the increase in speed is increased.

As a solution to this, there is a method of using precharge type logic in the decoding unit 112 as shown in FIG. In the precharge type logic, only data transitions in one direction occur when data is determined. Therefore, speeding up by adjusting the size ratio of the P-type MOSFET (field effect transistor) and the N-type MOSFET is effective.

In the circuit configuration shown in Fig. 6, the address signal is clocked by taking the AND of the two sets of complementary input addresses in the address input section 111 and the first clock signal, and each word line (in the decode section 112). The address signal corresponding to the address of the word line 116 is input to the decode circuit 114 of 116, respectively. The decode circuit 114 is composed of an N-type MOSFET 117 and a pre-charged P-type MOSFET 118 of the number of bit widths of the address, and the source terminal of the N-type MOSFET 117 is connected to the ground level. The drain terminal is commonly connected to the output terminal 119, and an address signal clocked at each gate terminal is input in accordance with the address of the word line 116. In the P-type MOSFET 118, the source terminal is connected to the power supply level, the drain terminal is connected to the output terminal 119, and the output terminal 119 is precharged to the high level by a precharge signal applied to the gate terminal. The word line buffer unit 113 outputs a signal for selecting the word line 116 by taking the AND of the output line 119 of the decode unit 112 and the second clock signal.

When the P-type MOSFET 118 of the decode section 112 is turned on by the precharge signal, all of the address inputs to the decode section 112 are set to the low level by the first clock signal of the address input section 111. The N-type MOSFETs 117 of the decode section 112 are all on, and the output of the decode circuit 114 is precharged to a high level by the P-type MOSFET 118. At this time, the second clock signal of the word line buffer unit 113 is at a low level, and the word line 116 is not activated. When the P-type MOSFET 118 is turned on by the precharge signal and the first clock signal becomes high level, and the address signal is input to the decoding unit 112, the decoding circuit corresponding to the word line 116 indicated by the address. At least one of the N-type MOSFETs 117 other than 114 is turned on, and the output signal transitions to the low level. At this time, the word line 116 is not activated because the decode output is at a low level in the next word line buffer unit 113 even when the second clock signal is input. Only the output of the decode circuit 114 of the word line 116 indicated by the address signal is maintained at the potential (high level) at the time of precharging, and the next word line buffer section 113 The word line 116 is driven by the input.

In the address decoding circuit employing such a precharge method, since the direction of data transition of the decoding unit 112 (in the example shown in FIG. 6) is constant, the decoding circuit 114 has a word line 116. It is only necessary to speed up only the direction () from the high level to the low level in the example shown in FIG. 6. Therefore, the decode section 112 becomes easy to speed up, and a method such as adjusting the size ratio of the P-type MOSFET 118 and the N-type MOSFET 117 of each gate is effective.

However, since the input timing of the second clock signal of the word line buffer unit 113 must be detected by the decode circuit 114 that the word line 116 is in an unselected state, similarly to the above-described conventional example. The timing must be adjusted later than the decode signal output.

For example, when the second clock signal for activating the word line 116 is later than the output of the decode circuit 114, grit occurs in the word line 116, which causes malfunction. For this reason, sufficient timing margin is required for the second clock signal for activating the word line 116, which causes a delay in the decoding time. Furthermore, in this example, the first clock signal is ANDed from the necessity of clocking the input to the address decode circuit also in the address input section 111. In this part, the timing of the address input and the first clock signal is relaxed. It is necessary. Therefore, there is a possibility that the timing margin necessary for these two positions can increase the decoding time.

As described above, in the conventional synchronous address decode circuit for outputting a signal for selectively activating a word line in synchronization with a clock signal, the decoding result of the address signal is determined in either the predecode method or the precharge method. Since it is necessary to input the clock signal after completion, a timing margin is provided between the determination of the decode result and the input of the clock signal. However, if the timing margin is large, the output of the decode result is slowed, and the operation speed of the address decode circuit is slowed. On the other hand, if the timing margin is too fast, there is a fear that glitches occur in the word lines and malfunction. From these points, it is extremely difficult to optimally set the timing of both without being influenced by various factors of the circuit related to signal delay.

Therefore, the present invention has been made in view of the above, and an object thereof is to provide an address decoding circuit capable of optimizing output timing of a decoded result, and shortening the decode operation time and preventing the malfunction. have.

1 is a diagram showing the configuration of an address decode circuit according to an embodiment of the invention described in claim 1;

2 is a diagram showing the configuration of an address decode circuit according to one embodiment of the invention as set forth in claim 1 or 2;

3 is a view showing an operating waveform of the circuit shown in FIG. 2;

4 is a diagram showing the configuration of a conventional address decode circuit;

5 is a view showing an operating waveform of the circuit shown in FIG. 4;

6 is a diagram showing another configuration of the conventional address decoding circuit.

<Explanation of symbols for main parts of drawing>

1 --- predecode section, 2 --- main decode section,

3 --- word line buffer, 4 --- memory array,

5 --- memory cell, 6 --- word line,

7, 23 --- decode circuit, 8, 24 --- N-channel FET,

9, 25 --- P-channel FET, 10, 26 --- output terminal,

11 --- buffer circuit, 12 --- inverted gate,

13 --- AND gate, 21 --- address input,

22 --- Decode Section.

In order to achieve the above object, the invention described in claim 1 is a synchronous address decode circuit in which an n-bit address signal is decoded so that 2 ⁿ output selection signals are selectively selected. A decode circuit that selects one decode signal from the 2 ⁿ decode signals set in the preselected state and maintains the selected state, and transitions a decode signal other than the selected decode signal from the selected state to the non-selected state; 2 after the ⁿ number of decode signal receives the decoded signal is selected, the state holding the other decode signal detecting that a transition from the selected state to the unselected state, the 2 ⁿ of the output selection corresponding to 2 ⁿ of the decode signal sinhojung selected state A buffer circuit for selectively selecting an output selection signal corresponding to a decode signal of All.

In the address decoding circuit according to claim 1, the decoding circuit includes an address input unit for inputting an address signal and an inverted address signal generated by inverting the address signal in synchronization with a clock signal, and a decode signal. A decode unit comprising a FET for precharging an output line to be output in a selected state, and a FET for receiving an address signal or an inverted address signal from the address input unit and discharging the output line in a non-selected state, wherein the buffer unit is configured to And an inverting circuit which receives and inverts a signal, and a gate buffer which generates an output selection signal by taking a logical product of the signal of the output line and the inverting signal of another inverting circuit except the inverting circuit which receives and inverts the signal of the output line. do.

Embodiment of the Invention

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described with reference to drawings.

1 is a diagram showing the configuration of an address decode circuit according to one embodiment of the invention described in claim 1.

In Fig. 1, the address decoding circuit of this embodiment alternatively selects 128 output selection signals for decoding 2 ^n, for example, 128 word lines by decoding an address signal of n bits, for example, 7 bits, in synchronization with a clock signal. In the selection state, a 7-bit address signal is received to select one decode signal among the 128 decoded signals set in the preselection state to maintain the selection state, and other decode signals other than the selected decode signal are not selected from the selection state. The decode section 1 and main decode section 2 serving as a decode circuit for transition to the decode circuit, and a decode signal different from the decode signal in which the decode signal is retained in the selected state by receiving 128 decode signals of the decode circuit are selected from the deselected state. After detecting that the signal has been transitioned to, output from the 128 output selection signals corresponding to the 128 decode signals corresponding to the decode signal in the selected state A selection signal is configured equipped with the alternative word line buffer section 3, which is a buffer circuit for a selected state.

The predecode unit 1 decodes the 7-bit address by 2 bits, 2 bits, and 3 bits, respectively, and takes a logical product of the predecode result and the clock signal to clock the predecode signal of the predecode result. . This predecode signal is set to a low level by the clock signal irrespective of the address signal, and when the clock signal is input, it is output as a decode result according to the address signal.

The main decode unit 2 is composed of 128 decode circuits 7 corresponding to 128 word lines 6 for selecting the memory cells 5 arranged in a row of the memory array 4. The decode circuit 7 is composed of a number obtained by dividing an address signal in order to predecode the address signal, that is, three N-type MOSFETs 8 and one P-type MOSFET 9 for precharging. In the FET 8, the source terminal is connected to the ground level, the drain terminal is commonly connected to the output terminal 10, and the predecode result corresponding to the address of the word line 6 is input to each gate terminal, and the output terminal Configure wired-OR logic for (10). In the FET 9, the source terminal is connected to the power supply level, the drain terminal is connected to the output terminal 10, and the output terminal 10 of the main decode unit 2 is freed by a precharge signal applied to the gate terminal. Occupy.

The word line buffer unit 3 is composed of 128 buffer circuits 11 that select or deselect the word line 6 in correspondence with each word line 6. The buffer circuit 11 has a decoded signal output from the output terminal 10 of the decode circuit 7 corresponding to the address of the word line 6 and an address that is one bit different from the address of the word line 6. The decode signal of the corresponding decode circuit 7 is input, and the latter decode signal is inverted by the inversion gate 12, and this inverted signal and the latter decode signal are logic by the AND gate 13. The product is taken, and the result is applied to the corresponding word line 6 as an output selection signal for selecting and controlling the word line 6, respectively.

In such a configuration, when the FET 9 of the main decode section 2 is turned on by the precharge signal, and the clock signals in the predecode section 1 set all predecode outputs to a low level, the main decode section ( The FETs 8 in 2) are all turned off, and all of the decode signals are fixed at high level. The inverted signal generated by inverting the decoded signal having an address of one bit different from that of the word line 6 by the inverted gate 12 is input to the AND gate 13 of the buffer circuit 11. Since the input is at a low level, the word line 6 is not activated and is in an unselected state.

When the FET 9 is turned off by the precharge signal and the predecode signal is input to the main decode unit 2, 127 words other than the decode circuit 7 corresponding to the word line 6 indicated by the address signal are indicated. At least one of the FETs 8 of the line decode circuit 7 is turned on so that the decode signal output transitions from a high level to a low level. At this time, since the low level is input to the AND gate 13 of the buffer circuit 11 from the decode circuit 7 corresponding to the address of the word line 6, the output of the AND gate 13 remains low level. The word line 6 is not activated and the non-selected state is maintained.

On the other hand, since all of the FETs 9 of the decode circuit 7 corresponding to the word line 6 indicated by the address signal are turned off, the output terminal 10 of the decode circuit 7 has a high level at the time of precharging. The potential is maintained. This high-level potential is applied to one input of the AND gate 13 of the buffer circuit 11, and the decode signal output of the word line decode circuit 7 which is one bit different always transitions to a low level. The high level of the signal is applied to the other input of the AND gate 13 so that the output of the AND gate 13 transitions from the low level to the high level, and the word line 6 is activated from the low level to the high level and is non- The selection state is changed from the selection state.

In such an address decoding circuit, a clock signal for activating the word line 6 after decoding is unnecessary. Activation of the word line 6 is determined at the timing when the decoding circuit 7 of the address signal of another bit is detected unselected. Since this timing is delayed by one stage of the gate of the inverted gate 12 than the decode signal output of the decode circuit 7 corresponding to one bit other address, the timing is never too early when the word line 6 is unselected. The selection timing of the word line 6 is compensated.

This eliminates the need to adjust and input the timing of the activation clock signal of the word line at the timing of the decode signal output as in the conventional example, and also eliminates the need for the timing of the clock signal. As a result, the selection timing of the word lines is optimized, and the time from the input of the address signal to the selection of the word lines, i.e., the decode operation time, can be shortened compared to the conventional one, and glitches are prevented from occurring in the word lines, thereby preventing malfunction. can do.

Further, since the main decode unit 2 adopts a precharge circuit configuration and sets the decode signal output of the decode circuit 7 to a preselected state to detect non-selection of the decode signal, the decode circuit 7 Since the output transition direction of the constant becomes constant, it is easy to speed up the output of a decode signal, and the speed up by adjusting the transistor size ratio of the FETs 8 and 9 of the decode circuit 7 is effective.

FIG. 2 is a diagram showing the configuration of the address decode circuit according to the first embodiment of the invention as set forth in claim 1, and FIG. 3 is an operational waveform diagram of the circuit shown in FIG. In FIG. 2, the same code | symbol as FIG. 1 has the same function, and the description is abbreviate | omitted.

In Fig. 2, the address decoding circuit of this embodiment includes an address input section 21 for receiving an address signal, a decode section 22 for decoding the address input applied from the address input section 21, and the one shown in Fig. 1. The word line buffer section 3 similar to the word line buffer section 3 is provided.

The address input section 21 generates two complementary signals (address signals, inverted address signals) of each address signal, and takes a logical product of the generated address signal and a clock signal to generate a clocked address signal. This address signal is set to a low level in an initial state, and when a clock signal is input, two sets of complementary address signals in accordance with the input address signal are generated.

The decode section 22 includes 128 decode circuits 23 corresponding to the respective word lines 6, and the decode circuit 23 has an N type of bit width (7 bits in this embodiment) of the address signal. It consists of MOSFET 24 and P-type MOSFET 25 for precharge. The source terminal of the FET 24 is connected to the ground level, the drain terminal is commonly connected to the output terminal 26, and the address signal from the address input portion 21 corresponding to the address of the word line 6 is connected to each gate terminal. Is input, and the wired ora logic is constituted with respect to the output terminal 26. The FET 25 has a source terminal connected to a power supply level, a drain terminal connected to an output terminal 26, and the output terminal 26 of the main decode unit 22 is pre-set by a precharge signal applied to the gate terminal. Occupy.

In such a configuration, when the FET 25 of the main decode section 22 is turned on by the precharge signal, and all complementary address signals output from the address input section 21 by the clock signal are set to a low level, decode is performed. The FETs 24 of the unit 22 are all turned off, and the decode signal outputs are all fixed at high level. As a result, the decoded signal output of the decode circuit 23 at an address different from the address of the word line 6 to the AND gate 13 constituting the word line buffer unit 3 is output to the inverted gate 12. The inverted signal generated by inversion is inputted, and the word line 6 is not activated but is in an unselected state by inputting the low level inverted signal.

Next, when the FET 25 is turned off by the precharge signal and the address signal is input to the decoder 22, the decode circuit 23 other than the decode circuit 23 of the word line 6 indicated by the address signal. At least one of the FETs 24 turns on so that the decode signal output transitions from the high level to the low level. As a result, a low level signal is input to the AND gate 13 of the word line buffer unit 3 from the decode circuit 22 corresponding to the address of the word line 6, so that the output of the AND gate 13 is output. Is at the low level, and the word line 6 is not activated and the unselected state is maintained.

On the other hand, none of the FETs 24 of the decode circuit 23 of the word line 6 indicated by the address signal is turned on, and the potential (high level) at the time of precharging is held in the output terminal 26. For this reason, this high level potential is input to one input terminal of the AND gate 13 of the word line buffer unit 3, and the decode signal output of the other word line decode circuit 23 by one bit is always brought to the low level. Since the high level signal of the inversion signal is inputted to the other input terminal of the AND gate 13, the output of the AND gate 13 transitions from the low level to the high level, so that the word line 6 Is activated from the low level to the high level and becomes a selection state.

In this embodiment, as in the above-described embodiment, the clock signal for activating the word line 6 is not necessary after decoding, and the activation of the word line 6 is unselected by the decoding circuit 23 of the address signal having a different bit. Since it is automatically determined at the timing at which the signal is detected, it is not necessary to consider the activation timing margin of the word line. In addition, since the decode circuit 22 is constituted by a precharge circuit, only the non-selection of the word line 6 needs to be made high speed as in the previous embodiment, so that the high speed can be easily realized. In addition, since the decoding unit 22 is constituted by a wired OR circuit, the multi-input gate can be configured to decode pre-decode and decode in one stage, compared to the structure in which the decoding is performed by a directly connected transistor. Time can be even faster.

As described above, in each of the above-described embodiments, it is possible to form a precharge type circuit which makes it easy to speed up the transition of the data line to obtain the decoded result in a constant direction, and further inputs the clock signal to the word line buffer unit 3. There is no need to consider timing margins. Since the activation timing of the word line 6 is generated by the decoding section, it also plays a role as a timing compensation circuit. Furthermore, since the decode section can be constituted by a wired ora circuit, multi-input gates are possible, and the number of gate stages of the decode circuit can be reduced. As a result, address decoding can be speeded up and the access time of the memory can be reduced.

Further, in the above embodiment, an address signal corresponding to a signal indicating non-selection of the word line 6 input to the inverting gate 12 of each buffer circuit 11 of the word line buffer unit 3, The address signal of the decode signal output applied to the other input of the AND gate 13 to which this signal is input is set to an address different from one bit, but using another address signal indicating non-selection even if the address is not one bit different. For example, the decode circuit 7 which detects the non-selection at the latest is made by transitioning the output terminals 10 and 26 of the decode circuits 7 and 23 from the high level to the low level with one FET 8, 24 which is warm. The decode signal output of 23 may be used. However, when an address different from one bit is used as in the above embodiment, the wiring for inputting the decoded signal outputs of the adjacent decode circuits 7 and 23 to the inverting gate 12 of the word line buffer 3 is shortened. The layout can be easily performed, and wiring can be performed in a small wiring area.

As described above, according to the present invention, since the structure which receives the decoded result of making the word line unselected and activates the signal which selects a word line is adopted, the synchronization signal which determines the timing which outputs a decoded result becomes unnecessary, and decodes. The output timing of the result can be optimized, and the decoding time can be shortened and the malfunction can be prevented.

Claims (2)

A synchronous address decode circuit for decoding an n-bit address signal to selectively select 2 ⁿ output selection signals, A decode circuit that receives an n-bit address signal and selects one decode signal from 2 ⁿ decode signals set in a preselected state to maintain the selected state, and transitions a decode signal other than the selected decode signal from the selected state to the non-selected state. Wow, After the 2 ⁿ of the decode signal is different from the decoding signal received and decoded signal is selected status retention of the decoding circuit is detected that a transition from the selected state to the unselected state, the 2 ⁿ outputs corresponding to the 2 ⁿ of the decode signal An address decoding circuit comprising a buffer circuit for selectively selecting an output selection signal corresponding to a decode signal in a selection state among the selection signals. The FET of claim 1, wherein the decode circuit pre-charges an address input unit for inputting an address signal and an inverted address signal generated by inverting the address signal in synchronization with a clock signal, and an output line for outputting the decode signal in a selected state. And a decoder configured to receive an address signal or an inverted address signal applied from the address input unit, and a FET configured to discharge the output line in an unselected state. The buffer unit performs a logical product of an inversion circuit that receives the signal of the output line and inverts the signal of the output line and an inversion signal of another inversion circuit except for the inversion circuit that receives and inverts the signal of the output line to generate an output selection signal. An address decode circuit comprising a buffer.