KR20030094629A - Clock enable buffer - Google Patents

Abstract

PURPOSE: A clock enable buffer is provided to certainly prevent the mis-operation during the initialization of the clock enable buffer by not accepting any command and address when the clock enable signal is 'L' state. CONSTITUTION: A clock enable buffer includes a clock enable buffering unit(100) and an initialization unit(210). The clock enable buffering unit(100) generates an output signal by comparing the size of the clock enable signal inputted to the second NMOS transistor gate with that of the reference voltage inputted to the first NMOS transistor gate in response to the input signal. And, the initialization unit(210) is placed between the clock enable buffering unit(100) and the ground voltage so as to operate the clock enable buffering unit(100) when the level of the reference voltage becomes larger than the threshold voltage by using the reference voltage as a control signal of the gate.

Description

Clock Enable Buffer

The present invention relates to a semiconductor memory device, and more particularly, to a clock enable buffer for initializing an internal power supply potential in a semiconductor memory device.

When the dynamic buffer is used as the input buffer in the semiconductor memory device, if the actual reference voltage generated by the external power potential is lower than the target reference voltage, a malfunction occurs when the clock enable buffer is initialized.

1A and 1B are waveform diagrams relating to initialization specifications of a general semiconductor memory device.

In order for the external power voltage to come in, the VDD voltage used inside the DRAM comes first, followed by the VDDQ voltage for the DQ used at the input / output buffer side at the same time or slightly later than the VDD voltage, and the reference voltage VREF comes later than the VDDQ voltage. .

Looking at the initialization specification in more detail with reference to Fig. 1B, the LVCMOS (a CMOS transistor capable of operating at a low voltage such as 3.3V) is set to the "L" state even after VDD is raised, and the clock CLK, The command CMD, the address ADDRESS and the reference voltage VREF are DON'T CARE. That is, the clock may come in, the reference voltage VREF may be in the "L" state, and any address / command may come in. At this time, if the reference voltage VREF is higher than the threshold voltage Vth of the NMOS transistor, the semiconductor memory device recognizes the power down and there is no failure, but the reference voltage VREF is lower than the threshold voltage Vth. If so, a fail will occur.

2 is a clock enable buffer circuit diagram according to the prior art.

The input signal EN may be a combination of a power-up signal and another control signal, and when the buffer is turned on by the input signal EN, both the reference voltage VREF and the clock enable signal CKE may have threshold voltages. Below Vth), the pull-down transistors NM2 and NM3 are all blocked and the aa node is likely to be in the "H" state, and when the clock is turned on as if the clock enable signal (CKE) was recognized as the "L" state. The device is in a power down state.

However, since the PMOS transistors PM1, PM2, PM3, and PM4 are also almost turned off, the node aa is almost floating, and therefore, there is a possibility of switching to the "L" state by noise. If it is switched to the "L" state, the clock enable signal is a result of being recognized as the "H" state, so the address / command buffers are enabled to accept the input.

In this case, unwanted commands and addresses are entered, causing a failure, and when all the commands are in the "L" state, the MRS setting (Mode register set) is executed to execute the column address strobe latency (CAS Latency). : CL), Burst Length (BL), Burst Type (BT), etc. can be set as desired or erased. That is, the flag signals of all the CL, BL, and BT in the semiconductor memory device may all be in the "L" state due to the illicit MRS.

3 is a simulation waveform diagram of a clock enable buffer according to the prior art.

In the clock enable buffer, the input signal EN is opened in the "H" state, and the clock enable signal CKE is VIL (VIL means a voltage range in which the input voltage is logically recognized as the "L" state.) When the reference voltage VREF comes in late, i.e. when the level of the reference voltage is low, the output signal out0 remains "H" so that the clock enable signal CKE is "H". This opens up the clock and all the buffers, causing a problem.

That is, in the initialization of the clock enable buffer, when the clock enable signal is in the "L" state, no commands and addresses should be accepted. When the reference voltage comes in late, the clock enable signal itself is in the "L" state. Instead of going into the power-down mode by recognizing the "H" state, all buffers, including the clock enable buffer, are enabled, causing an error.

In order to solve the above problems, an object of the present invention is to provide a clock enable buffer that can open a buffer after a reference voltage reaches a predetermined level or more at initialization.

1A and 1B are waveform diagrams relating to initialization specifications of a general semiconductor memory device;

2 is a clock enable buffer circuit diagram according to the prior art;

3 is a simulation waveform diagram of a clock enable buffer according to the prior art;

4 is a circuit diagram of a first embodiment of a clock enable buffer according to the present invention;

5 is a circuit diagram of a second embodiment of a clock enable buffer according to the present invention;

6 is a circuit diagram of a third embodiment of a clock enable buffer according to the present invention;

7A and 7B are simulated waveform diagrams of a clock enable buffer in accordance with the present invention.

<Explanation of symbols for the main parts of the drawings>

100: clock enable buffering unit

210, 220, 230: Initialization stabilizer

In order to achieve the above object, the clock enable buffer of the present invention compares a reference voltage input to a first NMOS transistor gate with a magnitude of a clock enable signal input to a second NMOS transistor gate in response to an input signal. Clock enable buffering means for generating an output signal; And an initialization stabilization means located between the clock enable buffering means and the ground voltage side so that the clock enable buffering means operates when the reference voltage is above a threshold voltage using the reference voltage as a control signal of a gate. It is characterized by including.

In addition, the clock enable buffer of the present invention generates an output signal by comparing the magnitude of the reference voltage input to the first NMOS transistor gate with the magnitude of the clock enable signal input to the second NMOS transistor gate in response to an input signal. Clock enable buffering means; And turning on the third NMOS transistor between the clock enable buffering means and the ground voltage side by using an output side power supply voltage as a gate control signal to enable the clock enable buffering means, and outputting the output side power supply voltage to a gate control signal. And an initialization stabilizing means for deactivating the clock enable buffering means by turning on a first PMOS transistor between an input side power supply voltage and an output terminal.

Preferably, the initialization stabilization means of the present invention detects whether the level of the output power supply voltage reaches between one and two times the threshold voltage of the NMOS transistor between the output side power supply voltage terminal and the third NMOS transistor. A plurality of buffers are connected in series so as to be used.

In addition, the clock enable buffer of the present invention includes an initialization stabilizing means for outputting by the control of the control signal when it is detected that the output side power supply voltage has reached a predetermined level; And a signal output from the initialization stabilization means as an input signal, and the magnitude of the reference voltage input to the first NMOS transistor gate and the clock enable signal input to the second NMOS transistor gate in response to the input signal. And clock enable buffering means for generating an output signal in comparison.

Preferably, the initialization stabilization means of the present invention is to use a plurality of buffers in series so as to detect whether the level of the output-side power supply voltage reaches 1 to 2 times the threshold voltage of the NMOS transistor. It features.

The present invention eliminates the initialization failure of the clock enable buffer by using an NMOS transistor connected in series with a buffer enable transistor of the prior art and whose gate is controlled by a reference voltage, or the reference voltage VREF itself is equal to the VDDQ voltage. Since the power is divided and output from the VSSQ voltage, the initialization fail is eliminated by detecting the VDDQ voltage level and opening the buffer.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

4 is a circuit diagram of a first embodiment of a clock enable buffer according to the present invention.

According to the first embodiment of the present invention, the reference voltage VREF input to the NMOS transistor NM2 and the clock enable signal CKE input to the NMOS transistor NM3 in response to the input signal EN are provided. The clock enable buffering unit 100 that compares the magnitude and generates the output signal out, and the reference voltage VREF is used as a control signal of the gate, and when the level of the reference voltage VREF becomes greater than or equal to the threshold voltage, the clock in The enable buffering unit 100 includes an initialization stabilizer 210 formed of an NMOS transistor NO located between the clock enable buffering unit 100 and the ground potential VSSI to operate.

The clock enable buffering unit 100 operates only when the level of the reference voltage is greater than or equal to the threshold voltage of the NMOS transistor N0. When the reference voltage is lower than the threshold voltage, the clock enable buffering unit 100 operates. As a result, the output terminal OUT is turned to the "L" state, and the power-down state is not established. Consequently, the initialization failure of the clock enable buffer does not occur.

5 is a circuit diagram of a second embodiment of a clock enable buffer according to the present invention.

According to the second exemplary embodiment of the present invention, the reference voltage VREF input to the NMOS transistor NM2 and the clock enable signal CKE input to the NMOS transistor NM3 in response to the input signal EN are provided. The clock enable buffering unit 100 which compares the magnitude and generates the output signal out, and the clock enable buffering unit 100 and the ground voltage VSSI using the output power supply voltage VDDQ as a gate control signal. Turn on the NMOS transistor N1 to enable the clock enable buffering unit 100, and use the output side power supply voltage VDDQ as a gate control signal, and the PMOS transistor between the input side power supply voltage VDDI and the output terminal. It consists of an initialization stabilizer 220 that deactivates the clock enable buffering unit 100 by turning on P1. Here, when the output side power supply voltage VDDQ is used as the gate control signal of the NMOS transistor N1, it is possible to detect whether the VDDQ voltage reaches a predetermined level (for example, 1 to 2 times the threshold voltage). Since the clock enable buffer does not operate at the level where the reference voltage is low by using the buffers I0 and I1, the output end becomes the "L" state and the power-down state.

Figure 6 is a circuit diagram of a third embodiment of a clock enable buffer according to the present invention.

According to the third embodiment of the present invention, the reference voltage VREF input to the NMOS transistor NM2 and the clock enable signal CKE input to the NMOS transistor NM3 gate in response to the input signal EN are applied. The output power supply that has passed through the buffers I2 and I3 as the input signal EN inputted to the clock enable buffering unit 100 and the clock enable buffering unit 100 to generate the output signal out by comparing the magnitudes. When it is detected that the voltage VDDQ has reached a predetermined level, it is configured as an initialization stabilizer 230 using a signal output by the control signal CNTL related to self refresh or power down. Here, the CKE_CTRL block in the initialization stabilizer 230 may include an NAND gate and a NOR gate output connected to the NAND gate and the NAND gate output which input the output side power supply voltage VDDQ and the control signal CNTL.

7A and 7B are simulation waveform diagrams of a clock enable buffer according to the present invention.

FIG. 7A is a simulation result of the first embodiment of the present invention disclosed in FIG. 4, and it can be seen that the output is maintained in the "L" state even in a period where the reference voltage is low, thereby preventing the malfunction.

FIG. 7B is a simulation result of the second embodiment of the present invention disclosed in FIG. 5 and the third embodiment disclosed in FIG. 6, by using the VDDQ voltage as an input signal by using a voltage divided by the VDDQ voltage and the VSSQ voltage. Since the output remains in the "L" state, it goes into a power-down state, preventing malfunction.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited to.

According to the above configuration, the present invention has an excellent effect of reliably preventing a malfunction during initialization of the clock enable buffer by not accepting any command or address when the clock enable signal is in the "L" state.

Claims (5)

Clock enable buffering means for generating an output signal by comparing a reference voltage input to the first NMOS transistor gate with a magnitude of a clock enable signal input to the second NMOS transistor gate in response to an input signal; And Initialization stabilization means located between the clock enable buffering means and the ground voltage side so that the clock enable buffering means operates when the reference voltage is above a threshold voltage using the reference voltage as a control signal of a gate. The clock enable buffer comprising a. Clock enable buffering means for generating an output signal by comparing a reference voltage input to the first NMOS transistor gate with a magnitude of a clock enable signal input to the second NMOS transistor gate in response to an input signal; And The clock enable buffering means is enabled by turning on a third NMOS transistor between the clock enable buffering means and the ground voltage side by using an output power supply voltage as a gate control signal, and the output power supply voltage is used as a gate control signal. Initialization stabilizing means for disabling said clock enable buffering means by turning on a first PMOS transistor between an input side power supply voltage and an output terminal The clock enable buffer comprising a. The method of claim 2, wherein the initialization stabilization means, A plurality of buffers are connected in series between the output power supply voltage terminal and the third NMOS transistor so as to detect whether the level of the output power supply voltage reaches 1 to 2 times the threshold voltage of the NMOS transistor. Clock enable buffer. Initialization stabilizing means for outputting, by the control of the control signal, if it is detected that the output side power supply voltage reaches a predetermined level; And The signal output from the initialization stabilization means is used as an input signal, and the magnitude of the clock enable signal input to the second NMOS transistor gate is compared with the reference voltage input to the first NMOS transistor gate in response to the input signal. Clock enable buffering means for generating an output signal The clock enable buffer comprising a. The method of claim 4, wherein the initialization stabilization means, And a plurality of buffers connected in series so as to detect whether the level of the output power voltage reaches 1 to 2 times the threshold voltage of the NMOS transistor.