KR20030091334A - Liquid crystal display panel and fabricating method thereof - Google Patents

Abstract

PURPOSE: A liquid crystal display panel and a method for manufacturing the same are provided to prevent line type holes of an organic protective film from being exposed due to a position error of a seal pattern. CONSTITUTION: A thin film transistor array substrate(52) includes a plurality of signal lines, pixel electrodes and thin film transistors formed at a video display area, and an organic protective film having a plurality of holes at a sealing area. A color filter array substrate(54) is opposite to the thin film transistor array substrate, and includes color filters. A main seal pattern(56) and a dummy seal pattern(57) are placed at the sealing area in two rows following an outline of the video display area to bond the thin film transistor array substrate and the color filter array substrate. Liquid crystal is formed between the bonded substrates.

Description

Liquid crystal display panel and manufacturing method therefor {LIQUID CRYSTAL DISPLAY PANEL AND FABRICATING METHOD THEREOF}

The present invention relates to a liquid crystal display panel to which an organic protective film is applied, and more particularly, to a liquid crystal display panel and a manufacturing method thereof capable of preventing the penetration of external contaminants due to a defective seal pattern.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

In the liquid crystal display panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned at the intersections of the gate lines and the data lines. Each of the liquid crystal cells is provided with pixel electrodes and a common electrode for applying an electric field. Each of the pixel electrodes is connected to one of the data lines via a thin film transistor which is a switching element. The gate terminal of the thin film transistor is connected to one of the gate lines through which the pixel voltage signal is applied to the pixel electrodes for one line. Accordingly, the liquid crystal between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell. By changing the arrangement state and adjusting the light transmittance, the liquid crystal display panel displays an image.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a common voltage generator for driving the common electrode. The gate driver sequentially supplies the scanning signal, that is, the gate signal to the gate lines, to sequentially drive the liquid crystal cells on the liquid crystal display panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a gate signal is supplied to any one of the gate lines. The common voltage generator supplies a common voltage signal to the common electrode.

Among the driving circuits, the data driver and the gate driver directly connected to the liquid crystal display panel are integrated into a plurality of integrated circuits (hereinafter, referred to as ICs). Each integrated data drive IC and gate drive IC are mounted on a tape carrier package (TCP) and connected to a liquid crystal display panel using a tape automated bonding (TAB) method, or directly on a liquid crystal display panel using a chip on glass (COG) method. It is mounted.

In fact, the liquid crystal display panel has a structure in which the thin film transistor array substrate 2 and the color filter array substrate 4 are joined to each other as shown in FIG. 1. The bonded thin film transistor array substrate 2 and the color filter array substrate 4 maintain a constant cell gap by a spacer, and the cell gap is filled with a liquid crystal for light transmittance control.

The thin film transistor array substrate 2 includes gate lines and data lines formed on the lower substrate, thin film transistors formed of switching elements at intersections of the gate lines and the data lines, and are formed in liquid crystal cell units and connected to the thin film transistors. A pixel electrode and the like. The gate lines receive a scan signal from the gate driver through the gate pad unit 10. The data lines are supplied with the pixel voltage signal from the data driver through the data pad unit 8. The thin film transistor supplies the pixel voltage signal supplied to the data line to the pixel electrode in response to the scan signal supplied to the gate line.

The color filter array substrate 4 includes color filters formed in units of liquid crystal cells on an upper substrate, black matrices for distinguishing between color filters and reflecting external light, a common electrode for supplying a reference voltage to the liquid crystal cells in common. It is provided.

The thin film transistor array substrate 2 and the color filter array substrate 4 are bonded through a seal pattern 6 applied along the outer edge of the image display area in which the liquid crystal cells are provided. In this case, the color filter array substrate 4 is bonded to the thin film transistor array substrate 2 so that the data pad portion 8 and the gate pad portion 10 provided outside the thin film transistor array substrate 2 are exposed.

In particular, the thin film transistor array substrate 2 is coated with a protective film for protecting the thin film transistor and the signal lines. The pixel electrode is formed on the passivation layer for each cell region. As the protective film, an inorganic protective film and an organic protective film are largely used.

As the inorganic protective film, an inorganic insulating material such as SiNx or SiOx is used. Such an inorganic protective film has a high dielectric constant and is difficult to increase in height because it is formed by a deposition method. For this reason, the pixel electrode and the data line having the inorganic protective film therebetween must maintain a constant horizontal interval, for example, a horizontal interval of 3 to 5 μm, in order to minimize the coupling effect of the parasitic capacitor. As a result, the size of the pixel electrode which determines the aperture ratio of the liquid crystal cell is reduced, resulting in a lower aperture ratio.

The organic protective film is applied to solve the low aperture ratio problem caused by the inorganic protective film, and an organic insulating material having a relatively low dielectric constant is used. In addition, the organic protective film has an advantage that it can be formed relatively thick by the spin coating method. The parasitic capacitor capacitance between the data line and the pixel electrode is reduced by the organic passivation layer having a relatively low dielectric constant and a thick thickness, so that the organic passivation layer overlaps the data line with the pixel electrode and the organic passivation layer interposed therebetween. As a result, the size of the pixel electrode is increased and the aperture ratio is increased.

In the liquid crystal display panel in which the organic protective film is applied to increase the aperture ratio, the seal pattern is in contact with the organic protective film of the thin film transistor array substrate. However, as the seal pattern using epoxy resin and the like have poor adhesion characteristics with the organic protective film, defects such as liquid crystal leakage have been caused through poor adhesion. In order to prevent such poor adhesion between the seal pattern and the organic protective film, a method of improving the adhesive property by partially or entirely removing the organic protective film to which the seal pattern is applied has been adopted.

FIG. 2 is an enlarged plan view of some link regions 12 of the data link regions of the thin film transistor array substrate 2 traversed by the seal pattern 6 illustrated in FIG. 1, and FIG. 3 is illustrated in FIG. 2. It is sectional drawing which cut | disconnected the link area | region 12 along the line AA '. In particular, FIG. 3 illustrates the addition of the color filter array substrate 4 bonded to the thin film transistor array substrate 2 via the seal pattern 6.

In the data link region of the thin film transistor array substrate 2, data links 14 are formed on the gate insulating film 20 on the lower substrate 18. Each of the data links 14 electrically connects a data line and a data pad. An organic passivation layer 22 is formed on the data links 14, and then line-shaped holes 16 are formed in a sealing region to be patterned to apply a seal pattern in a subsequent process. The gate insulating film 20 is exposed through the line holes 16 or the data link 14 is partially exposed. The lower alignment layer 24 for liquid crystal alignment in the image display area is applied on the organic passivation layer 22.

In the color filter array substrate 4, a common electrode 32 is formed below the upper substrate 30, and a black matrix 34 and a color filter 36 are formed below the common electrode 32. Under the black matrix 34 and the color filter 36, an upper alignment layer 38 for liquid crystal alignment in the image display area is applied.

The thin film transistor array substrate 2 and the color filter array substrate 4 are bonded through a seal pattern 6 applied in a direction crossing the data links 14 and the line-shaped holes 16. The bonded thin film transistor array substrate 2 and the color filter array substrate 4 maintain a constant cell gap by spacers, and the liquid crystal 26 is filled in the cell gap.

The liquid crystal display panel employing the organic protective film 22 is formed by forming a plurality of line-shaped holes 16 in the organic protective film 22 to reduce the contact area between the seal pattern 6 and the organic protective film 22. The adhesion characteristic of the pattern 6 is improved. In this case, it is preferable that the seal pattern 6 is usually applied to cover all of the line-shaped holes 16. However, due to the application position error of the seal pattern 6, the seal pattern 6 may not cover all of the line-shaped holes 16, thereby causing a defect in which the ends are exposed. When the seal pattern 6 does not cover all of the linear holes 16, contaminants penetrate from the outside through the exposed linear holes 16. In particular, when the line-type holes 16 are exposed to the outer side of the seal pattern 6, contaminants from the outside penetrate by the negative pressure state of the line-type holes 16. For example, the cleaning liquid penetrates from the outer side of the seal pattern 6 through the exposed line-shaped holes 16 during the liquid crystal display panel cleaning process. The contaminants penetrated through the linear holes 16 may corrode the exposed metal wiring, that is, the data link 14, and cause defects such as line defects. In addition, the contaminants penetrated through the line-shaped holes 16 weaken the adhesive force of the seal pattern 6, or further, the contaminants penetrate into the seal pattern 6 through portions where the adhesive force is weakened, thereby displaying an image. Smudges may occur in areas.

Accordingly, an object of the present invention is to provide a liquid crystal display panel and a method of manufacturing the same, which can prevent penetration of external contaminants through holes formed in the organic protective film.

1 is a plan view schematically showing a general liquid crystal display panel structure.

FIG. 2 is an enlarged plan view of a portion of the link area that the yarn pattern illustrated in FIG. 1 crosses.

FIG. 3 is a cross-sectional view of the link region shown in FIG. 2 taken along line AA ′. FIG.

4 is a plan view schematically illustrating a structure of a liquid crystal display panel according to an exemplary embodiment of the present invention.

FIG. 5 is an enlarged plan view of a portion of the link area that the yarn pattern illustrated in FIG. 4 crosses.

6 is a cross-sectional view of the link region shown in FIG. 5 taken along the line BB ′;

<Description of Symbols for Main Parts of Drawings>

2, 52: lower substrate 4, 54: upper substrate

6, 56, 57: yarn pattern 8, 58: data pad

10, 60: gate pad 12, 62: link area

14, 64: data link 16, 66: hole

20, 70: gate insulating film 22, 72: organic protective film

24, 74: lower alignment layer 26, 76: liquid crystal

32, 82: common electrode 34, 84: black matrix

36, 86: color filter 38, 88: upper alignment layer

In order to achieve the above object, a liquid crystal display panel according to the present invention includes a plurality of signal lines, pixel electrodes and thin film transistors formed in units of cells in an image display area, and an organic protective film having a plurality of holes formed in a sealing area. A formed thin film transistor array substrate; A color filter array substrate facing the thin film transistor array substrate and having color filters formed thereon; A seal pattern positioned in two rows along the outer edge of the image display area in the sealing area to bond the thin film transistor array substrate and the color filter array substrate together; And a liquid crystal formed between the bonded substrates.

Here, the seal pattern may include a main seal pattern applied in a direction crossing the holes while overlapping the plurality of holes; It characterized in that it comprises a dummy yarn pattern applied along the outer periphery of the main yarn pattern.

A liquid crystal display panel manufacturing method according to the present invention includes a thin film transistor array including a plurality of signal lines, pixel electrodes and thin film transistors formed in units of cells in an image display area, and an organic passivation layer having a plurality of holes formed in a sealing area. Providing a substrate; Providing a color filter array substrate having color filters formed in units of cells; Bonding the thin film transistor array substrate and the color filter array substrate to each other by applying a seal pattern in two rows along the outer edge of the image display region in the sealing region; Forming a liquid crystal between the bonded substrates.

Here, the application of the seal pattern in the bonding step includes applying a main seal pattern in a direction crossing the holes while overlapping the plurality of holes; And applying a dummy yarn pattern along the periphery of the main yarn pattern.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 6.

4 is a plan view schematically illustrating a liquid crystal display panel according to an exemplary embodiment of the present invention.

The liquid crystal display panel illustrated in FIG. 4 includes a thin film transistor array substrate 52 and a color filter array substrate 54 bonded to each other.

The thin film transistor array substrate 52 includes gate lines and data lines formed on the lower substrate, thin film transistors formed of switch elements at intersections of the gate lines and the data lines, and are formed in liquid crystal cell units and connected to the thin film transistors. A pixel electrode and the like. The gate lines receive a scan signal from the gate driver through the gate pad part 60. The data lines are supplied with the pixel voltage signal from the data driver through the data pad unit 58. The thin film transistor supplies the pixel voltage signal supplied to the data line to the pixel electrode in response to the scan signal supplied to the gate line.

The color filter array substrate 54 includes color filters formed in units of liquid crystal cells on an upper substrate, black matrices for distinguishing between color filters and reflecting external light, a common electrode for supplying a reference voltage to the liquid crystal cells in common. It is provided.

The thin film transistor array substrate 52 and the color filter array substrate 54 are bonded through the main seal pattern 56 and the dummy seal pattern 57 applied along the outer edge of the image display area. The dummy seal pattern 57 is for preventing the infiltration of contaminants from the outside due to the positional error of the main seal pattern 56. The color filter array substrate 54 is bonded to the thin film transistor array substrate 52 so that the data pad portion 58 and the gate pad portion 60 provided outside the thin film transistor array substrate 52 are exposed. The bonded thin film transistor array substrate 52 and the color filter array substrate 54 maintain a constant cell gap by a spacer, and the cell gap is filled with liquid crystal for light transmittance control.

FIG. 5 is an enlarged plan view illustrating some link regions 62 of the data link regions of the thin film transistor array substrate 52 intersecting the main seal pattern 56 and the dummy seal pattern 57 of FIG. 4. FIG. 6 is a cross-sectional view of the link region 62 of FIG. 5 taken along the line BB '. In particular, FIG. 6 illustrates the addition of the color filter array substrate 54 bonded to the thin film transistor array substrate 52 through the main seal pattern 56 and the dummy seal pattern 57.

In the data link region of the thin film transistor array substrate 52, data links 64 are formed on the gate insulating layer 70 on the lower substrate 68. Each of the data links 64 electrically connects a data line and a data pad. An organic passivation layer 72 is formed on the data links 64, and then line-shaped holes 66 are formed in a sealing region to be patterned to apply a seal pattern in a subsequent process. The gate insulating layer 70 is exposed through the line holes 66 or the data link 64 is partially exposed. The lower alignment layer 74 is disposed on the organic passivation layer 72 for liquid crystal alignment in the image display area. As the organic protective layer 72, an acryl compound, Teflon, BCB (benzocyclobutene), cytotope (cytop), or perfluorocyclobutane (PFCB) is used.

In the color filter array substrate 54 facing the data link region of the thin film transistor array substrate 52, the common electrode 82 is disposed under the upper substrate 80, and the black matrix 84 is disposed under the common electrode 82. ) And a color filter 86 are formed. Under the black matrix 84 and the color filter 86, an upper alignment layer 88 for liquid crystal alignment in the image display area is applied.

The thin film transistor array substrate 52 and the color filter array substrate 54 may include a main seal pattern 56 and a dummy seal pattern 57 applied in a direction crossing the data links 64 and the line-shaped holes 66. Are cemented through. In other words, the thin film transistor array substrate 52 and the color filter array substrate 54 are bonded through the main seal pattern 56 and the dummy seal pattern 57 applied in two rows. The spacers are dispersed between the thin film transistor array substrate 52 and the color filter array substrate 54 thus bonded to maintain a constant cell gap, and after the liquid crystal 76 is injected into the cell gap, the liquid crystal display panel is completed. do.

Alternatively, the liquid crystal 76 may be dropped onto one of the thin film transistor array substrate 52 and the color filter array substrate 54, and then the two substrates 52 and 56 may be bonded to each other. In this case, the closed-type seal pattern which does not need a liquid crystal injection hole separately is formed in the other board | substrate which does not drop the liquid crystal 76, and the photocurable seal pattern is used as the seal pattern.

The liquid crystal display panel employing the organic protective film 72 is formed by reducing the contact area between the main seal pattern 56 and the organic protective film 72 by forming a plurality of line-shaped holes 66 in the organic protective film 72. The adhesive property of the seal pattern is improved.

A dummy yarn pattern 57 is further formed along the outer periphery of the main yarn pattern 56. The dummy seal pattern 57 is to prevent the line-shaped holes 66 formed in the organic passivation layer 72 from being exposed at the outer side of the main seal pattern 56 due to the application position error of the main seal pattern 56. . In other words, since the yarn pattern is applied in two rows of the main yarn pattern 56 and the dummy yarn pattern 57, the line-shaped holes 66 are formed at the outside of the main yarn pattern 56 due to the positional error of the main yarn pattern 56. This can prevent the side from being exposed. Accordingly, contaminants from the outside may be prevented from penetrating through the line-shaped holes 66. As a result, defects such as line defects, weakening of adhesion, and stain generation, which have conventionally been caused by contaminant penetration through the line-shaped holes 66, do not occur.

As described above, the liquid crystal display panel and the method of manufacturing the same according to the present invention can prevent the line-shaped hole of the organic protective film from being exposed from the outer side due to the positional error of the seal pattern by applying the seal pattern in two rows. Accordingly, since the line-type hole of the organic protective film is not exposed from the outer side of the seal pattern, it blocks the infiltration of external contaminants through the line-type hole, thereby preventing defects such as line defects, weakened adhesive strength, and stains caused by the conventional contaminant infiltration. It can be prevented.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (4)

A thin film transistor array substrate having a plurality of signal lines, pixel electrodes and thin film transistors formed in units of cells in an image display area, and an organic passivation layer having a plurality of holes formed in a sealing area; A color filter array substrate facing the thin film transistor array substrate and having color filters formed thereon; A seal pattern positioned in two rows along the outer edge of the image display area in the sealing area to bond the thin film transistor array substrate and the color filter array substrate together; And a liquid crystal formed between the bonded substrates. The method of claim 1, The thread pattern is A main seal pattern overlapping the plurality of holes and coated in a direction crossing the holes; And a dummy yarn pattern applied along an outer portion of the main yarn pattern. Providing a thin film transistor array substrate having a plurality of signal lines, pixel electrodes and thin film transistors formed in units of cells in an image display area, and an organic passivation layer having a plurality of holes formed in a sealing area; Providing a color filter array substrate having color filters formed in units of cells; Bonding the thin film transistor array substrate and the color filter array substrate to each other by applying a seal pattern in two rows along the outer edge of the image display area in the sealing region; Forming a liquid crystal between the bonded substrates. The method of claim 3, wherein The seal pattern is applied in the bonding step Applying a main seal pattern in a direction crossing the holes while overlapping the plurality of holes; And applying a dummy seal pattern along an outer edge of the main seal pattern.