KR20030085628A - Method of forming CMOS logic device of semiconductor - Google Patents
Method of forming CMOS logic device of semiconductor Download PDFInfo
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- KR20030085628A KR20030085628A KR1020020023502A KR20020023502A KR20030085628A KR 20030085628 A KR20030085628 A KR 20030085628A KR 1020020023502 A KR1020020023502 A KR 1020020023502A KR 20020023502 A KR20020023502 A KR 20020023502A KR 20030085628 A KR20030085628 A KR 20030085628A
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- polysilicon
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- cmos logic
- salicide
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 229920005591 polysilicon Polymers 0.000 claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 3
- 239000010703 silicon Substances 0.000 claims abstract description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims description 2
- 238000002955 isolation Methods 0.000 abstract description 2
- 239000002019 doping agent Substances 0.000 abstract 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 208000031610 hypomyelinating 20 leukodystrophy Diseases 0.000 description 1
- 208000027209 hypomyelinating leukodystrophy 20 Diseases 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
Abstract
Description
본 발명은 반도체 씨모스(CMOS) 로직 디바이스의 제조 방법에 관한 것으로, 보다 상세하게는, 고집적 씨모스 반도체 소자의 트랜지스터를 형성하기 위한 반도체 씨모스 로직 디바이스의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor CMOS device, and more particularly, to a method of manufacturing a semiconductor CMOS logic device for forming a transistor of a highly integrated CMOS semiconductor device.
현재 로직 디바이스 제조에 있어서 가장 큰 문제점 중의 하나는 PMOS 폴리 샐리사이드 표면 저항(Rs ; Sheet Resistance)의 특성 열화이다.샐리사이드(Salicide) 형성 후 진행되는 후속 열공정에 의해 샐리사이드 표면저항의 패일(Fail) 현상이 심화된다.One of the biggest problems at present in logic device fabrication is the degradation of the properties of PMOS poly salicide surface resistance (Rs). The failure of salicide surface resistance by subsequent thermal processes following the formation of salicide ( Fail) The phenomenon is intensified.
이와 같은 열적 안정도 문제를 개선시키기 위해 많은 노력을 하고 있으나 충분한 공정 마진(Margin)을 확보하기가 쉽지 않은 상황이다.Although efforts have been made to improve such thermal stability problems, it is not easy to secure sufficient process margins.
NMOS 폴리 샐리사이드 표면저항, NMOS 액티브 표면저항 및 PMOS 액티브 영역의 표면저항은 별 문제가 없으나 PMOS 폴리 샐리사이드의 표면저항 특성은 선폭이 줄어듦에 따라 점점 더 열화되는 현상을 보이고 있는 것이다.NMOS poly salicide surface resistance, NMOS active surface resistance and the surface resistance of the PMOS active region have no problem, but the surface resistance characteristics of PMOS poly salicide are gradually deteriorating as the line width decreases.
이와 같은 문제점을 해결하기 위한 본 발명의 목적은, 샐리사이드의 표면저항을 감소시키도록 하기 위한 반도체 씨모스 로직 디바이스의 제조 방법을 제공하는 것이다.An object of the present invention for solving such a problem is to provide a method for manufacturing a semiconductor CMOS logic device for reducing the surface resistance of salicide.
본 발명의 다른 목적은, 채널 지역의 폴리 선폭은 디자인 룰(Design Rule)에 의한 크기로 형성하는 반면, 샐리사이드가 형성되는 부분의 폴리 선폭은 크게 하여 샐리사이드 단면적을 크게 하여 샐리사이드 표면저항 값을 감소시키기 위한 반도체 씨모스 로직 디바이스의 제조 방법을 제공하는 것이다.According to another object of the present invention, the poly line width of the channel region is formed by the size of the design rule, while the poly line width of the portion where the salicide is formed is increased to increase the salicide cross-sectional area to increase the salicide surface resistance To provide a method for manufacturing a semiconductor CMOS logic device to reduce the.
도 1 내지 도 4는 본 발명의 반도체 씨모스 로직 디바이스 제조 과정의 일 실시예를 보여주는 공정 단면도들이다.1 through 4 are process cross-sectional views illustrating one embodiment of a semiconductor CMOS logic device fabrication process of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 반도체 기판12 : 트렌치 영역10 semiconductor substrate 12 trench region
14 : 게이트 옥사이드16 : 폴리실리콘14 gate oxide 16: polysilicon
18 : HLD20 : 나이트라이드18: HLD20: nitride
22 : 게이트 폴리24 : 샐리사이드22: gate poly 24: salicide
상기 목적을 달성하기 위한 본 발명에 의한 반도체 씨모스 로직 디바이스의 제조 방법은, 실리콘 기판 위에 소자 절연용 트렌치 절연막을 형성하는 단계와, 상기 절연막 위에 게이트 옥사이드를 성장시킨 후 제 1 폴리실리콘을 증착하는 단계와, 소스/드레인 형성을 위한 저농도의 이온을 주입하는 단계와, 게이트 폴리 패터닝을 한 후 스페이서(Spacer)를 형성하는 단계와, 상기 소스/드레인 형성을 위한 고농도의 이온을 주입하는 단계와, 상기 제 1 폴리실리콘과 상기 스페이서를 포함하여 일정 두께가 되도록 화학기계적으로 연마하는 공정을 진행하는 단계와, 상기 연마공정이 종료된 후 상기 제 1 폴리실리콘 위에 제 2 폴리실리콘을 증착하는 단계와, 상기 제 2 폴리실리콘이 게이트 전극으로 형성되도록 패터닝을 진행하는 단계, 그리고, 패터닝된 상기 제 2 폴리실리콘 위에 샐리사이드를 형성하는 단계를 포함하는 것을 특징으로 한다.A method for manufacturing a semiconductor CMOS logic device according to the present invention for achieving the above object comprises forming a trench insulating film for device insulation on a silicon substrate, and growing a gate oxide on the insulating film and then depositing first polysilicon; Implanting a low concentration of ions for source / drain formation, forming a spacer after gate poly patterning, implanting a high concentration of ions for source / drain formation, Performing a process of chemical mechanical polishing including the first polysilicon and the spacer to a predetermined thickness, and depositing second polysilicon on the first polysilicon after the polishing process is finished; Patterning the second polysilicon as a gate electrode, and patterning the second polysilicon Forming a salicide on the second polysilicon.
본 발명의 바람직한 예에 의해 상기 제 2 폴리실리콘의 선폭은 상기 제 1 폴리실리콘의 선폭보다 더 크게 형성되도록 하는 것이 바람직하다.According to a preferred embodiment of the present invention, the line width of the second polysilicon is preferably larger than that of the first polysilicon.
상기 스페이서는 에치엘디(HLD)와 나이트라이드로 형성되도록 할 수 있으며, 상기 제 1 폴리실리콘이 연마된 후의 두께는 1300 내지 1800Å로 하는 것이 바람직하다.The spacer may be formed of HLD and nitride, and the thickness after the first polysilicon is polished is preferably 1300 to 1800 kPa.
그리고, 상기 샐리사이드는 상기 제 2 폴리실리콘의 선폭보다 더 크게 형성하며, 상기 제 2 폴리실리콘을 외측에서 둘러싸도록 형성되는 것이 바람직하다.In addition, the salicide is formed to be larger than the line width of the second polysilicon, and is preferably formed to surround the second polysilicon from the outside.
이하, 본 발명의 실시예에 대한 설명은 첨부된 도면을 참조하여 더욱 상세하게 설명한다. 아래에 기재된 본 발명의 실시예는 본 발명의 기술적 사상을 예시적으로 설명하기 위한 것에 불과한 것으로, 본 발명의 권리범위가 여기에 한정되는 것으로 이해되어서는 안될 것이다. 아래의 실시예로부터 다양한 변형, 변경 및 수정이 가능함은 이 분야의 통상의 지식을 가진 자에게 있어서 명백한 것이다.Hereinafter, an embodiment of the present invention will be described in more detail with reference to the accompanying drawings. The embodiments of the present invention described below are merely for illustrating the technical idea of the present invention by way of example, it should not be understood that the scope of the present invention is limited thereto. Various modifications, changes and variations are possible in the following examples which will be apparent to those of ordinary skill in the art.
본 발명의 실시예에 의한 반도체 씨모스 로직 디바이스의 제조과정을 도 1내지 도 4를 참조하여 설명한다.A manufacturing process of a semiconductor CMOS logic device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4.
먼저, 도 1을 참조하면, 반도체 기판(10) 위에 STI(Shallow Trench Isolation) 방법을 통해 트렌치 영역(12)을 형성하여 액티브 영역을 아이솔레이션 시키고, 그 위에 게이트 옥사이드(14)를 성장시킨다. 그리고, 상기 게이트 옥사이드(14) 위에 1500 내지 2500Å 두께로 폴리실리콘(16)을 증착한 후 게이트 폴리 패터닝을 실시한다. 이때 패터닝된 게이트 폴리는 그 선폭이 0.12 내지 0.18㎛의 두께가 되도록 패터닝되며, 바람직하게는 0.15㎛ 두께로 실시된다.First, referring to FIG. 1, the trench region 12 is formed on the semiconductor substrate 10 through the shallow trench isolation (STI) method to isolate the active region, and the gate oxide 14 is grown thereon. In addition, after the polysilicon 16 is deposited on the gate oxide 14 to a thickness of 1500 to 2500 Å, gate poly patterning is performed. At this time, the patterned gate poly is patterned such that its line width is 0.12 to 0.18 탆 thick, and preferably 0.15 탆 thick.
그리고, 소스와 드레인 형성을 위한 저농도의 불순물 이온을 주입하는 LDD(Lightly Doped Drain) 이온주입을 실시한 후 LDD 스페이서를 형성한다. 이때 상기 스페이서는 HLD(High temperature Low pressure Deposition)(18)와 나이트라이드(20)로 이루어지며, 그 두께는 HLD(18)가 100 내지 200Å이고, 나이트라이드(20)의 두께는 600 내지 1000Å으로 형성되는 것이 바람직하다.Then, LDD (Lightly Doped Drain) ion implantation is performed to inject low concentrations of impurity ions for source and drain formation to form LDD spacers. At this time, the spacer is made of a high temperature low pressure deposition (HLD) 18 and the nitride 20, the thickness of the HLD (18) is 100 to 200Å, the thickness of the nitride 20 is 600 to 1000Å It is preferably formed.
도 2를 참조하면, 폴리실리콘(16)을 화학, 기계적으로 연마하고 LDD를 형성한 후의 상태를 볼 수 있다.2, the state after the polysilicon 16 is chemically and mechanically polished and the LDD is formed can be seen.
즉, 폴리실리콘(16)에 CMP(Chemical Mechanical Polishing)를 실시하여 폴리실리콘(16')의 두께가 1500Å이 되도록 한다. 이렇게 되면 폴리실리콘(16') 뿐만 아니라 스페이서인 HLD(18')와 나이트라이드(20')도 함께 CMP에 의해 플랫(Flat)한 면을 얻을 수 있게 된다.That is, the polysilicon 16 is subjected to chemical mechanical polishing (CMP) so that the thickness of the polysilicon 16 'is 1500 kPa. In this case, not only the polysilicon 16 'but also the spacer HLD 18' and the nitride 20 'can be obtained with a flat surface by CMP.
도 3을 참조하면, 상기 플랫한 면 위에 2차 폴리실리콘 증착 및 패터닝 후 게이트 폴리(22)가 형성된 것을 보여주고 있다. 상기 폴리실리콘은 1차 폴리실리콘증착 때와는 달리 약 500Å으로 얇게 형성한다.Referring to FIG. 3, the gate poly 22 is formed after the secondary polysilicon deposition and patterning on the flat surface. The polysilicon is formed as thin as about 500 kPa, unlike when polysilicon is deposited.
상기 게이트 폴리(22)가 형성된 후에는 소스/드레인 형성을 위한 고농도의 이온을 주입하는 이온주입 공정이 이루어지고, 그 후에 게이트 전극 형성을 위한 코발트(Co) 샐리사이드(24)를 형성시킨다. 이에 대한 도면이 도 4에 도시되어 있다.After the gate poly 22 is formed, an ion implantation process of implanting a high concentration of ions for source / drain formation is performed, and then cobalt (Co) salicide 24 is formed to form a gate electrode. A diagram of this is shown in FIG. 4.
1차로 증착된 폴리실리콘은 디자인 크기에 맞춰 선폭을 갖게 되고, 2차로 증착된 폴리실리콘은 선폭을 스페이서 부분까지 크게 해줌으로써 결과적으로 샐리사이드(24)가 형성되는 면적이 100% 이상 크게 되는 효과를 얻게 된다.The first-deposited polysilicon has a line width in accordance with the design size, and the second-deposited polysilicon increases the line width up to the spacer portion, resulting in an area over 100% of the area where the salicide 24 is formed. You get
이와 같이 형성되는 본 발명의 실시예에 의하면, 0.15㎛ 로직 기술 개발에 있어서 폴리실리콘의 선폭이 줄어듦에 따라 급격히 열화되는 샐리사이드 표면 저항(Rs) 문제가 해결될 수 있게 된다.According to the embodiment of the present invention formed as described above, the problem of salicide surface resistance (Rs) that is rapidly deteriorated as the line width of polysilicon decreases in the development of a 0.15 μm logic technology can be solved.
따라서, 본 발명에 의하면, 로직 디바이스에 있어서 PMOS 폴리 샐리사이드의 표면저항이 개선되고, 그에 따라 디바이스의 특성 향상이 이루어짐으로써 수율이 높아지는 효과가 있다.Therefore, according to the present invention, the surface resistance of the PMOS poly salicide is improved in the logic device, whereby the characteristics of the device are improved, whereby the yield is increased.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20040025949A (en) * | 2002-09-17 | 2004-03-27 | 아남반도체 주식회사 | Method for forming gate of semiconductor element |
| KR100481551B1 (en) * | 2002-09-23 | 2005-04-07 | 동부아남반도체 주식회사 | Method for forming sidewall spacers disposed around a gate in fabricating semiconductor element |
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| JP2000036594A (en) * | 1998-07-17 | 2000-02-02 | Texas Instr Japan Ltd | Semiconductor device and manufacture thereof |
| KR100611114B1 (en) * | 2001-01-17 | 2006-08-09 | 삼성전자주식회사 | Method of manufacturing a semiconductor device |
| KR100465055B1 (en) * | 2001-12-29 | 2005-01-05 | 매그나칩 반도체 유한회사 | Method of manufacturing a transistor in a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20040025949A (en) * | 2002-09-17 | 2004-03-27 | 아남반도체 주식회사 | Method for forming gate of semiconductor element |
| KR100481551B1 (en) * | 2002-09-23 | 2005-04-07 | 동부아남반도체 주식회사 | Method for forming sidewall spacers disposed around a gate in fabricating semiconductor element |
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