KR20030085142A - Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies - Google Patents

Abstract

Various integrated circuit probe card assemblies are described, which extend the mechanical compliance of these probes to test one or more integrated circuits on a semiconductor substrate using MEMS and thin film probes. In addition, we will discuss various probe card assemblies that have tight signal pad pitch and compliance, allowing you to parallel test or burn-in multiple ICs using a commercial wafer probe. In some preferred cases, probe card assembly structures include separate standard electrical connectors, saving assembly manufacturing costs and manufacturing time. Such structures and assemblies can speed up testing on a wafer. These probes preferably mechanically protect both integrated circuits and MEMS or thin film spring tips. In addition, interleaved spring probe tip designs are formed that can connect multiple probes on a tiny integrated circuit pad. Probe tips of this type are preferably formed to control the probe tip penetration depth between the probe spring and pad or trace on the integrated circuit. In addition, by improving the coating technology for the probe, it is possible to improve the life and quality of the probe card assembly.

Description

Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies

In a conventional integrated circuit (IC) wafer probe card, the contacts between the probe card and the integrated circuit wafer are typically provided as tungsten needle probes. However, advances in semiconductor technology require more pin counts, smaller pad pitches, and higher clock frequencies, but this is not possible with tungsten needle probes.

Although engineering probes are provided for different probes, most probes are basically limited in pitch, pin count, flexibility, tip shape, material, manufacturing cost, and the like.

U.S. Patent No. 5,166,774 dated Nov. 24, 1992, entitled "Selectively Releasing Conductive Runner and Substrate Assembly Having Non-Planar Areas" by K.Banerji, A.Suppelas, W.Mullen III. And some of these runners have regions that are not flat with the substrate, such that the runner / substrate assembly is selectively released from the substrate when subjected to a given stress.

U.S. Patent 5,280,139 of January 18, 1994 entitled "Selectively Releasing Conductive Runner and Substrate Assembly" by A.Suppelsa, W.Mullen III, G.Urbish includes a number of conductive runners bonded to a substrate, Some of these describe a runner / substrate assembly that is adhered to the bottom of the substrate and selectively released from the substrate when subjected to a given stress.

U.S. Patent No. 5,786,701 dated July 28, 1998, entitled "Bare Die Testing" by D.Pedder, discloses an apparatus for testing integrated circuits on bare die, which is a connection trace terminal of a multilayer interconnection structure. And a testing station in which a conductive microbump is disposed, the trace terminals being distributed in a pattern corresponding to the contact pad pattern on the die to be tested. In order to facilitate testing of the die before detaching from the wafer using these microbumps, other connections provided in the connection structure have a low profile.

U.S. Patent No. 5,152,695, entitled "Surface Mount Electrical Connector" by D. Grabbe, I. Korsunsky, R. Ringer, discloses a connector for electrically connecting a circuit between electronic devices. The connector includes a platform with cantilevered spring arms extending obliquely out of it. These spring arms protrude from the surface and become complex wiper shapes during bending.

U.S. Patent 5,847,572, entitled "Partly Replaceable Device for Testing a Multi-contact Integrated Circuit Chip Package" by H.Iwasaki, H.Matsunaga, T.Ohkubo, A test apparatus for testing a circuit (IC) is described. The test apparatus includes a socket base, contact units having contact support members and socket contact members, and anisotropic conductive plate assemblies having elastic insulating plates and conductive materials. The anisotropic conductive plate assemblies are arranged to hold each conductive material in contact with one of the socket contact members of the contact unit. The test apparatus further includes a contact retainer detachably mounted to the socket base to contact the socket contact members to the anisotropic plate assemblies to electrically connect the socket contact members and the conductive materials of the anisotropic plate assembly. When some of the socket contact members have reached the end of their life, maintenance of the test apparatus can be facilitated by replacing each of the contact units with a new one. In addition, the lead pins of the IC chip may be electrically connected to a test circuit board having the shortest paths formed through the conductive material of the anisotropic conductive plate assembly and a part of the socket contact member.

U.S. Patent 4,758,9278, entitled "Method of Mounting a Substrate Structure to a Circuit Board" by W.Berg, describes one side of the circuit board having matching characteristics in place relative to the contact pads of the circuit board. An invention is disclosed in which a substrate structure having conductive pads is mounted on a circuit board having conductive pads exposed on a surface. According to this substrate structure, the leads protrude from the substrate in the form of cantilever beams while being electrically connected to the contact pads of the substrate. The mating element having the plate portion has mating characteristics that can be distributed about the plate portion and connected with the mating characteristics of the circuit board, and move in parallel to the circuit board plane when so connected. This substrate structure is attached to the plate portion of the mating element so that the leads are located at a predetermined position for the mating characteristics of the circuit board. When the mating element is positioned in this way, the leads of the substrate overlap the contact pads of the circuit board. A clamp member is further provided for pressing the leads against the contact pads of the circuit board to maintain the electrical connection.

U.S. Patent No. 5,121,298, entitled "Conrolled Adhesion Conductor" of D.Sama, P.Palanisamy, J.Heam, D.Schwarz, issued June 9, 1992, discloses fine compositions useful for controlling the printing of adhesive conductive pads on printed circuit boards. It is described to include copper powder, shielding agent and adhesive. The adhesive is designed to provide adhesion to sinter the copper layer and then bond the copper layer to the substrate so that the copper layer can peel off from the substrate in response to thermal stress. In addition, the adhesive serves to enhance the bonding force between the copper particles to give the copper layer sufficient mechanical strength to peel off the copper layer without cracking.

US Patent No. 4,423,401, filed December 27, 1983, entitled "Thin-Film Electrothermal Device" by R. Mueller, describes a thin-film multilayer technology for the construction of micro-miniature electromechanical switches with low on-metal contact resistance and distinct on-off characteristics. It is described to use. Thermoelectrically activated switches are formed on a conventional hybrid circuit board using a method that can also be used as a method for manufacturing thin film circuits. Preferably, these switches comprise a cantilevered actuator member made of a hard and elastically bendable insulating (eg silicon nitride) strip, to which a metal heating element such as nickel is attached. The free end of the cantilever member is provided with a metal contact, which is connected to the fixed contact thereunder by bending the cantilever member due to the current applied to the heating element.

US Patent 4,320,438, entitled "Multi-Layer Ceramic Package" by S.Ibrahim, J. Elsner, discloses a chip array in which a plurality of ceramic layers each have a conductive pattern and adhere one or more chips to each other. Multilayer packages with internal cavities are described. The chip or chip array is connected to the metal conductive pattern through short wirebonds at different heights, and a specific conductive pattern is formed in each layer. The conductive patterns of each layer are connected to the various pads on the bottom of the ceramic package ultimately mounted on the metal plate through through holes filled with metal material or edges made of metal. In this case, the component density is high, but since the leads are connected in a zigzag form at completely different heights, the size of the wirebond regions can be maintained at 10 mm and the gap at 10 mm. As a result, component densities can be improved, but without limiting the interference between wirebonds, they are limited to obtaining the high component density networks required for multilayer ceramic packages.

US Patent No. 5,416,429, entitled "Probe Assembly for Testing Integrated Circuits" by F. McQuade, J.Lander, describes a probe assembly for testing integrated circuits, which is made of insulating material. A probe card with an opening in the center, a rectangular frame attached to the probe card with a small opening, four separate probe wings consisting of a flexible layered member having a conductive ground plate, an adhesive dielectric layer bonded to the ground plane, and a dielectric layer Probe wing traces of spring alloy copper on the top. A cantilevered leaf spring in each probe wing enters into the central opening and extends through a series of alignment probe fingers consisting of the ends of the probe wing traces. The tips of these probe fingers are arranged along a straight line and at intervals corresponding to the spacing of the respective contact pads along the edge of the IC under test. The cantilever portion of each of the four spring clamps contacts the leaf spring of each probe blade to adjust the leaf springs. There are four separate spring clamp adjustment means for adjusting the pressure exerted by each of the spring clamps on each probe wing. These spring clamp adjusting means have spring bias platforms which are respectively attached to the frame member by three screws and spring washers, so that the spring clamps can be moved in any direction to align with the probe fingers of each probe blade.

European Patent Application EP 0,731,369A2, filed February 14, 1996, entitled "Structure for Testing Bare Integrated Circuit Device" by D.Pedder, and U.S. Patent 5,764,070, issued June 9, 198, are connected to a bare IC or wafer to be tested. A test probe structure is disclosed that includes a multi-layer printed circuit probe arm supporting a tip of an MCM-D type substrate having a microbump row formed on its underside to form a necessary connection. The probe arm is supported at a slight angle to the integrated circuit or wafer surface, and the passive elements necessary to interface with the integrated circuit under test are formed on the MCM-D type substrate. Four such probe arms are formed, one on each side of the integrated circuit.

US Patent 5,829,128, entitled "Method of Making Temporary Connections Between Electronic Components," dated Nov. 3, 1998, entitled "Method of Mounting Resilient Contact Structure to Semiconductor Device" by B.Eldridge, G.Grube, I. Khandros, G.Mathieu. United States Patent No. 5,832,601, filed November 10, 1998, entitled "Method of Making Contact Tip Structure," US Patent No. 5,864,946, filed March 23, 1999, entitled "Mounting Spring Elements on Semiconductor Device." U.S. Patent 5,884,398, US Patent 5,878,486, issued March 9, 1999, entitled "Method of Burning-in Semiconductor Device," and U.S. Patent 5,897,326, dated April 27,1999, titled "Method of Exercising Semiconductor Device," It is described that the elastic contact structures are directly mounted so as to directly bond the pads of the semiconductor die before removing the semiconductor die. In this case, the semiconductor die may be operated by connecting the semiconductor die to a circuit board having a plurality of terminals disposed on the surface thereof. As a result, the semiconductor die can be separated from the semiconductor wafer, and the same elastic contact structures can be used to effectively connect the semiconductor die and other electronic elements (eg, circuit boards, semiconductor packages, etc.). When the elastic contact structure is used as all the metal-forming connecting elements of the present invention, burn-in operation can be performed within 60 minutes at a temperature of 150 ° C or higher. B. The contact tip structures by the Eldridge party provide an elastic contact structure, but because they must be individually mounted on the adhesive pad of the semiconductor die, the structure becomes complicated and the manufacturing cost increases. In addition, since the adhesive tip structure is formed of a wire, its shape is limited. This adhesive tip structure cannot satisfy the case where the pitch is as small as about 50 μm for the peripheral probe card or about 75 μm for the area array.

A surface-mount soldering socket is disclosed in U.S. Patent No. 5,772,451, filed June 30, 1998, entitled "sockets for Electronic Components and Methods of Connecting to Electronic Components" by T. Dozier II, B.Eldridge, G.Grube, I.Khandros, G.Mathieu. By means of this, the mounting of electronic elements such as semiconductor packages to a circuit board is described. Elastic contact structures extend from the top of the support substrate and solder ball (or other suitable) contact structures are disposed on the bottom of the support substrate. Complex connecting elements are used as the elastic contact structure disposed on the support substrate. In a suitable manner, selected ones of the elastic contact structures on the support substrate are connected through the substrate to the corresponding ones of the contact structures on the bottom surface of the support substrate. In an embodiment to accommodate the LGA type semiconductor package, the contact force perpendicular to the upper surface of the support substrate is brought into pressure contact between the external connection points of the semiconductor package and the elastic contact structures. In an embodiment adapted to receive a BGA type semiconductor package, there is a pressure contact between the external connection points of the semiconductor package and the elastic contact structures with a contact force parallel to the top surface of the support substrate.

Other techniques include spring-like probe tips made by a batch mode method such as thin film or micro electronic mechanical systems (MEMS).

PCT / US96 /, filed March 25, 1997, U.S. Patent No. 5,613,861, filed December 15, 1998, U.S. Patent No. 5,848,685, filed May 30, 1996, to D.Smith, S. Alimonda, " Photolithographically Patterned Spring Contact. &Quot; 08018 discloses photolithographic patterned spring contacts that electrically connect contact pads on two devices and are formed on a substrate. This spring contact also compensates for thermal mechanical changes and other environmental factors. The free end of the spring bends up and down the substrate according to the natural stress gradient of the spring contact. The anchor portion is fixed to the substrate and electrically connected to the first contact pad on the substrate. This spring contact is made of an elastic material and the free end contacts the two contact pads in compliance with the second contact pad. Although the photolithographic pattern springs by Smith party can meet many IC probe conditions, they are compact and have little vertical compliance to control the flatness compliance required for reliable operation of many current IC probe systems. The vertical compliance required for many probe systems is 0.004 "-0.010" and this level of compliance is required to use tungsten needle probes.

In addition, no one has disclosed how to connect probes with thousands of pins to testers while effectively handling flat compliance. As integrated circuits become more complex and smaller in size, it would be desirable to provide probe card assemblies that can reliably connect integrated circuits.

In order to accommodate the difference in planarity between the surface pads on the wafer under test and the probe tip array, it may be desirable to provide a probe substrate that can pivot slightly freely about a center point. However, in such a system, the contacts must be connected with precisely controlled forces while keeping the substrate stable in the X, Y and Z axis rotation directions. In addition, if many (thousands) of wires or springs protrude from the back of the substrate and the supports are arranged around the substrate, the expansion paths should not be interrupted by these supports. In addition, the pivot of the substrate should not be disturbed by the signal wires, nor should the force provided to connect the springs to the device under test be disturbed.

It would be desirable to provide a method and apparatus for an improved flexible probe spring that is high in pin count, small in pitch, inexpensive to manufacture and adaptable to suitable spring tips. It would also be advantageous to provide a probe card assembly utilizing such a flexible probe spring, as it provides precise axis and rotational movement while providing flat compliance to the semiconductor device under test and / or burn-in.

TECHNICAL FIELD The present invention relates to the field of probe card assembly systems, and in particular, to an improved probe card assembly and photolithographic pattern spring contacts having photolithographic pattern spring contacts used for testing and burn-in of integrated circuits. It is about improvement.

1 is a plan view of a linear array of photolithographic pattern springs before being released from a substrate;

2 is a perspective view of a linear array of photolithographic pattern springs after being released from the substrate;

3 is a side view of first short photolithographic pattern springs having a first effective radius and height after the short springs are released from the substrate;

4 is a side view of a second long photolithographic pattern spring having a second large effective radius and height after the long spring is released from the substrate;

5 is a perspective view of opposing photolithographic springs having an interleaved spring tip pattern before the spring is released from the substrate;

6 is a perspective view of an opposing photolithographic spring having an interleaved spring tip pattern after the spring is released from the substrate;

7 is a plan view of opposing pairs of interleaved multiprojection photolithographic probe springs in contact with a single trace on an integrated circuit;

8 is a plan view of an opposing single-projection photolithographic probe spring before the spring is released from the substrate;

9 is a plan view of the monolithic photolithographic probe springs in parallel opposite arrangement after the spring is released from the substrate and in contact with the single pad of the integrated circuit;

10 is a front view of a shoulder protruding photolithographic probe spring;

11 is a partial cross-sectional view of a shoulder protruding photolithographic spring with traces on an integrated circuit;

12 is a perspective view of a multiple shoulder protruding photolithographic probe spring;

FIG. 13 is a cross-sectional view of the probe card assembly, with a plurality of photolithographic spring probes on the bottom of the substrate electrically connected to flexible connectors on the top of the substrate, with the flexible connectors connected to the printed circuit board probe card; FIG.

14 is a partially enlarged cross-sectional view of the probe card assembly, showing a pitch of the printed circuit board probe card and the substrate being gradually expanded;

15 is a first partial cross-sectional view of a bridge / plate spring probe card assembly;

FIG. 16 is a second partial cross-sectional view of a bridge / plate spring suspension probe card assembly in contact with the device under test; FIG.

FIG. 17 is an enlarged, exploded view of the bridge / plate spring suspension probe card assembly; FIG.

FIG. 18 is a first cross-sectional view of a bridge / plate spring suspension probe card assembly in which an intermediate subcard is detachably connected to the probe card substrate, with a probe spring substrate detachably connected to the bridge; FIG.

19 is a second partial sectional view of the bridge / plate spring suspension probe card assembly shown in contact with the device under test;

20 is a cross-sectional view of the wire / spring post suspension probe card assembly.

FIG. 21 is a cross-sectional view of a suspended probe card assembly in which an intermediate lower card is detachably connected to the probe card substrate, and the probe spring substrate is electromechanically connected to the bridge through flexible connectors; FIG.

FIG. 22 is a cross-sectional view of the probe card assembly with the nanospring substrate connected directly to the probe card substrate through an array connector; FIG.

FIG. 23 is a cross-sectional view of a wire suspended probe card assembly in which a nanospring substrate is connected to a probe card substrate through an LGA insertion connector; FIG.

24 is a cross-sectional view of a small test area probe card assembly with one or more connectors formed between the probe card and the sub card, with the sub card attached to the small probe spring substrate via a microball grid solder array;

25 is a top view of a substrate wafer with a plurality of microball grid array probe spring contact chip substrates arranged thereon;

26 is a plan view of a single-pitch microball grid array nanospring contact chip;

27 is a plan view of a tiled probe strip having a plurality of probe strip contact regions;

28 is a bottom view of a plurality of tiled probe strips attached to a probe card support substrate.

29 is a side view of a plurality of tiled probe card strips attached to a probe card support substrate;

30 is a cross-sectional view of a structure capable of temporarily connecting a plurality of integrated circuits to a burn-in board through a plurality of probe spring contacts;

FIG. 31 shows a first step in a method of coating a spring probe assembly for applying a protective coating to the probe face of the spring probe assembly; FIG.

32 illustrates a second step of the method of coating a spring probe assembly for applying a photosensitive layer to a second substrate;

FIG. 33 shows a third step of a method of coating a spring probe assembly that partially penetrates a coated probe assembly into a photosensitive layer on a second substrate; FIG.

FIG. 34 illustrates a fourth step of a method of coating a spring probe assembly that removes a coated, partially infiltrated probe assembly from a second substrate;

35 shows a fifth step of a method of coating a spring probe assembly to etch a coated and penetrated probe assembly to remove a protective coating that has not penetrated the photosensitive layer;

FIG. 36 shows a sixth step of the method of coating a spring probe assembly to expose a protective coating by removing the photosensitive layer from the spring tip of the probe assembly; FIG.

37 is a partial cross-sectional view of a probe substrate covered with a reference plane.

Various integrated circuit probe card assemblies are described below to expand the mechanical compliance of these probes for testing one or more integrated circuits on a semiconductor substrate using MEMS and thin film probes. In addition, we will discuss various probe card assemblies that have tight signal pad pitch and compliance, allowing you to parallel test or burn-in multiple ICs using a commercial wafer probe. In some preferred cases, probe card assembly structures include separate standard electrical connectors, saving assembly manufacturing costs and manufacturing time. Such structures and assemblies can speed up testing on a wafer. These probes preferably mechanically protect both integrated circuits and MEMS or thin film spring tips. In addition, interleaved spring probe tip designs are formed that can connect multiple probes on a tiny integrated circuit pad. Probe tips of this type are preferably formed to control the probe tip penetration depth between the probe spring and pad or trace on the integrated circuit. In addition, by improving the coating technology for the probe, it is possible to improve the life and quality of the probe card assembly.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view 10 of a linear array 12 of photolithographic pattern springs 14a-14n prior to release from substrate 16. These conductive springs 14a-14n are formed on the substrate 16 by a continuous deposition metal layer by a high low energy plasma deposition process or the like and then formed by a photolithography pack pattern process as is well known in the semiconductor art. These continuous metal layers have basically different stress levels. Next, the release region 18 of the substrate 16 is undercut etched such that portions of the springs 14a-14n located above the release region 18 are released from the substrate 16 and extend from the substrate 16 (ie, Bend), due to the inherent stresses between the layer of metal being enlarged. The fixed region 15 of the deposited metal layers is attached to the substrate 16 (see FIGS. 3 and 4) and used to unfold from the springs 14a-14n. 2 is a perspective view 22 of a linear array 12 of photolithographic pattern springs 14a-14n after being released from the substrate 16. These springs 14a-14n may be formed into a high density array with a pitch 20 therebetween as fine as 0.001 inches.

3 is a side view 26a of a first photolithographic pattern spring 14 having a short length 28a, which spring 14 is a release region of the substrate 16 from a distance away from the flat anchor region 15. After being released at 18a, it is formed to have a first effective spring angle 30a, a spring radius 31a and a spring height 32a. 4 is a side view 26b of a second photolithographic pattern spring 14 having a long spring length 28b, which spring 14 is released from the release area 18b of the substrate 16 and then is a second view. It is formed to have a large effective spring angle 30b, a spring radius 31b and a spring height 32b. The effective shape of the springs 14 thus formed may vary depending on the desired application. In addition, these springs are usually flexible and can be used for a variety of applications.

Since the pitch of the patterned springs 14 is made very small, many springs 14 can be brought into contact with the power pad or the ground pad of the integrated circuit 44, thereby improving the current carrying capacity (Fig. 13). Also, for probe card assemblies having an array 12 of probe springs 14, a number of probe springs 14 are used to probe the I / O pads of the integrated circuit 44 under test to provide a wafer under test ( Since all springs 14 can be continually identified after connecting the springs 14 to 92, a complete electrical contact between the probe card assembly and the integrated circuit 44 is ensured before starting the test procedure.

Improved miniature spring structure.

FIG. 5 is a perspective view of opposing photolithographic springs 34a, 34b with a spring tip pattern interleaved, which spring is shaped before being separated from the substrate. 6 is a perspective view of opposite interleaved photolithographic pack springs 34a, 34b after being separated from the substrate.

There are a number of spring contacts 24 at each of the interleaved photolithographic springs 34a and 34b. When these spring contacts are used to connect to the power or ground trace 46 or pad 47 of the integrated circuit 44, the electrical resistance at the contacts is maximized. Thus, the interleaved spring 34 with multiple contacts 24 basically lowers the resistance between the spring 34 and the trace 46 or pad 47. As noted above, many interleaved probe springs 34 may be utilized in many cases, such as probe card assemblies 60 for the purpose of high quality electrical connections of the integrated circuit 44 or for finding the integrated circuit 44 during testing. (See Figure 13).

7 is a perspective view of opposing interleaved photolithographic springs 34a, 34b, which are in contact with a single trace 46 of the integrated circuit 44 under test. Each of these interleaved springs 34a and 34b has a number of contacts 24 in contact with the trace 46. As shown in FIG. 5, when a zigzag gap 38 is formed between two springs 34a and 34b on the substrate 16, a plurality of contacts 24 are set at each spring 34a and 34b. do. Prior to releasing the interleaved springs 34a and 34b from the substrate 16, the contacts 24 are located in the overlapped interleaved region 36. When the interleaved springs 34a and 34b are separated from the substrate 16, the contacts 24 are close to each other in the contact region 40 formed between the springs 34a and 34b. Next, the interleaved springs 34a and 34b are placed in contact with the same trace 46 of the integrated circuit 44 to improve reliability. In addition, since each of the interleaved springs 34a and 34b includes a plurality of contacts 24, the contact with the trace 46 is improved while minimizing the possibility of overheating or current arcing at the plurality of contacts 24. do.

FIG. 8 is a plan view of parallel opposing single-projection photolithographic springs 14 prior to releasing the springs 14 from the substrate 16. As described in interleaved springs 34a and 34b, parallel springs 14 may be disposed such that contacts 24 contact a single trace 46 of integrated circuit 44. In addition, the opposing springs 14 may be superimposed on each other on the substrate 16 so that when the release region 18 is released from the substrate 16, these contacts 24 may be disposed in close proximity to each other. 9 is a plan view of the parallel opposing monolithic photoless graphic springs 14 after releasing the spring 14 from the substrate 16, wherein the parallel opposing monolithic photolithographic springs 14 are integrated circuits. A single pad 47 of 44 is in contact.

FIG. 10 is a top view of the shoulder-projection photolithographic spring 50 with the projection 52 protruding from the shoulder 54. FIG. 11 is a partial cross-sectional view of shoulder-projection photolithographic spring 50 in contact with trace 46 of an integrated circuit. 12 is a perspective view of a multiple shoulder-projection photolithographic spring 50. The single projection springs 14 typically have good physical contact with the conductive trace 46 of the integrated circuit 22, which allows a single sharp contact to penetrate the existing oxide layer on the trace 46 or the pad 47. Because. However, if the trace 46 or pad 47 is a thin or relatively soft integrated circuit or semiconductor wafer 92, the contacts 24 may penetrate through the trace 46 and into the IC substrate 48 or other circuitry. Can be.

Thus, the shoulder-projection photolithographic spring 50 has one or more projections 52 and one shoulder 54, which projections penetrate sufficiently to make good electrical contact with the traces 46, Shoulder 54 prevents spring 50 from penetrating too deep into device 44 or wafer 92. Since the shape of the probe spring 50 can be highly controlled by the photolithographic screening or etching process, the detailed shape of the shoulder-projection photolithographic spring 50 can be obtained in advance.

Improved probe card assembly.

13 is a cross-sectional view 58 of the probe card assembly 60a, in which a plurality of electroconductive probe tips 61a-61n are disposed on the lower probe face 62a of the substrate 16. On the upper connector face 62b of the substrate 16 are located a number of flexible electroconductive connectors 64a-64n, each of which has a number of electroconductive spring probe tips via corresponding electrical connectors 66a-66n. 61a-61n).

The substrate 16 is usually a solid plate, and is preferably made of a material having a low coefficient of thermal expansion such as ceramic, ceramic glass, glass, or silicon. When the probe card assembly 60a and the semiconductor wafer 92 are positioned together, electrical contact is made between the probe card assembly 60 and the semiconductor wafer 92 by the electroconductive spring probe tips 61a-61n. .

The spring probe tips 61a-61n may have various shapes such as the protruding spring 14, the interleaved spring 34, the shoulder-protruding spring 50, and the like, and are generally formed on the substrate 16 using a thin film or MEMS process. In addition, the manufacturing cost can be lowered, and the pad pitch 20 can be formed very uniformly and precisely, and the number of pins can be greatly increased.

These probe tips 61a-61n are electrically connected to flexible electrical connectors 64a-64n through metal connectors 66a-66n in the substrate 16. Each of the plurality of flexible connectors 64a-64n is electrically connected to a printed circuit board probe card 68, which is secured in place by a metal ring or frame support structure 70. Preferred metal electrical connectors 66a-66n, produced by Micro Substrate Corporation, Tempe, Arizona, are typically formed by drilling holes in the substrate 16 using a laser or other perforation method. These holes are filled or plated with a conductive metal by plating or extrusion. After the conductive connectors 66a-66n are formed, they are polished and processed into a flat and smooth surface.

14 is a partially enlarged cross-sectional view 79 of the probe card assembly 60a, showing a printed circuit board probe card 68 and substrate 16. Probe tips 61a-61n are typically arranged at a fine pitch 20 on the probe surface 62a of the substrate. The fixed anchor regions 15 extend up to the connectors 66a-66n, which are arranged in pitch 81. Conductive connectors 64a-64n disposed on the upper connector face 62b of the board 16 and connected to the connectors 66a-66n are arranged with connecting pitches 83, which pitches may coincide with the pitch 81. It may be possible or wider at the upper connector surface 62b of the substrate 16.

The conductive pads 77a-77n on the bottom of the printed circuit board probe card 68 are typically arranged at a pad pitch 85 to align with the conductive connectors 64a-64n located on the upper connector surface 62b of the substrate 16. do. These conductive pads 77a-77n are spread with conductive paths 78a-78n arranged at the probe card pitch 87. The conductive connectors 72a-72n disposed on the top surface of the printed circuit board probe card 68 and connected to the conductive paths 78a-78n are arranged at the probe card connector pitch 89, which is the probe card pitch 87 ) Or more on the top surface of the printed circuit board probe card 68. It is preferable to select the probe card connection pitch 89 so that the test head connectors 74a-74n and the conductive connectors 72a-72n aligned with the test head pitch 91 and aligned with the test head 76 are aligned. Do.

Typically, flexible electrical connectors 64a-64n are formed using spring lengths 28 longer than the probe tips 61a-61n to give 4-10 mm compliance. In some cases, flexible connectors 64a-64n are formed to conform to the photolithographic spring as described in US Pat. No. 5,848,685 or 5,613,861, which is incorporated herein by reference.

The flexible connectors 64a-64n are permanently connected (by solder or conductive epoxy) to the printed circuit board probe card 68, or a corresponding metal coupled to the contacts 24 of the flexible connector 64a-64n. By the pad) is temporarily connected. Next, signals are inputted by the printed circuit board probe card 68 to a pad pitch 89 suitable for the standard pin connectors 74a-74n arranged in the test head 76 as the test head pitch 91. 72n).

The flexible connectors 64a-64n are preferably arranged in an array region having an array pitch 83, such as 1.00 mm or 1.27 mm, such that the pitch is a plated through hole on the printed circuit board probe card 68. Providing an appropriate density for the plated through-hole (PTH) and spreading the signal in multiple layers within the printed circuit board probe card 68 irrespective of the printed circuit board probe card 68 including the conductive paths 78a-78n.

The flexible conductive connectors 64a-64n in contact with the conductive pads 77a-77n at the bottom of the printed circuit board probe card 68 maintain the electrical connection between the printed circuit board probe card 68 and the substrate 16. In addition, the substrate 16 may slide up and down along the Z axis 84 and may be inclined with respect to the center line thereof. The flexible connectors 64a-64n also provide lateral compliance between the printed circuit board probe card 68 and the substrate 16, which have different coefficients of thermal expansion (the coefficient of thermal expansion is lower on the substrate and relatively high on the probe card).

In addition, the substrate 16 may be an assembly such as a membrane probe card, which is connected to the printed circuit board probe card 68 through the membrane bump connectors 64a-64n. In another example of a probe card assembly, the connectors 64a-64n may be provided as a detachable connector 132 (see FIG. 18) or as a MEG-Array connector 162 of FCI Electronics of Etters, PA. (See FIG. 24), wherein ball grid solder arrays disposed on opposite halves of connectors 132 and 162 are soldered to corresponding conductive pads on substrate 16 and in-circuit board probe card 68, these conductive pads. Are each arranged in the area array pattern, so that each of the plurality of spring probe tips 61a-61n and the plurality of conductive pads 77a-77n on the bottom of the printed circuit board probe card 68 at the corresponding halves of the connectors 132,162. Multiple electrical connections are made between each.

As the size and design of the integrated circuit 44 become smaller and more complicated, the importance of the fine pitch 20 between the miniature spring probe tips 61a-61n becomes increasingly important (see FIG. 2). Further, as the integrated circuit 44 and the required probe card test assemblies become smaller, the difference in flatness between the integrated circuit 44 and the substrate 16 including many spring probe tips 61a-61n becomes important.

The probe card assembly 60a is electrically connected to the substrate 16, which may include thousands of spring probe tips 61a-61n, and these probe tips provide a suitable mechanical support for the probe card assembly 60a. It functions effectively in a typical integrated circuit test probe environment. The probe card assembly 60a is easily used when it requires very many pins or when the pitch is tight or the frequency is high. In addition, the probe card assembly 60a is configured to close all traces 46 (see FIG. 7) and I / O pads 47 of the integrated circuit in case of a test probe that needs to be connected to the center portion of the integrated circuit 44. Easily adapted for electrical connection.

As shown in FIG. 13, the probe card assembly 60a is positioned relative to a semiconductor wafer 92 having one or more integrated circuits 44, which are typically separated by a grating 94. The X-axis 80 and the Y-axis 82 determine the position of the probe card assembly 60 relative to the semiconductor wafer 92 and the integrated circuit 44, the X-axis the surface of the wafer 92 and the probe card assembly ( Determine the vertical gap between 60). The position of the wafer 92 relative to the test head 76 and the probe card assembly 60a is centered on the Z axis 84 as well as on the X axis 80, Y axis 82, and Z axis 84. It should be precisely positioned with respect to the Z axis rotation θ.

However, while the importance of contacting the probe card assembly to the flatbed semiconductor wafer 92 is gradually increasing, the semiconductor wafer 92 and the probe card assembly are not slightly flat with each other, such as X-axis rotation 86 and / or It fluctuates slightly during Y axis rotation 88.

Since the probe tips 61a-61n are flexible in the probe card assembly 60a shown in FIG. 13, there is flat compliance between the substrate 16 and the semiconductor wafer 92. In addition, due to the flexible connectors 64a-64n, which are flexible conductive springs 14, 34, 50, the flatness compliance between the substrate 16 and the wafer 92 becomes greater. Thus, the probe card assembly 60a ensures flat compliance between the substrate 16 and the integrated circuit 44 (ie, between the X-axis rotation 86 and / or Y-axis rotation 88). In addition, the probe card assembly 60a may cover the difference in coefficient of thermal expansion between the substrate 16 made of ceramic, cerium film glass, glass, or silicon and the printed circuit board probe card 68 made of glass epoxy material.

Signal traces from probe tips 61a-61n with small pitch 20 typically use both sides 62a and 62b of substrate 16 or traces on one side to flexible connectors 64a-64n with large pitch. It happens

These flexible connectors 64a-64n are preferably placed on a standardized layout pattern, which is consistent with the standardized power and ground pad patterns (ie, assignments) on the printed circuit board probe card 68. The same printed circuit board probe card 68 can be used for the substrate 16 that is placed to be coupled to another integrated circuit 44. Since the printed circuit board probe card 68 may be applied to a special substrate 16, the operating cost of the printed circuit board probe card 68 is reduced for testing the various integrated circuits 44.

To aid in ultra-high frequency power separation, it is desirable to mount a capacitor 172, such as the LICA series capacitor sold by AVX Corporation of Myrtle Beach SCd, on the top surface 62b of the substrate 16 (see FIG. 24). Otherwise, a parallel plate capacitor may be formed in the substrate 16 between the surface formed in the non-use area of the routing trace layer and the reference surface. When the substrate 16 is made of silicon, it is desirable to form an integral capacitor 67 (such as an integral bypass capacitor) between the processed diffusion layers in the silicon substrate 16.

The wafer chuck is typically aligned with the substrate 16 to align the pitch 20 of the probe tip with the contact pads 47 or traces 46 of the integrated circuit 44 disposed on the semiconductor wafer 92. Use up and down cameras. Alignment is typically accomplished by observing the contacts 24 or by examining the alignment marks 125 printed on the substrate 16.

In the case of probe camera assemblies without such a camera, it is desirable to form the substrate 16 with a transparent material such as glass ceramics or glass so that the test operator can perform the visual observation alignment method. While it is desirable to form a window 165 in the printed circuit board probe card 68 (see FIG. 24), it is desirable to form alignment marks 125, 185 in the substrate and / or the wafer 92 under test (FIG. 17, 26). Next, the test operator observes the alignment mark 125 through the window using a camera or a microscope, and aligns the substrate 16 with the wafer 92.

If connection to the surface of the semiconductor wafer 92 is required while maintaining the probe contact (by a voltage-contrast electron beam, etc. probed during the development of the integrated circuit 44), the window 123 is placed on the substrate 16 on the center of the IC. It is preferable to form and observe the signal in the wafer 92 (see FIG. 17). The window 123 is best if I / O pads are disposed along the edge to directly probe the integrated circuit 44 on the wafer 92. Currently, the semiconductor wafer 92 must be first stamped and then the separate integrated circuits 44 wirebonded in a packaged form to be tested.

The window 123 formed on the substrate 16 is preferably used to repair the electron beam in the original position, such as DRAM, and at this time, the probe card assembly 60 may be held in the original position. Therefore, the test, repair and retest can be performed at the same position without moving the wafer 92.

The structure of the probe card assembly 60a results in a very short electrical distance between the controlled impedance environment within the printed circuit board probe card 68 and the probe tips 61a-61n, which is why the probe card assembly 60a is It can be used in the case of high frequency. If it is necessary to control impedance on both sides 62a and 62b or traces of one side of the substrate 16, one or more conductive reference plates may be added to the substrate 16 either above, below, or below the trace. For very high frequencies, the substrate 16 may also include other ground reference traces, which are connected to one or two reference planes 262a and 262b at regular intervals using the path 266 (see FIG. 37). .

Highly compliant probe assembly.

As described above, the probe card assembly 60 firmly supports the substrate 16 in the X and Y directions in the rotational direction 90 about the printed circuit board probe card 68 as well as in the X axis 84.

The flexible spring probe tips 61a-61n, as well as the flexible connectors 64a-64n, produce some degree of flatness compliance between the probe card assembly 60 and the semiconductor wafer 92 or integrated circuit 44. On the other hand, according to other preferred embodiments of the probe card assembly 60, its flatness compliance is further improved.

For some probe cards that require substantial flat compliance, the probe tips 61a-61n may have to be very small to provide high density connections and fine pitch 20, so compliance with these probe tips alone may be insufficient. have. Thus, in some preferred cases of the probecard assembly 60, the probecard assembly 60 causes the substrate 16 to pivot about its center (ie, X-axis rotation 86 and / or Y-axis rotation 88). ), The flatness of the semiconductor wafer 92 can be improved. In this case, the probe card assembly 60 must continue to apply downward force in the direction of the Z axis 84 to couple the probe tips 61a-61n of the bottom surface 62a of the substrate 16 to the wafer 92. do.

In many cases of the probe card assembly 60, the center portion 119 of the substrate 16 is used for electrical connectors 64a-64n between the substrate 16 and the printed circuit board probe card 68, so that the substrate (16) It is necessary to support the substrate 16 along the edge 127 (see Fig. 17).

A ball joint lever point structure may be positioned at the center of the probe card assembly behind the substrate support structure to pivot the substrate 16 about its center and apply force to the probe tips 61a-61n. However, this structure usually interferes with wire leads or other electrical connections and therefore needs to be removed from the center of the probe card assembly. Moreover, the Z-axis rotation 90 of the board | substrate 16 does not limit in such a movable joint.

FIG. 15 is a first partial cross-sectional view 96a of a bridge and leaf spring supported probe card assembly 60b. FIG. 16 is a second partial cross-sectional view of the bridge and leaf spring supported probe card assembly 60b shown in FIG. 15, showing one or more integrated circuits on a semiconductor wafer 92 that are not coplanar with the probe card assembly 60b. Flatness compliance with 44). 17 is a partial exploded view of the main components for the bridge and leaf spring probe card assembly 60b.

The leaf spring 98 is connected to the substrate 16 via a bridge 100. The substrate 16 freely pivots in the directions of the Z-axis 84, the X-axis 80, the Y-axis 82, and the Z-axis rotation 90 by the leaf spring 98 and the bridge 100. In a preferred embodiment, the preload assembly 121 is used as a means for accurately setting the initial surface and Z position of the substrate 6 and the preload force of the leaf spring 98 with respect to the printed circuit board probe card 68b. (See FIG. 15). For example, in the embodiment shown in FIGS. 15 and 16, preload assembly 121 includes fasteners 118, which are used with bridge wedges 122. In other embodiments, the preload assembly 121 may include a calibration screw 118.

As illustrated in FIGS. 15 and 16, the printed circuit board probe card 68 is attached to the outer edge of the leaf spring 98 by the connecting frame 107. The bridge 100 is connected to the center of the leaf spring 98 by one or more fasteners 108, an upper bridge spacer 104, and a lower bridge spacer 106. It is desirable to add a bridge preload wedge 110 to vary the Z-axis spacing between the leaf spring 98 and the bridge 100, which is then applied downward to the bridge 100 by the leaf spring 98. Force changes. The bridge structure 100 transfers its bearing force from the center to the edge and is connected to the substrate 16 via a plurality of bridge legs 102 (usually three or more). These bridge legs 102 protrude through the through holes 111 formed in the printed circuit board probe card 68 and are firmly connected to the substrate 16 by adhesives or mechanical connectors 112.

The leaf spring 98 is usually made of stainless steel or spring steel and patterned using chemical etching. The downward force is a function of the rigidity of the spring, the diameter of the spring spacers 104 and 106 as well as the size of the leaf spring 98.

The leaf spring 98 shown in FIG. 16 is a cross sectional view, but other geometries may be used to provide downward force, tilt freedom, and X, Y, Z translation resistance. For example, the leaf spring 98 may have multiple wings 99. In addition, these wings 99 may be asymmetrical, in which case the width may change from the outside to the center. In addition, the ring spring may be connected to the outer edge of the leaf spring 98 to further stabilize the leaf spring.

The bridge 100 and the spacers 104 may be made of a light and strong metal such as aluminum or titanium to minimize the mass of the probe card assembly 60b.

The substrate 16 is attached to the leg 102 of the bridge 100 using an adhesive 112 such as epoxy or solder. If the board needs to be replaced, a disconnect connector 130 as shown in FIG. 18 can be used.

It is preferable to use the lower insulator 114 on the bottom surface 62a of the substrate 16 so that the substrate 16 does not touch the wafer 92. The lower isolator 114 is preferably made of a relatively soft material such as polyimide to prevent breakage of the semiconductor wafer 92. In addition, to prevent damage to the integrated circuit 44 in the wafer 92, the probe card assembly 60 is aligned with the integrated circuit 44 on the wafer 92 in the absence of a test structure such as the integrated circuit 44. When the isolators 114 are aligned with the separation line 94 on the semiconductor wafer 92, it is preferable to arrange the isolators 114. In addition, the height of the lower isolator 114 is preferably selected to limit the maximum compression of the probe tips (61a-61n) to prevent breakage of these tips.

An upper isolator 116 is also disposed on the top surface 62b of the substrate 16 to prevent breakage of the top flexible electrical connectors 64a-64n. These upper insulators 116 are preferably made of a hard insulating material such as LEXAN, silicon, plastic, or the like.

In the preferred embodiment shown in FIGS. 15, 16, and 17, the adjustment stop screw 118 and the bridge wedge 122 are used to set the initial plane of the substrate 16 as well as to provide a downward stop on the substrate 16. It is provided to prevent breakage of the flexible connectors 64a-64n due to overload.

Since the printed circuit board probe card 68b is made of a soft material such as glass epoxy, the crush pad 120 is disposed on the probe card 68b under the adjusting screw 118 so that the tip of the adjusting screw 118 is repeated. It is desirable to prevent penetration into the printed circuit board probe card 68b in a contact cycle. In addition, by using the bridge wedge 122 together with the adjustment screw 118, it is possible to accurately set the initial spacing and flatness between the substrate 16 and the probe card 68b.

The preload wedge 10 is used to adjust the initial preload of the downward force exerted on the bridge 100 by the leaf spring 98. This set evi load prevents vibration of the substrate 16 and improves contact characteristics between the substrate and the wafer 92.

18 is a first partial cross-sectional view 126a of another bridge / spring suspension probe card assembly 60c, in which an intermediate lower card 134 is detachably connected to the in-circuit board probe card 68b, and the bridge 100. The substrate 16 is detachably connected to the substrate 16. FIG. 19 is a second partial cross-sectional view 126b of the probe card assembly 60c shown in FIG. 18, basically one or more integrated circuits 44 on the semiconductor wafer 92 that are not coplanar with the probe card assembly 60c. ) Gives flatness compliance.

It is desirable to use a disconnect connector 132 to replace the substrate 16. Substrate connection fasteners 130, such as, but not limited to, screws, protrude from the bridge legs 128 to detachably connect the bridge 100 to the substrate posts 128, wherein the substrate posts 16 is mounted on the upper surface 62b.

In one embodiment of the probe card assembly 60, the detachable connector 132 is preferably a MEG-Array connector manufactured by FCI Electronics of Etters, Pennsylvania. One side of the detachable connector 132 is soldered to the printed circuit board probe card 68, and the coupling side is soldered to the lower card 134, while the lower card 134 is detachably connected to the probe card 68b. It is common to provide a reliable electrical connection. This subcard 134 is electrically connected from a pitch of about 1 mm for flexible connectors 64a-64n to a common pitch of about 1.27 mm for the detachable connector 132. Open up.

20 is a cross-sectional view 136 of a wire / spring post suspended probe card assembly 60d. A plurality of steel wires 138 (usually three or more) allow the substrate 16 to move on the Z axis 84. The spring pillar frame 140, which is usually soldered or epoxy bonded to the printed circuit board probe card 68c, has one or more spring pillars 141, which pillars provide downward force in the Z direction as well as limit the movement thereof. do.

21 is a cross-sectional view 142 of a suspended probe card assembly 60e having an intermediate subcard 134 detachably connected to a printed circuit board probe card 68 by a detachable connector 132. The flexible connectors 64a-64n are made of springs 14, 34, 50 and provide a mechanical connection between the probe card 68 and the subcard 134 as well as providing an electrical connection to the printed circuit board probe card 68. Provide a connection. In the probe card assembly 60e, the flexible connectors 64a-64n are permanently connected to the conductive pads 143a-143n on the lower card 134 by solder or conductive epoxy. The flexible connectors 64a-64n are preferably designed to generate a force greater than the force required to compress the entire probe tip 61a-61n at the bottom when compressed to 2-10 mm. Further, as the flexible connectors 64a-64n are compressed, it is preferable to arrange the flexible connectors 64a-64n so that the substrate 16 does not move in the X and Y directions and does not rotate about the Z axis.

The upper substrate isolator 116 is preferably used to protect the flexible connectors 64a-64n by limiting the maximum Z-axis movement of the substrate 16 relative to the lower card 134. In addition, by applying a slight preload to the flexible connector (64-64n) to drop the substrate 16 from the lower card 134, the upper isolator 116 to reduce the vibration or shaking of the substrate 16 during operation It is desirable to be able to make adjustments. It may be desirable to place a buffer material 145, such as a gel, in one or more places between the substrate 16 and the lower card 134 to prevent vibration or shaking of the substrate 16.

The detachable connector 132, such as an FCI connector, preferably provides a fine flatness compliance between the lower card 134 and the probe card 68 in compliance with the same flat coupling condition. Mechanical adjustment mechanism 149 such as, but not limited to, fasteners 166, spacers 164, nuts 168, wedges 170, and the like, may be provided between the lower card 134 and the probe card 68. FIG. It may be desirable to use (see FIG. 24).

FIG. 22 is a cross-sectional view 146 of the probe card assembly 60f, where the substrate 16 is attached to the printed circuit board probe card 68 through the detachable array connector 147. The probe card assembly 60f is suitable for the small substrate 16, and in this case, minor non-flatness between the substrate 16 and the wafer 92 can be absorbed only by the probe tips 61a-61n.

FIG. 23 is a cross-sectional view of a springwire suspended probe card assembly 60g, wherein the nano-spring substrate 16 is printed circuit board probe card 68 through a large grid array (LGA) intermediate connector 150. FIG. Attach to. In one embodiment, the LGA intermediate connector 150 uses an AMPIFLEX connector manufactured by AMP, Inc. of Harrisburg, PA. In another example, W.L. of Eau Clare, Wisconsin. Use the GOREMATE connector manufactured by Gore and Associates, Inc. In another embodiment, the spring pin intermediate connector 150 is used to connect the opposing spring pins 152 on the printed circuit board probe card 68 to the electrical connectors 66a-66n on the substrate 16. The substrate 16 is secured by a number of strong spring suspension wires 154, which wires provide a slight upward force to prevent vibration or shaking of the probe card assembly 60g while retaining the connector 150. It is desirable to be.

Probe assembly with small test area.

24 shows a small test area probe card in which one or more area array connectors 162 are disposed between a sub card 134 attached to a spring probe substrate 16 having a small main test area and a printed circuit board probe card 68. It is sectional drawing of the assembly 60h.

Although the various probecard assemblies 60 described above have a high flatness compliance to the substrate 16, some probecard assemblies are used when the surface area of the devices under test is relatively small. For example, for the wafer 92 having a relatively small number of integrated circuits 44, the size of the substrate 16 can be made smaller than 2 cm 2.

Thus, in this case, the flatness of the substrate 16 with respect to the wafer 92 is less important than the case where the surface area is large, and compliance with the probe tips 61a-61n alone is sufficient to compensate for the test environment. If the compliance by the probe tips 61a-61n is relatively small compared to the general needle springs, the probe tips 61a-61n are suitable for the probe card assembly 60 formed by the MEMS method or the photolithographic method.

Thus, this probe card assembly 60h is basically less complex and cheaper than a multilayer probe card assembly. The small size of the substrate 16 can lower the price of the probe card assembly 60h, since the price of the substrate 16 is highly dependent on the surface area.

As described above, the probe tips 61a-61n are formed on the bottom surface 62a of the rigid substrate 16 by using a thin film processing method or a MEMS processing method. Probe tips 61a to the array of metal pads 182, 184, 186 on the top surface 62b of the substrate 16 using connectors 66a-66n or both sides 62a, 62b or metal traces on one side that penetrate the substrate 16. Signals from -61n) are unfolded (see FIG. 26). The upper pads are connected to the lower card 134 through common microball grid solder array pads with an array pitch of 0.5 mm. This subcard 134 further spreads the array pitch up to pads having a pitch of about 0.050 inches on opposite sides of the subcard. An array connector 162, such as a MEG-Array connector manufactured by FCI Electronics Inc. of Etters, Pennsylvania, is used to connect a pad array with a pitch of 0.050 inches to the printed circuit board probe card 68. It is desirable to add a power bypass capacitor 172, such as a LICA capacitor manufactured by AVX Corporation of Myrtle Beach SC, to the subcard 134 close to the micro-BGA pads 182, 184, 186 of the substrate to provide low impedance power filtering. Do.

The probe card assembly 60h having a small test area includes means for providing a mechanical connection between the printed circuit board probe card 68 and the lower card 134. In the case of the probe card assembly 60h shown in FIG. 24, one or more spacers 164 and wedges 170 are aligned at a controlled distance between the subcard 134 and the probe card 68, and the one or more spacers are arranged at a controlled interval. The fastener 166 and the nuts are provided as mechanical connecting means. Although the spacer 164, the wedge 170, the fastener 166, and the nut 168 are shown in FIG. 24 in combination, in the case of the probe card assembly 60h having a small test area, the lower card 134 and the probe card are shown. Any connection means such as, but not limited to, spring-loaded fasteners, gluing means, other fittings, or the like may be used between the 68 and 68.

The lower substrate isolator 114, which protrudes from other components except for the spring tips 61a-61n on the substrate 16, is disposed on the bottom surface 62a of the substrate 16 and the grid 94 of the wafer 92. Arranged to coincide, the wafer 92 is prevented from penetrating into the substrate 16 and the breakage of the active area of the wafer 92 is prevented.

As shown in FIG. 24, it is preferable that the connection hole 123 is provided in the substrate 16 (see FIG. 17), the lower card connection hole 163 is also present in the lower card 134, and the printed circuit board probe card 68 is provided. ), There is also a probe card connection hole 165, so that the probe card assembly 60h can be positioned on the wafer 92 while being able to connect to the semiconductor wafer 92 so that it can be visually aligned or can be electron beam probed. These connection holes 123, 163, and 165 may be used anywhere in the probe card assembly 60.

25 is a plan view of a substrate wafer 174, in which a plurality of microball grid array spring probe contact chip substrates 16 are disposed. For these spring probe substrates 16 with small surface area, several spring probe contact chip substrates 16 can be fabricated from one wafer 174. For example, as shown in FIG. 25, 24 having a width 176 and a length 178 can be formed on a 4 inch round initial wafer 174 having an area of about 14 microns. In addition, other substrates 16a and 16b may be formed on the initial wafer 174 to jointly bear the masking and processing costs (which may be significantly larger) for the substrate 16. Therefore, the development cost of the other substrates 16a and 16b can be significantly reduced (up to 10% or more).

FIG. 26 is a plan view of a single microball grid array 180 with a pitch of 0.5 mm for an area 14 micron spring probe contact chip substrate 16b. It is desirable to arrange the micro BGA pads 182, 184, 186 at a standard pitch (0.5 mm). The outer five rows of pads 182 and center pads 184 provide 341 signal connections, and the inner two rows of pads 186 provide 96 dedicated power / ground connections. Routing traces for the probe tips 61a-61n can be tailored to accommodate specific power / ground spring locations in one routing layer to match the integrated circuit 44.

It is preferable to arrange the insulator 114 on the lattice line 94 which is an inactive region of the wafer 92 to prevent breakage of the integrated circuit 44. One or more alignment marks 185 are disposed on the substrate wafer 174. Standardizing the micro BGA pad array 180, the lower card 134, and the printed circuit board probe card 68 can significantly reduce the manufacturing cost of the probe card assembly 60. Standardizing the power / ground pad distribution for the pads on the substrates 16, 134, 68 as well as the micro BGA pad array 180 can normalize the pattern of connectors 66a-66n in the substrate 174.

Standardizing other portions of the probe card assembly 60 allows the use of a printed circuit board probe card 68 (in some cases including a sub-card 134) for other substrates 16 and integrated circuits 44, wherein the substrate You only need to adjust the routing in (16). Initial substrates 174 with standardized connector 66a-66n patterns can be used to order, store, and use these substrates in large quantities, saving cost and reducing board purchase time.

Other Application of Probe Spring

Photographic or MEMS spring probes for bare die burn-in sockets, such as DieMata burn-in sockets from Texas Instruments Inc. of Mansfield, Massachusetts or Die Pak burn-in sockets sold by Aehr Test Inc. of Fremont, CA (61, 14, 34, 50) can also be used. For the bare die burn-in socket contacting the substrate 16 around the edge, the probe spring 61 is formed only on one surface 62a of the substrate 16, and expansion metallization is required. The necessary extension is used to determine the size of the substrate 16 based on the number of I / O signals that need to be connected to the feeds at the edge of the substrate 16. On the other hand, as described above, the probe spring 66 in the substrate 16 is used to connect the I / O signal to the pad array on the opposite side 62b of the substrate 16, further miniaturizing the substrate and reducing the manufacturing cost. can do.

Tiled Probe Assemblies

27 is a plan view 190 of a tiled probe strip 192 having a probe strip length 198 and a probe strip width 200. Tile probe strip 192 is a plurality of probe strip contact areas 194a-. 194n, each region has a plurality of spring probe tips 61a-61n. Further, in the illustrated embodiment, the spring probe tips 61a-61n are disposed in the longitudinally aligned probe regions 196a, 196b. The use of one or more tiled probe strips 192 in the probe card assembly allows for simultaneous electrical contact with multiple integrated circuits 44 to test the connection of integrated circuits 44 on semiconductor wafer 92. Can be achieved. The plurality of probe strip contact regions 194a-194n is preferably disposed symmetrically along the length of the tiled probe strip 192 to align with the plurality of symmetric integrated circuits 44 on the wafer 92.

Further, the tiled probe strip 192 with spring probe tips 61a-61n includes an electrical connector 66a-66n and an electrical connector 64a-64n array (see FIGS. 1, 17, 21), While arranging the probe tips 61a-61n to match the integrated circuit 44 under test, the probe strip 192 includes standard electrical connectors 66a-66n and / or arrays of electrical connectors 64a-64n. . For example, in the probe card assembly 202 shown in FIGS. 28 and 29, each of the tiled probe strips 192 includes a standard ball grid array 160 of solder connections. Therefore, the preferred embodiment of the tiled probe strip 192 includes spring probe tips 61a-61n that lie to match the particular integrated circuit 44 under test, while the probe strips 192 are standard subcards. 204 and / or a standard intermediate connector (eg, detachable connector 132), to minimize engineering development costs for producing tiled probe assembly 202.

FIG. 28 is a partial bottom view of a tiled probe head 202 that includes a plurality of tiled probe strips 192 attached to a support substrate 204 that includes an array 207 of conductive paths 205 (FIG. 29). Reference). 29 is a side view of a plurality of tiled probe strips 192 connected to a probe card used to connect to a plurality of integrated circuits 44 disposed on a semiconductor wafer 92. The tiled probe head 202 is used to connect to a number of integrated circuits 44 disposed on the semiconductor wafer 92. The plurality of tiled probe strips 192 are typically disposed symmetrically on the substrate 204 to align with the plurality of symmetric integrated circuits 44 on the wafer 92.

The substrate 204 has a low coefficient of thermal expansion (TCE) and is made of silicon. In addition, the plurality of signal traces 46 of the substrate 24 are connected to the connectors of the opposite side 209b. In one embodiment, the substrate 204 is a silicon wafer, which includes paths 205a-205n arranged at a pitch of 0.056 inches and thin film traces 46 on one or both sides of the substrate 209a and 209b.

In the tiled probe head 202 shown in FIGS. 28 and 29, the tiled probe strips 192 are a plurality of probe springs 61 used to contact pads 47 disposed on either side of the integrated circuit 44. It includes. In the tiled probe head 202 shown, one of the probe strips 192 contacts the right side of the integrated circuit 44 (using the probe contact region 196a of FIG. 27) and the probe contact region of FIG. Probe strip 192 is arranged to contact the left side of adjacent integrated circuit 44 (using 196b). Thus, the embodiment shown in FIG. 28 allows for adequate error between the tiled probe strip 192 while simultaneously connecting the plurality of probe strips 192 and the plurality of integrated circuits 44 at the same time. In this case, the side edges of the tiled probe strips 192 may be placed on the lattice lines of the integrated circuit 44. For example, the width of the grid lines 94 between adjacent integrated circuits 44 is 4-8 mm, and the spacing between the tiled probe strips 192 of the tiled probe head 202 can be similar.

In another example of tiled probe head 202, all pads of integrated circuit 44 may be connected by a probe from one probe strip 192.

Burn-in structure.

30 is a partial perspective view of a burn-in structure 210 capable of temporarily connecting a plurality of integrated circuits 44 to a burn-in board 212. An array of probe spring (ie, nano-spring) contactor chip (NSCC) substrates 214 is mounted to the burn-in board 212, such as through a microball grid array 216, and multiple integrations by these arrays 216. An electrical connection is made between the circuit and an external burn-in circuit (not shown). The board vacuum ports 218 are formed on the burn-in board 212, and the contactor chip vacuum ports 220 are formed on the NCSS substrate 214. The board vacuum ports 218 are generally the contactor chip vacuum ports. Aligned with the field 220, a vacuum through the vacuum port 238 is applied to the vacuum port 220. An air seal 222 made of epoxy or the like is disposed around each nanospring contact chip substrate 214 to prevent loss of vacuum through the BGA ball array 216.

As the integrated circuit 44 is positioned on the NCSS substrate 214 by an adsorber or the like, the integrated circuit is vacuumed through the board vacuum port 218 of the burn-in board 212 and the vacuum port 220 of the substrate 214. 44 will not be out of position.

Once all of the integrated circuits 44 are placed on the substrate 214, it is desirable to position the clamp plate 224 in contact with the integrated circuits 44 to hold the integrated circuits in place during burn-in operation. Each spring pad 226 may be used to press the integrated circuit 44 under test to allow flatness of the clamp plate 224 and the burn-in board 212. The burn-in structure 210 includes a means 217 for securing the clamp plate 224, so that the clamp plate 224 is connected to the burn-in board 212 once the clamp plate 224 is in contact with the integrated circuit 44. It is good to connect and allow the applied vacuum to be off.

Protective coating to improve spring probe.

As described above, the spring probes 61 are widely used because they have advantages such as precise pitch, high pin count, and flexibility. However, when these small spring probes 61 are used to connect to the traces 46 of the integrated circuit 44 on the semiconductor wafer 92 (these traces often include an oxide layer), the spring probes may have an oxide layer. It must be penetrated properly and electrically connected to metal traces or conductive pads. The more the spring probes 61 are used, the smaller the unprotected contacts wear out. Therefore, it is preferable to apply conductive wear coating to the contacts 24 of the probe springs 61. However, this protective coating must be made over the front of the contacts.

As described above, the probe springs 61 may be formed by plasma chemical vapor deposition / photolithographic processing described in US Pat. Nos. 5,848,685 and 5,613,861, wherein a series of conductive layers are formed on the substrate and then the non-flat springs Is formed. In this process, however, the protective coating formed during the deposition process does not completely coat all surface areas of the non-flat probe spring.

The probe springs 61 are not flat to the substrate after release. Therefore, the protective coating may be applied after the spring 61 is released in the release region 18. FIG. 31 shows a first step 230 of a spring probe assembly coating process, wherein a protective coating 232 is applied to a probe surface of a spring probe assembly substrate 16 having one or more non-flat probe springs 61. do. A protective layer is formed on the non-flat probe spring 61 by the spring probe assembly coating process. Such coatings may be used for a wide variety of non-planar structures, but are particularly useful for treating thin film and MEMS probe springs 61. In Fig. 31, the applied conductive protective coating is a rigid conductive material such as titanium nitride, rhodium, tungsten or nickel. The applied conductive protective coating may also be made of an inert material to provide lubrication (i.e., low coefficient of friction) to the contacts on the spring 61, thereby minimizing wear to the spring 61 as well as to the integrated circuit.

When the protective coating 233 is formed on the substrate 16 and the probe spring 61, the protective coating 233 covers both the flat and non-flat regions of the exposed surface 62 of the substrate 16. While the substrate 16 is covered with the protective coating 233 in the coating step 230, all traces on the substrate are simultaneously electrically shorted from the coating 233. Accordingly, it is necessary to pattern or partially remove the conductive coating 233 to restore the insulation between the different probe springs 61 and the respective traces. In most integrated circuit processing, the conventional photo-masking process used in planar structures is used to selectively etch conductive coatings such as titanium nitride coatings.

32 shows a second step 234 of the spring probe assembly coating process, wherein a photosensitive layer 240 of about 10 μm in thickness is applied to the second substrate 236, which substrate 236 is preferably It has isolators 238 about 30 μm high. The photosensitive layer 240 is used to protect the protective coating 233 on the non-flat portions of the probe springs. 33 shows a third step of the coating process, in which the coated spring probe assembly is carefully inserted 242 into the photosensitive layer 240 on the second substrate 236. The remaining protective coating 233 is controlled according to the depth of the photosensitive layer 240. The substrate 16 is lowered to a desired depth in the photosensitive layer 240, and the application depth of the photosensitive layer 240 on the second substrate 236 and the height of the insulator 238 are controlled. The operator may control the movement of the substrate 16 relative to the photosensitive layer 240 by controlling the application depth such as controlling the axial movement of the processing apparatus.

34 is a fourth step of the coating process, wherein the coated and partially lowered spring probe assembly is removed from the photosensitive layer 240 of the second substrate 16 (246) and gently baked, while the baked photosensitive layer ( The protective coating 233 portion of the probe spring 61 covered with 248 is left. 35 is a fifth step of the coating process, where the coated and lowered spring probe assemblies 16, 61 are etched (250) to form a portion of the substrate 16, i.e., the field region and photosensitive layer of the substrate (16). Remove the protective coating 233 from the probe spring 61 not covered with 248. 36 is a sixth step of the coating process, in which the photosensitive layer 248 is peeled off from the portion of the probe spring 61 covered with the photosensitive layer 248 to expose the protective coating 233.

Therefore, according to the non-flat probe spring coating process, a protective coating is generated at the contact 24 of the probe spring, and the portion of the substrate 16 that is not coated with the unnecessary photosensitive layer 248 and the unnecessary protective coating in the substrate 16. Etch.

Spring probe board for very high frequency applications.

As described above, the probe card assembly 60 creates a very short electrical gap between the impedance environment within the printed circuit board probe card 68 and the probe tips 61a-61n, which causes the probe card assembly 60 ) Can be used for high frequencies. The substrate 16 can also be changed for ultra high frequency. 37 is a partial cross-sectional view 260 of a very high frequency spring probe substrate 16. If it is necessary to control the impedance of both sides 62a and 62b or traces of one side of the substrate 16, one or more conductive reference planes 262a and 262b are added above or below the traces 270 of the substrate 16. can do. It may also include other ground reference traces 266a and 266b connected to the reference planes 262a and 262b to effectively provide a coaxial shielded transmission line environment 268. While the substrate 16 is usually made of ceramic, the layer 264 between the reference planes is made of a dielectric.

Although the probe card assembly systems described above, improved non-flat spring probes, and methods for fabricating the same have been described with reference to integrated circuit test probes and probe cards, such systems or techniques may be used in other devices, such as electronic components, electronic devices, burn-in devices. It is also possible to implement a connection between an integrated circuit and a substrate of a MEM device or a combination thereof.

Accordingly, while the invention has been described in detail with reference to specific embodiments, those skilled in the art will recognize that various changes and modifications may be made without departing from the spirit and scope of the appended claims.

Claims (31)

A probe card substrate having a bottom surface and a top surface, the plurality of conductors connected from the bottom surface to the top surface; A substrate having a probe surface and a connector surface, wherein the probe surface has a plurality of spring probe contact tips formed therein and a plurality of electrical connectors penetrating between each of the plurality of contact tips and the connector surface; And A plurality of flexible conductive connectors between each of the plurality of electrical connectors on the substrate and each of the electrical conductors on the bottom surface of the probe card substrate; Test the substrate against the probe card such that the substrate pivots slightly about its center and provides a support for connecting the plurality of spring probe contact tips to the surface of the integrated circuit wafer. Device. The apparatus of claim 1, further comprising: a suspension mechanism disposed between the substrate and the probe card, the suspension mechanism capable of slightly moving the substrate relative to the probe card; And And a plurality of steel wires connected between the suspension device and the substrate. And suspending the substrate with the plurality of steel wires to move the substrate perpendicular to the probe card. The method of claim 1, wherein the probe card substrate comprises a plurality of leg holes formed between the bottom surface and the top surface; A leaf spring disposed on an upper surface of the probe card substrate and having an outer portion including a central bridge connection portion and means for connecting to an external test structure; And And a bridge having a plurality of legs extending down through the plurality of leg holes of the probe card substrate and a central structure connected to the central connection portion of the leaf spring. And the substrate is attached to each of the plurality of legs of the bridge. The test apparatus of claim 1, wherein the plurality of flexible conductive connectors are springs, and the substrate is suspended supported on the probe card by these flexible conductive spring connectors. The test apparatus of claim 1, wherein the substrate is a film structure, the flexible conductive connectors are flexible flaps with contacts, and the contacts are connected to each of the electrical connectors of the probe card substrate. The test apparatus of claim 1, further comprising at least one lower substrate isolator firmly attached to the probe surface of the substrate. The test apparatus according to claim 1, further comprising a movement limiting mechanism for limiting vertical movement of the substrate with respect to the probe card. The connector of claim 1, further comprising a detachable connector disposed between the substrate and the probe card, the detachable connector having a lower half and an upper half, the lower half of the detachable connector being connected to each of a plurality of conductive connectors of the substrate. Wherein the upper half includes a plurality of electrical connectors connected to each of the plurality of electrical connectors on the bottom surface of the probe card substrate, the upper half includes a plurality of electrical connectors each of the lower half and a plurality of electrical connectors on the upper half. And the upper and lower halves are removably connected such that the contacts are removably formed between each of the electrical connectors. The substrate of claim 1, wherein the substrate comprises a plurality of holes penetrating between a probe surface and a connector surface, wherein each of the plurality of electrical connectors between each of the contact tips and each of the flexible conductive connectors is a substrate. And a conductive path located in each of the plurality of holes of the plurality of holes. The test apparatus of claim 1, wherein the substrate is electrically insulating. The test apparatus of claim 1, wherein the substrate is a dielectric. The test apparatus according to claim 1, wherein the substrate is conductive. 2. The substrate of claim 1, wherein the substrate includes a connection opening that penetrates between the probe surface and the connector surface, and when the substrate is placed on the surface of the integrated circuit wafer, the substrate can connect to the integrated circuit wafer surface through the connection opening. Test apparatus. A probe card substrate having a bottom surface and a top surface, the plurality of conductors connected from the bottom surface to the top surface; A substrate having a probe surface and a connector surface, wherein a plurality of contact tips are disposed on the probe surface, and a plurality of electrical connectors penetrating between each of the contact tips and the connector surface; And Consisting of a first half and a second half, these two halves forming a removable connection between the plurality of electrical connectors on the first half and the plurality of electrical connectors on the second half, And a plurality of electrical connectors connected to each of the plurality of electrical connectors on the substrate, and the plurality of electrical connectors on the second half are connected to each of the electrical conductors on the probe card substrate. . 15. The test apparatus of claim 14, wherein the detachable connector is an area array connector. The test apparatus according to claim 14, wherein the detachable connector is an insert connector. 15. The test apparatus of claim 14, wherein the substrate is insulative. 15. The test apparatus of claim 14, wherein the substrate is a dielectric. 15. The test apparatus of claim 14, further comprising a capacitor as an assembly on the substrate. 20. The test apparatus of claim 19, wherein the capacitor is an assembly on the substrate. 20. A test apparatus according to claim 19, wherein the substrate is made of silicon and the capacitor is an assembly in the substrate. A probe card substrate having a bottom surface and a top surface, the plurality of conductors connected from the bottom surface to the top surface; A lower printed circuit board having a bottom surface and a top surface, and having a plurality of conductors connected from the bottom surface to the top surface; A substrate having a probe surface and a connector surface, wherein a plurality of contact tips are disposed on the probe surface, and a plurality of electrical connectors penetrating between each of the contact tips and the connector surface; Consisting of a first half and a second half, these two halves forming a removable connection between the plurality of electrical connectors on the first half and the plurality of electrical connectors on the second half, A detachable connector, wherein electrical connectors are connected to each of the plurality of electrical connectors on the upper surface of the lower printed circuit board, and the plurality of electrical connectors on the second half are connected to each of the conductors on the probe card substrate; And And a plurality of flexible conductive connectors between each of the plurality of electrical connectors on the connector surface of the substrate and each of the plurality of conductors on the bottom surface of the lower printed circuit board. 23. The test apparatus of claim 22, wherein the substrate is insulating. 23. The test apparatus of claim 22, wherein the substrate is at least partially conductive. 23. The method of claim 22, wherein a plurality of leg holes are formed between the top and bottom surfaces of the probe card substrate, and a plurality of leg connection holes are formed between the top and bottom surfaces of the lower printed circuit board; A leaf spring disposed on an upper surface of the probe card substrate, the leaf spring having an outer portion and a center bridge connection portion having means connected to an external test structure; And A bridge having three or more legs extending downward through the plurality of leg holes of the probe card substrate and through the plurality of leg holes of the lower printed circuit board, and a central structure connected to the central connection of the leaf springs; More; And the substrate is attached to each of the plurality of legs of the bridge. 23. The substrate of claim 22, wherein the substrate comprises a plurality of holes penetrating between a probe surface and a connector surface, wherein each of the plurality of electrical connectors between each of the contact tips and the connector surface is in each of the plurality of holes. Test device, characterized in that the location of the electrically conductive furnace. 23. The test apparatus of claim 22, further comprising at least one lower substrate isolator securely attached to the probe surface of the substrate. 23. The test apparatus of claim 22, further comprising a movement limiting mechanism for limiting vertical movement of the substrate relative to the lower printed circuit board. Disposed between a substrate and a conductive elastic material composed of a plurality of layers having an internal stress, the conductive elastic material extending from the substrate to a spring probe assembly comprising a flat free end that is responsive to the internal stress and a fixing part attached to the substrate. In: And at least one probe tip protrudes a predetermined distance from a shoulder on the free end of the conductive elastic material, the protruding distance being determined so that the conductive elastic material penetrates the probe material as desired. Disposed between the substrate and two opposing conductive flexible spring probes composed of a plurality of layers with internal stress, each of the conductive flexible spring probes extending from the substrate to a free end and the substrate reacting to the internal stress. A spring probe assembly comprising an attached fixture, the free end having a plurality of probe tips: A spring probe assembly, wherein overlapping interleaved portions are formed on the substrate between the plurality of probe tips of the opposing conductive flexible spring probes. A method of making a probe card assembly that imparts flatness compliance to a flat wafer: Providing a probe card substrate having a bottom surface and a top surface, the plurality of conductors connected from the bottom surface to the top surface; Providing a probe substrate having a probe surface having a plurality of contact tips, a connector surface and a center portion, and having a plurality of electrical connectors penetrating the substrate between each of the plurality of contact tips and the connector surface; Establishing a plurality of conductive connectors between each of the plurality of electrical connectors on the probe substrate and each of the conductors on the probe card substrate; And Supporting the probe substrate with respect to the probe card substrate such that the probe substrate is slightly pivoted about a central portion and at the same time provides a support for connecting the plurality of contact tips to the surface of the flat wafer. Probe card assembly manufacturing method characterized in that.