KR20030083912A - The batch fabrication method of MEMS hermetic cavity structure - Google Patents
The batch fabrication method of MEMS hermetic cavity structure Download PDFInfo
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- KR20030083912A KR20030083912A KR1020020022311A KR20020022311A KR20030083912A KR 20030083912 A KR20030083912 A KR 20030083912A KR 1020020022311 A KR1020020022311 A KR 1020020022311A KR 20020022311 A KR20020022311 A KR 20020022311A KR 20030083912 A KR20030083912 A KR 20030083912A
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
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Abstract
Description
본 발명은 MEMS(Micro Electro Mechanical System, 미세기계전자복합시스템) 밀폐구조 일괄제조방법에 관한 것이다. 보다 상세하게는, 밀폐용 뚜껑 제작시 양면정렬기가 필요 없는 MEMS 밀폐구조 일괄제조방법에 관한 것이다.The present invention relates to a method for manufacturing a closed structure of a MEMS (Micro Electro Mechanical System). More specifically, the present invention relates to a MEMS sealed structure batch manufacturing method that does not require a double-sided aligner when manufacturing a sealing lid.
종래에는, 도 1 에 도시된 바와 같이 MEMS 밀폐구조 제조방법은Conventionally, as shown in Figure 1 MEMS sealing structure manufacturing method
반도체 공정에 의해 하나의 웨이퍼(1) 상(上)에 MEMS기능성 구조물을 형성하는 제 1 단계(10);A first step (10) of forming a MEMS functional structure on one wafer (1) by a semiconductor process;
구멍 가공 기술에 의해 또다른 웨이퍼(2)를 상면과 하면 중 어느 한쪽 면을 먼저 가공한 다음, 상·하면의 가공 위치를 맞추기 위해 고가의 양면 정렬기(Double Side Aligner)를 이용하여 정렬한 다음 나머지 한면을 가공하는 제 2 단계(20);Another wafer 2 is first machined by either of the top and bottom surfaces by a hole drilling technique, and then aligned using an expensive double side aligner to match the top and bottom machining positions. A second step 20 of processing the other side;
상기 MEMS 기능성 구조물 위에 상기 밀폐용 뚜껑층(3)을 접합하는 제 3 단계(30);A third step (30) of bonding the sealing lid layer (3) on the MEMS functional structure;
웨이퍼 절단기를 이용하여 칩 간의 네 군데의 경계선인 칩완전절단선(11)을 따라 완전절단(Full cutting)하는 제 4 단계(40);A fourth step (40) of using a wafer cutter to completely cut along the chip complete cutting line 11, which is four boundary lines between the chips;
와이어 본더(Wire Bonder)를 이용하여 반도체 칩과 리드프레임의 이너리드(Inner lead)를 도선으로 연결하는 제 5 단계(50)를 포함하여 이루어진다.And a fifth step 50 of connecting a semiconductor chip and an inner lead of the lead frame by a wire using a wire bonder.
도 2 및 도 3 에 도시된 바와 같이 상기MEMS기능성 구조물은 제일 하단에 기판(Substrate)(1)이 있으며, 상기 기판(1)위에 전기적 절연층(Electric isolation layer)(4)이 형성되며, 상기 전기적 절연층(4) 위에 기능성 구조물층(Functional structure layer)(5)이 형성되며, 그 위에 전극 연결용 금속패드막(Electric metal pad layer)(6)이 형성된 구조물이다.As shown in FIGS. 2 and 3, the MEMS functional structure has a substrate 1 at the bottom thereof, and an electrical insulation layer 4 is formed on the substrate 1. A functional structure layer 5 is formed on the electrical insulation layer 4, and an electrical metal pad layer 6 for electrode connection is formed thereon.
상기 밀폐용 뚜껑(3)을 씌우는 목적은 MEMS기능성 구조물(5)이 자유롭게 움직일 수 있게 하고, 외부로부터의 이물질의 유입을 막을 수 있는 밀폐공간을 확보함과 동시에 밀폐공간 내의 가능성 MEMS구조물의 전기적 특성을 외부로 이끌어 내기 위한 전기적 연결부인 패드 부분을 외부로 노출시키는 것이다.The purpose of covering the sealing lid (3) is to allow the MEMS functional structure (5) to move freely, to ensure the sealed space to prevent the inflow of foreign substances from the outside and at the same time the electrical characteristics of the potential MEMS structure in the sealed space It exposes the pad part, which is an electrical connection to draw outside, to the outside.
그런데, 상기와 같이 밀폐용 뚜껑을 제작하기 위해 뚜껑의 상·하면을 두번 가공하여야 하기 때문에 공정이 복잡하고 비용이 많이 드는 단점이 있으며, 또한 뚜껑의 상·하면의 가공위치를 맞추기 위해서는 고가의 양면 정렬기가 사용되는데, 이 장비가 없는 곳에서는 가공할수 없는 문제점이 생긴다.However, since the upper and lower surfaces of the lid must be processed twice in order to manufacture the sealing lid as described above, there is a disadvantage in that the process is complicated and expensive. The aligner is used, which creates problems that cannot be machined without it.
상기와 같은 문제점을 해결하기 위해, 밀폐용 뚜껑을 제작하는데 있어서 뚜껑의 하면만을 가공시키며, 뚜껑의 상·하면의 가공위치를 맞추기 위해 양면 정렬기를 구비할 필요가 없게 하는데 그 목적이 있다.In order to solve the above problems, it is the purpose to process only the lower surface of the lid in the manufacture of the sealing lid, it is not necessary to provide a double-sided aligner to match the processing position of the top and bottom of the lid.
도 1 은 종래의 MEMS밀폐구조 일괄제조방법 흐름도1 is a flow chart of a conventional MEMS sealed structure batch manufacturing method
도 2 는 종래의 MEMS밀폐구조 일괄제조방법에 따른 칩의 측단면도Figure 2 is a side cross-sectional view of a chip according to the conventional MEMS sealing structure batch manufacturing method
도 3 은 종래의 MEMS밀폐구조 일괄제조방법에 따른 칩의 평면도3 is a plan view of a chip according to the conventional MEMS sealing structure batch manufacturing method
도 4 는 본 발명에 따른 MEMS밀폐구조 일괄제조방법 흐름도Figure 4 is a flow chart of the MEMS sealed structure batch manufacturing method according to the present invention
도 5 는 본 발명에 따른 MEMS밀폐구조 일괄제조방법에 따른 칩의 측단면도Figure 5 is a side cross-sectional view of the chip according to the MEMS sealing structure batch manufacturing method according to the present invention
도 6 은 본 발명에 따른 MEMS밀폐구조 일괄제조방법에 따른 칩의 평면도6 is a plan view of a chip according to the MEMS sealing structure batch manufacturing method according to the present invention
※도면의 주요부분에 대한 부호의 설명※※ Explanation of symbols about main part of drawing ※
1, 2, 101, 102 : 웨이퍼 3, 103 : 밀폐용 뚜껑층1, 2, 101, 102: wafer 3, 103: sealing layer
4, 104 : 전기적 절연층 5, 105 : 기능성 구조물층4, 104: electrical insulation layer 5, 105: functional structure layer
6, 106 : 전극 연결용 금속패드막 7, 107 : 도선6, 106: metal pad film 7, 107: electrode wire for electrode connection
11, 111 : 칩완전 절단선 112 : 칩중간 절단선11, 111: chip complete cutting line 112: chip middle cutting line
본 발명은 하단만 공동제조되면서 비싼 양면 정렬기를 사용할 필요가 없도록 하기 위한 것으로 도 4 를 참조하여 설명하면, 본 발명은When the present invention is described with reference to Figure 4 to avoid the need to use an expensive double-sided aligner while only co-manufactured
반도체 공정에 의해 하나의 웨이퍼(101) 상(上)에 MEMS기능성 구조물을 형성하는 제 1 단계(100);A first step (100) of forming a MEMS functional structure on one wafer (101) by a semiconductor process;
또 다른 초기웨이퍼(102)의 하단을 공동제조하여 밀폐용 뚜껑층(103)을 형성하는 제 2 단계(200);A second step 200 of co-manufacturing the lower end of another initial wafer 102 to form a sealing cap layer 103;
상기 MEMS 기능성 구조물(105) 위에 상기 밀폐용 뚜껑층(103)을 접합하는 제 3 단계(300);A third step (300) of bonding the sealing lid layer (103) on the MEMS functional structure (105);
웨이퍼 절단기를 이용하여 칩간의 경계선인 칩완전절단선(111)을 따라 완전절단(Full cutting)시키며, 전극 연결용 금속패드막이 노출되도록 밀폐용 뚜껑의 일부인 칩중간절단선(112)을 절단하는 제 4 단계(400) 및Full cutting along the chip complete cutting line 111, which is a boundary between chips, using a wafer cutter, and cuts the middle chip cutting line 112, which is a part of the sealing lid, to expose the metal pad film for electrode connection. 4 steps 400 and
와이어 본더(Wire Bonder)를 이용하여 반도체 칩과 리드프레임의 이너리드(Inner lead)를 도선(107)으로 연결하는 제 5 단계(500)를 포함하여 이루어진다.And a fifth step 500 for connecting the inner lead of the semiconductor chip and the lead frame to the conductive wire 107 using a wire bonder.
도 5 는 본 발명에 따른 하나의 일실시예로서 그 평면도를 나타내며 도 6 는 본발명에 따른 일측단면도이다. 도시된 도 5 및 도 6 을 참조하여 보다 상세히 설명하면,Figure 5 shows a plan view as one embodiment according to the present invention and Figure 6 is a side cross-sectional view according to the present invention. Referring to Figures 5 and 6 shown in more detail,
상기 제 1 단계(100)에서는 웨이퍼상에 MEMS 구조물을 형성하는데, 제일 하단에 기판(Substrate)(101)이 있으며, 상기 기판(101) 위에 전기적 절연층(Electric isolation layer)(104)이 형성되며, 상기 전기적 절연층(104) 위에 기능성 구조물층(Functional structure layer)(105)이 형성되며, 그 위에 전극 연결용 금속패드막(Electric metal pad layer)(106)이 형성된 구조물이다.In the first step 100, a MEMS structure is formed on a wafer, and at the bottom thereof, a substrate 101 is formed, and an electrical insulation layer 104 is formed on the substrate 101. In addition, a functional structure layer 105 is formed on the electrical insulation layer 104, and an electrical metal pad layer 106 is formed thereon.
상기 기판(101)은 최하단층에 형성되며 회로나 기능성 구조물을 지지하는 초기 기판웨이퍼이다.The substrate 101 is an initial substrate wafer formed on the lowermost layer and supporting the circuit or the functional structure.
상기 전기적절연층(104)은 상기 기판이 Glass와 같은 전기적 절연체인 경우에는 필요 없으며, 실리콘 등과 같이 전기적 전도성이 있는 경우에는 상부의 회로나 기능성 구조물과의 전기적 절연을 위해 증착 등과 같은 반도체 고정을 이용해 올리는 산화막(SiO２) 또는 질화막(Si3N4) 같은 층을 말한다.The electrically insulating layer 104 is not necessary when the substrate is an electrical insulator such as glass, and when the substrate is electrically conductive such as silicon, semiconductor fixing such as evaporation is used to electrically insulate the upper circuit or the functional structure. The layer refers to a layer such as an oxide film (SiO 2 ) or a nitride film (Si 3 N 4 ).
상기 기능성 구조물층(105)은 접합이나 증착 등의 반도체 공정에 의해 올려지는 층으로, 전기적 전도성이 있고 기계적인 기능을 하는 층이다.The functional structure layer 105 is a layer which is raised by a semiconductor process such as bonding or deposition, and is a layer having electrical conductivity and mechanical function.
상기 전극 연결용 금속패드막(106)은 상기 기능성 구조물층(105)과 외부와의 전기적 연결을 위해 스퍼터(Sputter), 이배퍼레이터(Evaporator) 등과 같은 반도체 증착 장비에 의해 올려지는 전기적 연결막이다.The electrode connection metal pad layer 106 is an electrical connection layer that is mounted by semiconductor deposition equipment such as a sputter or an evaporator to electrically connect the functional structure layer 105 to the outside. .
상기 제 2 단계(200)는 또 다른 초기웨이퍼(102)의 하단만 공동제조하여 밀폐용 뚜껑층(103)을 형성하는 단계인데, 하단만 구멍을 형성함으로써 종래와 같은 값비싼 양면 정렬기가 필요치 않다. 그대신 제 3 단계에서 웨이퍼절단기를 이용하여 밀폐용 뚜껑층의 일부분을 전극 연결용 금속패드막이 노출되도록 절단시킨다.The second step 200 is a step of forming a sealing cap layer 103 by co-manufacturing only the lower end of another initial wafer 102, but by forming a hole only at the lower end, an expensive double-sided aligner as in the prior art is not required. . Instead, in the third step, a portion of the sealing cap layer is cut to expose the electrode pad metal film using a wafer cutter.
상기 밀폐용 뚜껑층(103)은 기능성 구조물층의 자유로운 운동 및 외부와의 밀폐를 위한 층으로, Glass 등과 같은 비전도성 재질로 이루어진 뚜껑형태의 층이다.The sealing cover layer 103 is a layer for free movement of the functional structure layer and sealing with the outside, a layer in the form of a lid made of a non-conductive material such as glass.
상기 하단공동제조는 초기웨이퍼의 하단 중, 전극 패드부분과 MEMS 기능성 구조물이 위치할 부분을 가공하는데 도시된 도 5 와 도 6 에서와 같이, 전극연결용 금속패드막이 형성된 부분 및 전기적 절연층에서 절연부분이 일부 끊어진 부분에 대응되게 웨이퍼의 하단에 구멍이 형성된다. 즉 도 6 의 A-A'부분을 보면, 제일 상단에 밀폐용 뚜껑층(103)이, 상기 밀폐용 뚜껑층(103) 아래에 기능성 구조물층(105)이, 그리고 상기 기능성 구조물층(105) 아래에 기판(101)이 형성되어 있어 기판(101)과 기능성 구조물(105)층 사이에는 전기적절연층(104)이 없다.The bottom co-manufacturing is insulated from the lower part of the initial wafer, the electrode pad part and the part where the MEMS functional structure is to be located, as shown in FIGS. 5 and 6, in which the electrode pad metal pad film is formed and the electrical insulating layer. Holes are formed in the lower end of the wafer so that the portions correspond to some broken portions. That is, in the portion A-A 'of FIG. 6, the sealing lid layer 103 is formed at the top, the functional structure layer 105 is disposed below the sealing lid layer 103, and the functional structure layer 105 is formed. A substrate 101 is formed below so that there is no electrically insulating layer 104 between the substrate 101 and the functional structure 105 layer.
상기 하단공동제조시 구멍가공기술에 의해 이루어지는데 구멍가공기술에는 반도체 식각기술, 샌드 블러스터, 방전 가공 등이 있으며 식각(에칭)은 KOH, TMAH 등의 식각용액이나 반응성 GaS를 사용하여 필요 없는 부분을 선택적으로 제거시키는 공정을 말하며, 샌드 블러스터(sand blast)는 주물(鑄物) 등 금속제품의 표면을 깨끗하게 마무리 손질을 하기 위해 많이 사용되고 있는 방법으로, 미세한 모래를 압축공기로 뿜어내어 패턴된 마스크를 통해 제거하고자 하는 부분을 선택적으로 제거시키는 공법이며, 방전 가공(Electric discharge machining)은 두 전극 사이에 방전을 일으킬 때 생기는 물리적 ·기계적 ·전기적 작용을 이용해서 가공하는 것을 말한다.When manufacturing the bottom joint, it is made by hole processing technology. Hole processing technology includes semiconductor etching technology, sand blasting, electric discharge processing, etc., and etching (etching) is performed by using etching solution such as KOH and TMAH or reactive GaS. Sand blast is a process that selectively removes, and sand blast is widely used to clean the surface of metal products such as castings and cleans it. It is a method of selectively removing the part to be removed through the electric discharge machining (Electric discharge machining) refers to the processing by using the physical, mechanical and electrical action that occurs when the discharge between the two electrodes.
상기 제 3 단계(300)는 상기 MEMS 기능성 구조물 위에 상기 밀폐용 뚜껑층(103)을 접합하는 단계로, 하단공동제조된 부위가 전극 연결용 금속패드막(106) 및 전기적 절연층(104)에서 절연부분이 일부 끊어진 부분의 위에 접합된다.The third step 300 is a step of bonding the sealing cap layer 103 on the MEMS functional structure, the bottom co-manufactured portion of the electrode pad metal film 106 and the electrical insulating layer 104 The insulation is joined on top of some broken parts.
상기 제 4 단계(400)에서 완전 절단 및 부분 절단이 이루어지는데 도 5 및 도 6 에 도시된 바와 같이 웨이퍼 절단기를 이용하여 칩간의 경계선을 따라 같은 크기와 형태로 완전절단이 이루어지며 전극 연결용 금속패드막이 노출되도록 밀폐용 뚜껑의 일부절단이 이루어진다. 여기서 완전절단이라 함은 그 경계선을 따라 상하로 밀폐용 뚜껑층부터 제일 하단에 있는 기판까지 자르는 것을 말한다.In the fourth step 400, complete cutting and partial cutting are performed. As shown in FIGS. 5 and 6, the cutting is performed in the same size and shape along the boundary line between the chips using the wafer cutter, and the metal for electrode connection Partial cutting of the lid is made to expose the pad membrane. Complete cutting means cutting from the top of the sealing cap layer up to the bottom of the substrate along the boundary line.
마지막으로 제 5 단계(500)에서는 와이어 본딩을 하는데 칩 내부의 외부연결단자와 리드프레임을 가는 도선(107)으로 연결하여 주는 공정을 말한다. 상기 일실시예(도 5, 도 6 )에서는 도선이 빠져 있다.Finally, in the fifth step 500, wire bonding is a process of connecting the external connection terminal inside the chip and the lead frame with a thin lead 107. In the above embodiment (FIGS. 5 and 6), the conducting wire is omitted.
상기와 같이, 밀폐용 뚜껑을 제작하는데 있어서 뚜껑의 하면만을 한번 가공시키 때문에 공정이 단순해지고, 뚜껑의 상·하면의 가공위치를 맞추기 위해 양면 정렬기를 구비할 필요가 없으므로 비용이 적게 드는 효과가 발생된다.As described above, since only the bottom surface of the lid is processed once in manufacturing the sealing lid, the process is simplified, and it is not necessary to provide a double-sided aligner to match the processing position of the top and bottom of the lid. do.
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| JP2001144117A (en) * | 1999-10-04 | 2001-05-25 | Texas Instr Inc <Ti> | Improved mems wafer-level package |
| KR20010045332A (en) * | 1999-11-04 | 2001-06-05 | 윤종용 | Fablication method of Micro Electromechanical System structure which can be packaged in the state of wafer level |
| KR20020018435A (en) * | 2000-09-01 | 2002-03-08 | 윤종용 | Semi-conductor package and producing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2001144117A (en) * | 1999-10-04 | 2001-05-25 | Texas Instr Inc <Ti> | Improved mems wafer-level package |
| KR20010045332A (en) * | 1999-11-04 | 2001-06-05 | 윤종용 | Fablication method of Micro Electromechanical System structure which can be packaged in the state of wafer level |
| KR20020018435A (en) * | 2000-09-01 | 2002-03-08 | 윤종용 | Semi-conductor package and producing method thereof |
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