KR20030083230A - Method for amplifying initial read data on bit line pair through the control of data transfer circuit - Google Patents

Abstract

PURPOSE: A method for amplifying initial read data of a phase of a bit line pair through the control of a data transmission circuit is provided to improve the sensing speed of a bit line sense amplifier by effectively reducing a charge sharing time through the control of a data control circuit. CONSTITUTION: First and second transmission control signals(PISO_RT,PISO_RC) which control data transmission circuits corresponding to a first bit line pair, transit from an active state to an inactive state. An equalization signal(PEQ_L) which controls an equalization circuit corresponding to a second bit line pair, transits from an active state to an inactive state. A third transmission control signal(PISO_LC) which controls a data transmission circuit corresponding to a second complementary bit line out of the second bit line pair, transits from an active state to an inactive state. A fourth transmission control signal(PISO_LT) transits to an active state of a boosted voltage that has a level higher than that of a voltage source. A word bit line signal(WL_LT) which selects a memory cell connected to a second bit line out of the second bit line pair, transits from an inactive state to the active state of the boosted voltage.

Description

Method for amplifying initial read data on bit line pair through the control of data transfer circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device operating at a low power supply voltage, and more particularly, prior to charge sharing between cell data and a bit line pair of a memory cell using bit line coupling. An initial read data amplification method on a bit line pair that amplifies the potential of the bit line pair.

As the power used in the system is lowered, the power supply voltage used in the semiconductor memory device included in the system is also lowered. Accordingly, there is a demand for a semiconductor memory device having the same performance as before by using a power supply voltage lower than the power supply voltage 3.3 (V) or 2.5 (V) currently used.

Meanwhile, as the power supply voltage used in the semiconductor memory device (for example, DRAM) is lowered, the voltage stored in the cell capacitor of the memory cell is also lowered. As a result, a read operation that senses, amplifies, and reads the lowered data voltage has reached a limit point.

1A and 1B are diagrams for describing an amount of potential rise (?? V) of a bit line generated when data of a cell capacitor shares charge with charge of a bit line. Referring to FIGS. 1A and 1B, the potential rise amount ?? V of a bit line is described as follows. When the word line WL is enabled, data of "1" stored in the cell capacitor CC performs charge sharing with the charge of the bit line BL. At this time, the potential rise amount ?? V of the bit line BL is given by the following equation.

In the above equation, Cc denotes the capacitance of the cell capacitor CC, Cb denotes the capacitance of the bit line BL, and Vc denotes the potential of the cell capacitor CC. And Vb = Vc / 2 and Vb is the potential of the bit line BL before charge sharing occurs. Referring to the above equation, the potential rise amount ?? V of the bit line is determined according to the potential Vc of the cell capacitor CC. That is, the smaller the power supply voltage VCC used for the memory cell of the semiconductor memory device, the smaller the potential rise amount ?? V of the bit line BL. When the potential rise amount ?? V of the bit line BL is small, the operating performance of the bit line sense amplifier, which amplifies data using the potential of the bit line BL, is degraded, thereby reducing the sensing speed. The time to reach the potential rise amount ?? V of the constant bit line BL is increased.

2 is a circuit diagram illustrating a semiconductor memory device having a bit line coupling structure according to the prior art. The bit line coupling scheme refers to a structure in which a potential of a bit line is adjusted by using a coupling capacitance of the bit line. Referring to FIG. 2, the conventional semiconductor memory device 100 includes two equalization circuits 110 and 170, two data transfer circuits 120 and 160, and two boost circuits 130. 160, the bit line sense amplifier 140, and memory cells 175, 180, 185, and 190 connected to the bit line and the complementary bit lines BL and BLB, respectively. The bit line pairs BL and BLB are connected to the input / output line pairs IO and IOB through switch transistors controlled by the column select line signal CSL.

Each of the memory cells 175, 180, 185, and 190 is selected in response to the respective word line signals WL_LC, WL_LT, WL_RT, WL_RC.

The equalization circuits 110 and 170 equalize the potentials of the bit line pairs BL and BLB to VCC / 2 in response to each of the equalization signals PEQ_L and PEQ_R.

The data transmission circuits 120 and 160 transmit data of the memory cells 175, 180, 185, and 190 to the bit line sense amplifier 140 in response to each of the transmission control signals PISO_L and PISO_R.

The first boosting circuit 130 raises the potential of the bit line BL above the potential of the previous bit line BL in response to the first boosting control signal PBLC_T. In response to the second boost control signal PBLBC_C, the second boost circuit 150 lowers the potential of the complementary bit line BLB to the potential of the conventional complementary bit line BLB. The first and second booster circuits 130 and 150 are operated to compensate for the decrease in the potential rise amount ΔV of the bit line as the power supply voltage VCC decreases.

The bit line sense amplifier 130 amplifies the voltage difference between the bit line BL and the complementary bit line BLB in response to the sensing control signals LA and LAB.

3 is a timing diagram illustrating a sensing operation of the bit line pair illustrated in FIG. 2 when the boost circuits of FIG. 2 do not operate. In addition, FIG. 3 is a timing diagram illustrating a bit line pair sensing operation when only the memory cell 175 of FIG. 2 is selected and data of “1” is stored in the memory cell 175.

When the transmission control signal PISO_R transitions from the power supply voltage VCC to the ground voltage 0 (V), the bit line pairs BL and BLB connected to the memory cells 185 and 190 become a bit line sense amplifier 140. Separated from.

Thereafter, when the equalization signal PEQ_L transitions from the power supply voltage VCC to the ground voltage 0 (V), an equalization operation of the bit line pairs BL and BLB connected to the memory cells 175 and 180. ) Is completed.

After the equalization operation is completed, the word line signal WL_LT for selecting the memory cell 175 transitions from the ground voltage 0 (V) to the boosted voltage VPP relatively higher than the power supply voltage VCC. At this time, charge sharing starts, so that the potential of the bit line BL rises by the potential rise amount ?? V of the bit line, and the potential of the complementary bit line BLB continues to maintain VCC / 2. Subsequently, the bit line sense amplifier 140 is operated so that the potential of the bit line is amplified by the power supply voltage VCC and the potential of the complementary bit line BLB is amplified by the ground voltage 0 (V).

After the sensing operation of the bit line sense amplifier 140 is performed, the transmission control signal PISO_L transitions from the power supply voltage VCC to the boosted voltage VPP for a restore operation of the memory cell 175. do.

FIG. 4 is a timing diagram illustrating a sensing operation of the bit line pair shown in FIG. 2 when the boost circuit of FIG. 2 operates. 4 is a timing diagram illustrating a bit line pair sensing operation when only the memory cell 175 of FIG. 2 is selected and data of "1" is stored in the memory cell 175.

The boost control signal PBLC_T transitions from the ground voltage 0 (V) to the power supply voltage VCC between the time point when the equalization signal PEQ_L is deactivated and the time point when the word line signal WL_LT is activated. The timing diagram of FIG. 4 differs from the timing diagram of FIG. 3 in that the potential of BL) rises by the initial amplification voltage VI.

However, the conventional semiconductor memory device 100 includes the boost circuits 130 and 150 in the bit line pairs BL and BLB, thereby increasing the size of the chip and thus increasing the production cost of the chip. .

Accordingly, an object of the present invention is to provide a method for amplifying an initial read data on a pair of bit lines through a control of a data transmission circuit that reduces the size of the chip and amplifies the initial read data of the pair of bit lines before charge sharing occurs. It is.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1A and 1B are diagrams for describing an amount of potential rise (?? V) of a bit line generated when data of a cell capacitor shares charge with charge of a bit line.

2 is a circuit diagram illustrating a semiconductor memory device having a bit line coupling structure according to the prior art.

3 is a timing diagram illustrating a sensing operation of the bit line pair illustrated in FIG. 2 when the boost circuits of FIG. 2 do not operate.

4 is a timing diagram illustrating a sensing operation of the bit line pair shown in FIG. 2 when the booster circuit of FIG. 2 operates.

FIG. 5 is a circuit diagram illustrating a semiconductor memory device having a bit line coupling structure for explaining an initial read data amplification method on a pair of bit lines according to the present invention.

FIG. 6 is a timing diagram illustrating a sensing operation of a bit line pair connected to the bit line sense amplifier of FIG. 5 for explaining a first embodiment of an initial read data amplification method on a bit line pair according to the present invention.

FIG. 7 is a timing diagram illustrating a sensing operation of a bit line pair connected to the bit line sense amplifier of FIG. 5 for explaining a second embodiment of an initial read data amplification method on a bit line pair according to the present invention.

FIG. 8 is a timing diagram illustrating a sensing operation of a bit line pair connected to the bit line sense amplifier of FIG. 5 to describe a third embodiment of an initial read data amplification method on a bit line pair according to the present invention.

FIG. 9 is a timing diagram illustrating a sensing operation of a bit line pair connected to the bit line sense amplifier of FIG. 5 for explaining a fourth embodiment of an initial read data amplification method on a bit line pair according to the present invention.

10 is a diagram comparing charge sharing time of conventional amplification methods and embodiments of the amplification method according to the present invention.

11 is a simulation diagram showing a result of simulating a first embodiment of the conventional amplification method and the third embodiment of the amplification method according to the present invention.

In order to achieve the above technical problem, an initial read data amplification method on a bit line pair according to an embodiment of the present invention includes a first bit line pair and a second bit line pair respectively connected to a bit line pair of a bit line sense amplifier. Memory cells connected to the first bit line pair and the second bit line pair through respective data transfer circuits corresponding to the first bit line pair and the second bit line pair, and the first bit line pair and the first bit line pair. A method of amplifying an initial read data on a pair of bit lines in a semiconductor memory device including equalization circuits corresponding to two bit line pairs and equalizing the potentials of the first bit line pair and the second bit line pair. According to an embodiment of the present invention, an initial read data amplification method on a pair of bit lines includes (a) a first transmission control signal and a second transmission control signal for controlling respective data transmission circuits corresponding to the first bit line pair. Transitioning from an active state to an inactive state; (b) after the step (a), an equalization signal controlling an equalization circuit corresponding to the second bit line pair transitions from an active state to an inactive state; (c) after the step (b), a third transmission control signal for controlling a data transmission circuit corresponding to a second complementary bit line of the second bit line pair transitions from an active state to an inactive state; (d) after the step (c), a word line signal for selecting a memory cell connected to a second bit line of the second bit line pair transitions from an inactive state to an active state of a boosted voltage relatively higher than a power supply voltage; And (e) after the step (d), a fourth transmission control signal for controlling the data transmission circuit corresponding to the second bit line of the second bit line pair is changed from an active state of the power supply voltage to an active state of the boosted voltage. And transitioning.

According to a preferred embodiment, the word line signal of step (d) is generated by a combination of row addresses.

According to a preferred embodiment, each of the first, second, third and fourth transmission control signals of steps (a), (c) and (e) has a respective memory corresponding to the respective data transmission circuits. Activated when cells are selected.

According to a preferred embodiment, the potential at which the first bit line pair and the second bit line pair are equalized is one half of the power supply voltage.

In order to achieve the above technical problem, an initial read data amplification method on a bit line pair according to another embodiment of the present invention includes a first bit line pair and a second bit line pair respectively connected to a bit line pair of a bit line sense amplifier. Memory cells connected to the first bit line pair and the second bit line pair through respective data transfer circuits corresponding to the first bit line pair and the second bit line pair, and the first bit line pair and the first bit line pair. A method of amplifying an initial read data on a pair of bit lines in a semiconductor memory device including equalization circuits corresponding to two bit line pairs and equalizing the potentials of the first bit line pair and the second bit line pair. According to another embodiment of the present invention, an initial read data amplification method on a bit line pair includes (a) a first transmission control signal and a second transmission control signal for controlling respective data transmission circuits corresponding to the first bit line pair. Transitioning from an active state to an inactive state; (b) after the step (a), an equalization signal controlling an equalization circuit corresponding to the second bit line pair transitions from an active state to an inactive state; (c) after the step (b), a third transmission control signal for controlling a data transmission circuit corresponding to a second complementary bit line of the second bit line pair transitions from an active state to an inactive state; (d) a step-up voltage of which a fourth transmission control signal for controlling a data transmission circuit corresponding to a second bit line of the second bit line pair after step (c) is higher than the power supply voltage from an active state of a power supply voltage; Transitioning to an active state of; And (e) after step (d), a word line signal for selecting a memory cell connected to a second bit line of the second bit line pair transitions from an inactive state to an active state of the boosted voltage. It is done.

In order to achieve the above technical problem, an initial read data amplification method on a bit line pair according to another embodiment of the present invention includes a first bit line pair and a second bit line pair respectively connected to a bit line pair of a bit line sense amplifier. Memory cells connected to the first bit line pair and the second bit line pair through respective data transfer circuits corresponding to the first bit line pair and the second bit line pair, and the first bit line pair; A method for amplifying an initial read data on a pair of bit lines in a semiconductor memory device including equalization circuits corresponding to a second pair of bit lines and equalizing potentials of the first pair of bit lines and the second pair of bit lines. According to still another embodiment of the present invention, an initial read data amplification method on a pair of bit lines includes: (a) transitioning an equalization signal from an active state to an inactive state to control an equalization circuit corresponding to the first bit line pair; (b) a first transmission control signal and a second transmission control signal for controlling respective data transmission circuits corresponding to the first bit line pair, and data transmission corresponding to a second complementary bit line of the second bit line pair; Simultaneously transitioning a third transmission control signal controlling the circuit from an active state to an inactive state; (c) after step (b), a word line signal for selecting a memory cell connected to a second bit line of the second bit line pair transitions from an inactive state to an active state of a boosted voltage relatively higher than a power supply voltage; And (d) after the step (c), a fourth transmission control signal for controlling a data transmission circuit corresponding to the second bit line of the second bit line pair is changed from an active state of the power supply voltage to an active state of the boosted voltage. And transitioning.

In order to achieve the above technical problem, an initial read data amplification method on a bit line pair according to another embodiment of the present invention includes a first bit line pair and a second bit line pair respectively connected to a bit line pair of a bit line sense amplifier. Memory cells connected to the first bit line pair and the second bit line pair through respective data transfer circuits corresponding to the first bit line pair and the second bit line pair, and the first bit line pair; A method for amplifying an initial read data on a pair of bit lines in a semiconductor memory device including equalization circuits corresponding to a second pair of bit lines and equalizing potentials of the first pair of bit lines and the second pair of bit lines. According to still another embodiment of the present invention, an initial read data amplification method on a pair of bit lines includes: (a) transitioning an equalization signal from an active state to an inactive state to control an equalization circuit corresponding to the first bit line pair; (b) a first transmission control signal and a second transmission control signal for controlling respective data transmission circuits corresponding to the first bit line pair, and data transmission corresponding to a second complementary bit line of the second bit line pair; Simultaneously transitioning a third transmission control signal controlling the circuit from an active state to an inactive state; (c) a fourth transmission control signal for controlling a data transmission circuit corresponding to a second bit line of the second bit line pair after step (b) has a boost voltage higher than the power supply voltage from an active state of a power supply voltage; Transitioning to an active state of; And (d) after said step (c), a word line signal for selecting a memory cell connected to a second bit line of said second bit line pair transitions from an inactive state to an active state of said boosted voltage. It is done.

The initial read data amplification method on the pair of bit lines according to the present invention can effectively reduce the charge sharing time through the control of the data control circuit to improve the sensing speed of the bit line sense amplifier, and can reduce the size of the chip. .

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

FIG. 5 is a circuit diagram illustrating a semiconductor memory device having a bit line coupling structure for explaining an initial read data amplification method on a pair of bit lines according to the present invention. Referring to FIG. 5, the semiconductor memory device 200 includes two equalization circuits 210 and 250, two data transfer circuits 220 and 240, a bit line sense amplifier 230, and a bit line. And memory cells 255, 260, 265, and 270 connected to the complementary bit lines BL and BLB, respectively. The bit line pairs BL and BLB are connected to the input / output line pairs IO and IOB, respectively, via switch transistors controlled by the column select line signal CSL.

Each of the memory cells 255, 260, 265, and 270 is selected in response to the respective word line signals WL_LT, WL_LC, WL_RT, and WL_RC. Each of the word line signals WL_LT, WL_LC, WL_RT, and WL_RC is generated by a combination of row addresses applied to the semiconductor memory device 200.

The equalization circuits 210 and 250 equalize the potentials of the bit line pairs BL and BLB to VCC / 2 in response to each of the equalization signals PEQ_L and PEQ_R.

The data transmission circuits 220 and 240 transmit data of the memory cells 255, 260, 265, and 270 to the bit line sense amplifier 230 in response to each of the transmission control signals PISO_LT, PISO_LC, PISO_RC, and PISO_RT. send. When the memory cells 255, 260, 265, and 270 corresponding to the respective transmission control signals PISO_LT, PISO_LC, PISO_RT, and PISO_RC are selected, the respective transmission control signals PISO_LT, PISO_LC, PISO_RC, and PISO_RT are It is optionally activated. For example, when the memory cell 255 is selected, the transfer control signal PISO_LT is activated to turn on the NMOS transistor 221 of the data transfer circuit 220.

The bit line sense amplifier 230 amplifies the voltage difference between the bit line BL and the complementary bit line BLB in response to the sensing control signals LA and LAB.

FIG. 6 is a timing diagram illustrating a sensing operation of a bit line pair connected to the bit line sense amplifier of FIG. 5 for explaining a first embodiment of an initial read data amplification method on a bit line pair according to the present invention. In addition, FIG. 6 is a timing diagram illustrating a bit line pair sensing operation when only the memory cell 255 of FIG. 5 is selected and data of “1” is stored in the selected memory cell 255.

When the first and second transmission control signals PISO_RT and PISO_RC transition from the power supply voltage VCC to the ground voltage 0 (V), the bit line pairs BL and BLB connected to the memory cells 265 and 270 are provided. This bit line sense amplifier 230 is separated.

Thereafter, when the first equalization signal PEQ_L transitions from the power supply voltage VCC to the ground voltage 0 (V), an equalization operation of the bit line pairs BL and BLB connected to the memory cells 255 and 260 is performed. equalization operation) is completed.

After the equalization operation is completed, when the third transmission control signal PISO_LC transitions from the power supply voltage VCC to the ground voltage 0 (V), the potential of the complementary bit line BLB connected to the memory cell 260 is increased. Lower the initial amplification voltage (VI) at VCC / 2. The voltage drop is caused by the coupling capacitance between the gate of the NMOS transistor 222 included in the data transfer circuit 220 of FIG. 5 and the complementary bit line BLB of the bit line sense amplifier 230.

After the third transfer control signal PISO_LC is inactivated, the word line signal WL_LT selecting the memory cell 255 has a boosted voltage relatively higher than the power supply voltage VCC at the ground voltage O (V). VPP). At this time, charge sharing starts so that the potential of the bit line BL of the bit line sense amplifier 230 rises by the amount of increase of the potential of the bit line ΔV and the complementary bit line BLB of the bit line sense amplifier 230. The potential of keeps on the previous potential. Subsequently, the bit line sense amplifier 230 operates so that the potential of the bit line BL connected to the bit line sense amplifier 230 is amplified by the power supply voltage VCC, and the complementary bit connected to the bit line sense amplifier 230. The potential of the line BLB is amplified to the ground voltage 0 (V).

Thereafter, when the fourth transfer control signal PISO_LT transitions from the power supply voltage VCC to the boosted voltage VPP, data of "1" is restored to the memory cell 255.

FIG. 7 is a timing diagram illustrating a sensing operation of a bit line pair connected to the bit line sense amplifier of FIG. 5 for explaining a second embodiment of an initial read data amplification method on a bit line pair according to the present invention.

The fourth transmission control signal PISO_LT transitions from the power supply voltage VCC to the boosted voltage VPP between the time when the equalization signal PEQ_L is inactivated and the time when the word line signal WL_LT is activated. The second embodiment of the present invention is different from the first embodiment of the present invention shown in FIG. Therefore, for a detailed description of the second embodiment of the present invention, reference is made to the description of the first embodiment of the present invention shown in FIG.

FIG. 8 is a timing diagram illustrating a sensing operation of a bit line pair connected to the bit line sense amplifier of FIG. 5 for explaining a third embodiment of an initial read data amplification method on a bit line pair according to the present invention.

According to the third embodiment of the present invention illustrated in FIG. 8, the equalization signal PEQ_L is first deactivated, and then the first, second and third transmission control signals PISO_RT, PISO_RC, and PISO_LC are deactivated. Is different from the first embodiment of the present invention. Therefore, for a detailed description of the third embodiment of the present invention, reference is made to the description of the first embodiment of the present invention shown in FIG.

FIG. 9 is a timing diagram illustrating a sensing operation of a bit line pair connected to the bit line sense amplifier of FIG. 5 for explaining a fourth embodiment of an initial read data amplification method on a bit line pair according to the present invention.

In the fourth embodiment of the present invention illustrated in FIG. 9, the fourth transmission control signal PISO_LT is inactive and the word line signal WL_LT of the first, second and third transmission control signals PISO_RT, PISO_RC, and PISO_LC. Transitions from the power supply voltage VCC to the boosted voltage VPP between the inactive points of the < RTI ID = 0.0 >), < / RTI > the potential of the bit line BL and the complementary bit line BLB of the bit line sense amplifier 230, respectively Is different from the third embodiment of the present invention shown in FIG. 8 in that it is amplified by the initial amplification voltage VI. Therefore, for a detailed description of the fourth embodiment of the present invention, reference is made to the description of the third embodiment of the present invention shown in FIG.

10 is a diagram comparing charge sharing time of conventional amplification methods and embodiments of the amplification method according to the present invention. In addition, the diagram of FIG. 10 is a chart comparing charge sharing time when the potential rise amount? V of the bit line is 100 (mV) or 120 (mV). The charge sharing time refers to the time until the data of the selected memory cell is maintained at a constant potential by sharing charge with the charge of the bit line, and the Fail shown in FIG. 10 indicates that the amplification methods are ΔV = 120 (mV). Indicates that it could not be created.

Referring to FIG. 10, the fourth amplification method of the present invention shown in FIG. 9 has a charge sharing time of about 2.0 (compared to that of the conventional first amplification method shown in FIG. 3 and the conventional second amplification method shown in FIG. ns) and about 1.3 (ns) fast. Therefore, the initial read data amplification method on the bit line pair according to the present invention can improve the sensing speed of the read data since the charge sharing time is faster than the conventional amplification methods.

11 is a simulation diagram showing a result of simulating a first embodiment of the conventional amplification method and the third embodiment of the amplification method according to the present invention.

Referring to FIG. 11, when the third embodiment BL_new3 and BLB_new3 of the initial read data amplification method on the bit line pair according to the present invention is ΔV, it is larger than the conventional first amplification methods BL_old1 and BL_old1 and is constant. It can be seen that the time to reach V is faster than the conventional first amplification methods BL_old1 and BL_old1.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The initial read data amplification method on the bit line pair according to the present invention can effectively reduce the charge sharing time through the control of the data control circuit to improve the sensing speed of the bit line sense amplifier and reduce the size of the chip.

Claims (16)

A first bit line pair and a second bit line pair respectively connected to a bit line pair of a bit line sense amplifier, and through the respective data transmission circuits corresponding to the first bit line pair and the second bit line pair; Equalization circuitry for memory cells connected to the bit line pair and the second bit line pair, and equalizing the potentials of the first bit line pair and the second bit line pair, corresponding to the first bit line pair and the second bit line pair. In the semiconductor memory device comprising an initial read data amplification method on a pair of bit lines, (a) transitioning a first transmission control signal and a second transmission control signal from the active state to the inactive state to control respective data transfer circuits corresponding to the first bit line pair; (b) after the step (a), an equalization signal controlling an equalization circuit corresponding to the second bit line pair transitions from an active state to an inactive state; (c) after the step (b), a third transmission control signal for controlling a data transmission circuit corresponding to a second complementary bit line of the second bit line pair transitions from an active state to an inactive state; (d) after the step (c), a word line signal for selecting a memory cell connected to a second bit line of the second bit line pair transitions from an inactive state to an active state of a boosted voltage relatively higher than a power supply voltage; And (e) a fourth transmission control signal for controlling a data transmission circuit corresponding to a second bit line of the second bit line pair after the step (d) transitions from an active state of the power supply voltage to an active state of the boosted voltage And an initial read data amplification method on a pair of bit lines. The method of claim 1, And the word line signal of step (d) is generated by a combination of row addresses. The method of claim 2, Each of the first, second, third and fourth transmission control signals of steps (a), (c) and (e) is activated when respective memory cells corresponding to the respective data transmission circuits are selected. And an initial read data amplification method on a pair of bit lines. The method of claim 3, And a potential at which the first bit line pair and the second bit line pair are equalized is one half of the power supply voltage. A first bit line pair and a second bit line pair respectively connected to a bit line pair of a bit line sense amplifier, and through the respective data transmission circuits corresponding to the first bit line pair and the second bit line pair; Equalization circuitry for memory cells connected to the bit line pair and the second bit line pair, and equalizing the potentials of the first bit line pair and the second bit line pair, corresponding to the first bit line pair and the second bit line pair. In the semiconductor memory device comprising an initial read data amplification method on a pair of bit lines, (a) transitioning a first transmission control signal and a second transmission control signal from the active state to the inactive state to control respective data transfer circuits corresponding to the first bit line pair; (b) after the step (a), an equalization signal controlling an equalization circuit corresponding to the second bit line pair transitions from an active state to an inactive state; (c) after the step (b), a third transmission control signal for controlling a data transmission circuit corresponding to a second complementary bit line of the second bit line pair transitions from an active state to an inactive state; (d) a step-up voltage of which a fourth transmission control signal for controlling a data transmission circuit corresponding to a second bit line of the second bit line pair after step (c) is higher than the power supply voltage from an active state of a power supply voltage; Transitioning to an active state of; And and (e) after step (d), a word line signal for selecting a memory cell connected to a second bit line of the second bit line pair transitions from an inactive state to an active state of the boosted voltage. An initial read data amplification method on a pair of bit lines. The method of claim 5, And the word line signal of step (d) is generated by a combination of row addresses. The method of claim 6, Each of the first, second, third and fourth transmission control signals of steps (a), (c) and (d) is activated when respective memory cells corresponding to the respective data transmission circuits are selected. And an initial read data amplification method on a pair of bit lines. The method of claim 7, wherein And a potential at which the first bit line pair and the second bit line pair are equalized is one half of the power supply voltage. A first bit line pair and a second bit line pair respectively connected to a bit line pair of a bit line sense amplifier, and through the respective data transmission circuits corresponding to the first bit line pair and the second bit line pair; Equalization circuitry for memory cells connected to the bit line pair and the second bit line pair, and equalizing the potentials of the first bit line pair and the second bit line pair, corresponding to the first bit line pair and the second bit line pair. In the semiconductor memory device comprising an initial read data amplification method on a pair of bit lines, (a) transitioning an equalization signal from an active state to an inactive state controlling an equalization circuit corresponding to the first bit line pair; (b) a first transmission control signal and a second transmission control signal for controlling respective data transmission circuits corresponding to the first bit line pair, and data transmission corresponding to a second complementary bit line of the second bit line pair; Simultaneously transitioning a third transmission control signal controlling the circuit from an active state to an inactive state; (c) after step (b), a word line signal for selecting a memory cell connected to a second bit line of the second bit line pair transitions from an inactive state to an active state of a boosted voltage relatively higher than a power supply voltage; And (d) a fourth transmission control signal for controlling a data transmission circuit corresponding to a second bit line of the second bit line pair after the step (c) transitions from an active state of the power supply voltage to an active state of the boosted voltage And an initial read data amplification method on a pair of bit lines. The method of claim 9, And the word line signal of step (c) is generated by a combination of row address signals. The method of claim 10, Each of the first, second, third and fourth transmission control signals of steps (b) and (d) is activated when respective memory cells corresponding to the respective transmission control signals are selected. An initial read data amplification method on a pair of bit lines. The method of claim 11, And a potential at which the first bit line pair and the second bit line pair are equalized is one half of the power supply voltage. A first bit line pair and a second bit line pair respectively connected to a bit line pair of a bit line sense amplifier, and through the respective data transmission circuits corresponding to the first bit line pair and the second bit line pair; Equalization circuitry for memory cells connected to the bit line pair and the second bit line pair, and equalizing the potentials of the first bit line pair and the second bit line pair, corresponding to the first bit line pair and the second bit line pair. In the semiconductor memory device comprising an initial read data amplification method on a pair of bit lines, (a) transitioning an equalization signal from an active state to an inactive state controlling an equalization circuit corresponding to the first bit line pair; (b) a first transmission control signal and a second transmission control signal for controlling respective data transmission circuits corresponding to the first bit line pair, and data transmission corresponding to a second complementary bit line of the second bit line pair; Simultaneously transitioning a third transmission control signal controlling the circuit from an active state to an inactive state; (c) a fourth transmission control signal for controlling a data transmission circuit corresponding to a second bit line of the second bit line pair after step (b) has a boost voltage higher than the power supply voltage from an active state of a power supply voltage; Transitioning to an active state of; And and (d) after the step (c), a word line signal for selecting a memory cell connected to a second bit line of the second bit line pair transitions from an inactive state to an active state of the boosted voltage. An initial read data amplification method on a pair of bit lines. The method of claim 13, And the word line signal of step (d) is generated by a combination of row addresses. The method of claim 14, Each of the first, second, third and fourth transmission control signals of steps (b) and (c) is activated when respective memory cells corresponding to the respective data transmission circuits are selected. An initial read data amplification method on a pair of bit lines. The method of claim 15, And a potential at which the first bit line pair and the second bit line pair are equalized is one half of the power supply voltage.