KR20030074665A - Distribution /combining packet switching apparatus using brief scheduling information - Google Patents

Abstract

The present invention relates to a distributed combining packet switching device in a next generation packet network. The distributed combining packet switching device in the next generation packet network includes distribution means for distributing a predetermined number of packets, each consisting of a second predetermined number of unit switch modules each having a first predetermined number of queues; Queue control means for controlling packet input and output with respect to the first predetermined number of queues; Distribution arbitration means for distributing the packet to an output link of the distribution means by inputting a predetermined number of packets stored in a predetermined number of queues in the queue control means; Coupling arbitration means for arbitrating and distributing contention of packets distributed in the distribution mediation means; Switching means configured to constitute the second predetermined number of unit switch modules and to classify and output packets according to the coupling arbitration information of the coupling mediation means; Combining means for constituting a predetermined number of unit switch modules, classifying packets output from the combining arbitration means according to destination information, queuing them in a corresponding buffer, and outputting the packet data to a means for outputting the packet data; And connecting means for connecting the distribution means and the switching means, the switching means and the coupling means.

Description

DISTRIBUTION / COMBINING PACKET SWITCHING APPARATUS USING BRIEF SCHEDULING INFORMATION}

Next-generation converged networks maintain the advantages of the Internet Protocol (IP), Asynchronous Transfer Mode (ATM), that is, guaranteeing the quality of service (QoS) of the ATM, while maintaining the ATM virtual path. It is widely expected that this will be an ATM + network that solves the difficulty of directly accommodating connectionless Internet services according to its characteristics, or an IP + network that solves the problems of quality of service (QoS) and network stability of an ATM network. In other words, the next generation communication network is composed of a packet switched network.

However, the delay performance of the Internet, which has recently increased explosively among existing packet networks, shows about 400 ms 90 percentile delay. However, for quality assurance similar to the voice service quality of conventional public switched telephone network (PSTN) telephones, a performance of about "90 percentile delay of less than 50 ms is required."

The low latency performance of the Internet can be attributed to the existing multi-hop switching / routing architecture. In other words, due to the difficulty in the efficient implementation of large-scale routing / switching functions, the existing Internet forms a network by connecting multiple small routers / switches.

Inevitably, packets originating from the sender are routed through a complex multi-stage path and are delivered to the receiver with a large number of switching delays.

Meanwhile, the conventional packet switch will be described in more detail as follows.

Packet switches can be classified into output buffering, shared buffering, input buffering, and input and output buffering according to packet buffer positions.

First, the output buffering method operates at a speed of N times the number of input and output terminals of the switch compared to the switching input and output link speeds, thereby transmitting up to N packets to one output terminal during a unit time. Thus, buffering of packets occurs only at the output and shows ideal performance in terms of throughput and packet latency. However, in the output buffering scheme, the individual output buffers require N + 1 double speed operation, resulting in high implementation cost and difficulty in implementing large switches.

On the other hand, the shared buffering method uses a shared buffer that has 2N times the bandwidth of the I / O link, so that N writes and N reads per unit time are possible, which shows optimal throughput and packet delay characteristics as well as output buffering. . In addition, since N inputs and N outputs share a buffer, a minimum packet loss rate can be obtained with the same amount of buffers. However, since it is difficult to implement a 2N double-speed buffer, there is a limit to applying it to a high-speed large-scale switch, and a switch having a maximum throughput of about 40 Gigabit / sec can be manufactured using the currently available 0.2 um CMOS semiconductor technology. .

In input buffering, the input buffer and the switching fabric operate at link speed. Therefore, only one packet can be transmitted to an output terminal at one input terminal, and the transport blocked packets are stored in the input buffer. In addition, the buffer memory bandwidth required for packet storage in the input buffering method is twice the packet input rate, which is the minimum of the buffering methods.

However, although the input buffering scheme has the advantages described above, if the destination output terminal of the first packet stored in a specific input buffer is preempted and blocked by the first packet of another input terminal, the destination output terminal of the packets after the first idle state. In this case, the maximum throughput is limited to 58.6% due to HOL (Head-of-Line) blocking in which these packets cannot be transmitted.

This occurs when an NxN switching fabric is used with one First In First Out (FIFO) queue at the input, so extensive research has been conducted to improve the maximum throughput of the input buffering switch by mitigating this condition. Among these, a widely used technique is to perform output-level queuing (Virtual output queueing or N FIFO queueing) on individual input buffers to make the best use of the switching fabric's capabilities. It is a method of selecting the maximum possible number of packets that can be transmitted. That is, in the NxN switch, there are N output queues for each input, and the input packets are stored in their own output queue. There are N ² queues throughout the switch, and the I / O arbitration arbiter of the switch performs a procedure for efficiently and efficiently allocating packets that may exist in these N ² input queues to N outputs.

Among the algorithms of operation of these arbitration arbitrators are well known PIM (T. Anderson, S. Owicki, J. Saxe, and C. Thacker. "High Speed Switch Scheduling for Local Area Networks," ACM Transactions on Computer Systems 11, 4 , November 1993.), RRM, iSLIP (Nick McKeown, "iSLIP: A Scheduling Algorithm for InPut-Queued Switches," IEEE Transactions on Networking, April 1999.). 2DRR (RO LaMaire et al, "Two-dimensioanl round-robin schedulers for packet switches with multiple input queues." IEEE / ACM Trans. Networking., Vol. 2., No, 5., Oct. 1994), WFA (C Partridge, et al., "A 50-Gb / s IP router," IEEE / ACM Trans. Networking, vol. 6, pp. 237-248, June 1998), MUCS (H. Duan, A High-performance OC. -12 / OC-48 Queue Design Prototype for Input-buffered ATM Switches, IEEE Infocom '97, Kobe, Japan, pp 20-28, April 7-11, 1997), RRGS (A. Smiljanic, "RRGS"-Round-Robin Greedy Scheduling for Electronic / Optical Terabit Switches, "IEEE GLOBECOM'99, pp 1244-1250,1999), and CORP (Cavendish, D.," High Performance Switching and routing, "ATM 2000, Proceedings of the IEEE Conference on High Performance Switching and routing, Page (s): 55-64, 2000).

Switches using these arbitration control algorithms achieve high throughput by eliminating HOL blocking because input packets are stored and managed by destination. Among them, Mckeown, developer of iSLIP (Nick McKeown, et-al, "Achieving 100% Throughput in an Input-Queued Switch," IEEE Transactions on Communications, Vol. 47, No. 8, August 1999, pp. 1260-1267) Can achieve 100% throughput for the Maximum Size Matching algorithm if the input traffic is uniform, and 100% throughput for the non-uniform traffic environment with the Maximum Weight Matching algorithm. Proved to be possible.

However, these input buffer type virtual output queuing (VOQ) switches require N ² queues, the switching delay characteristics increase in proportion to N at high input loads, and high contention contention control. The contention control device must operate at high speed due to the need for multiple repetitive contention control, and the practical implementation of the space switch in which the switching operation is performed when using the currently available 0.2 um class CMOS semiconductor technology is about 80 Gigabit / It is not very high compared to 40 Gigabit / sec, which is the maximum possible speed of shared buffer method, and the switching delay characteristic increases in proportion to N, the number of switch I / O terminals. One-hop switching (one h) is suitable for the structure that has a small number of I / O stages and the individual I / O link operates at high speed. As next-generation switches aiming for op switching are inadequate structures and different signal paths on high-speed spatial switches, it is difficult to synchronize packets at the output stage, which actually requires a packet buffer at the output stage of the spatial switch. Have problems.

Accordingly, new methods are being sought for next-generation switches in which the number of matching stages is N to thousands to tens of thousands, and information processing capacity is several Terabit / sec to several tens of Terabit / sec. The results of research on such a large switch generally have packet buffers at the input / output stage. In order to overcome the physical limitations, these large-capacity switch structures are composed of several unit switches having mostly small switching capabilities. Accordingly, internal blocking occurs in the switch, so that input / output is inevitably necessary to arbitrate or buffer them. Buffers are needed.

The large-capacity switches developed are first-generation structures developed by "Bell Lab" represented by "StarLite", "MoonLite", and "SunLite", which operate according to the algorithm of "Batcher-Banyan Switch" network. do. These structures have not been commercialized due to the necessity of huge interconnection networks and the difficulty of guaranteeing quality of service (QoS) as packet loss rate is linked to input traffic patterns.

As the second-generation series high capacity switch structure developed following the first generation structure, "Tandem Banyan", "ReRouting Banyan", "Knockout switch", "Growable switch", and "MSM switch" are representative. These structures feature stochastic internal blocking arbitration control. Although these switch structures are reduced compared to the first generation architecture, they still completely overcome the shortcomings of the first generation architecture such as the need for a large interconnection network and difficulty in guaranteeing quality of service (QoS) due to stochastic arbitration control. I could not.

Another second-generation scheme is a simple architecture, in which internal blocking is mediated using packet buffers in a "Banyan" network with switches in the "CLOS" or "BENES" network with "buffered Banyan" architecture. The furnace is relatively easy to implement and has been widely used as a commercial exchanger structure. The "ACE" switches and "Alcatel" ATM switches developed by "HAN-BISDN" are "buffered banyan" switches.

Recently, methods for arbitration-deterministically controlling internal blocking in a large input / output buffer structure have been developed. Of these, "Obara" time reservation technique (H. Obara, et al., "Input and output queueing ATM switch architecture with spatial and temporal slot reservation control," Electronics Letters, Vol. 28, No. 1, Jan. 1992) Is a structure in which a request is sent from the input buffer module to the arbitration arbiter and the transmission buffer time is set by the arbitration arbiter and sent to the input buffer module. Here, the number of I / O ports is grouped several times to reduce the number of queues for each input port, thereby reducing the number of transmission requests used in contention control. In addition, the statistical multiplexing gain according to the input port grouping improves the overall switch performance.

However, the paper uses time information in contention control. Therefore, in the case of a large-capacity switch, the amount of time information is increased and high speed operation is difficult. In addition, when only one crossbar is used as the switch fabric and the number of input / output ports increases, the number of crossbar input / output links increases, making it difficult to implement a large-scale switch.

Compared to the above structure, "ATLANTA (Fabio M. Chiussi, et-al." The ATLANTA Architecture and Chipset: A Low-Cost Scalable Solution for ATM Networking, "ISS'97, p43-52, 1997) (us5689500, us5689505, us5689506) "has a known" CLOS "switch fabric structure. In fact, the "CLOS" switch fabric is non-blocking under certain conditions for circuit switched traffic.

In addition, packet-blocking traffic may be non-blocking when packet path control is performed. The non-blocking properties mentioned above for "CLOS" or "BENES" switch fabrics are of interest and are well known in that they can be obtained within a minimum amount of crossbar input resources (Joseph Y. Hui, "Switching"). and traffic theory for integrated broadband networks, "Kluwer Academic Publishers, 1990). Accordingly, the "ATLANTA" switch structure is superior in scalability compared to the structure of "Obara".

The internal blocking arbitration control scheme of the " ATLANTA " switch is similar to " SLIP " in that the first failed packet in the contention for the crossbar output is re-engaged in the next contention opportunity. Each input buffer module has packet buffers for queuing by output and class of service. For the packets stored in these buffers, the second round robin arbiter in the input buffer module has an input buffer module for each packet slot. Select packets corresponding to the number of links connecting the crossbar and the crossbar. Information on the final output end of the selected packet and the class of service is transmitted to the arbiter in the crossbar through the link, and the arbiter in the crossbar selects one packet for each crossbar output and sends it to the input buffer module attached to the selected link. Send a signal At this time, the packet that is not allowed to transmit due to the crossbar output end contention by the arbiter in the crossbar rejoins the next contention arbitration. That is, a round robin pointer movement scheme similar to " SLIP " is used.

However, the internal blocking arbitration control scheme of the "ATLANTA" switch is not disclosed in more detail than mentioned above, and according to the above-mentioned reference, the non-blocking feature is extended when the internal links are extended by at least 8/6 times. It is announced that it can maintain. Accordingly, the saturation throughput of the internal blocking arbitration control method of the "ATLANTA" switch is expected to reach about 75%.

Another arbitration control algorithm for the "CLOS" type I / O buffer switch architecture is 2DRRMS (MS Han et al, "Fast scheduling algorithm for input and output buffered ATM switch with multiple switching planes," Electronics Letters, Vol. 35, No. 23 , pp. 1999-2000, Nov. 1999).

Like 2DRR, 2DRRMS uses a transmission request matrix and a search pattern matrix to search the transmission request matrix in the order defined in the search form matrix to determine a transmission request. At this time, the 2DRRMS method performs contention arbitration control only for the head of line (HOL) packet, and transmits whether to allow transmission and crossbar information to be used to the input buffer module. As such, many crossbars are used, but they are used to improve switch throughput and are not used directly for processing capacity expansion.

Therefore, a method for enabling information exchange with one hop switching in a next-generation packet network is required.

The present invention relates to a distributed combined packet switching device having concise arbitration communication information enabling one hop switching in a next generation packet network and an internal blocking arbitration device using the same.

1 is a block diagram of an embodiment of a distribution combining packet switching device according to the present invention;

2 is a block diagram of an internal blocking arbiter for the distributed combining packet switching device of FIG. 1 according to the present invention;

3 is a detailed block diagram of an embodiment of a distribution arbiter for the internal blocking arbiter of FIG. 2 according to the present invention;

4 illustrates one embodiment of the distribution arbiter component and method of operation of FIG. 3 in accordance with the present invention.

FIG. 5 is a detailed block diagram of an embodiment of a combined arbitrator for the internal blocking arbitrator of FIG. 2 according to the present invention; FIG.

FIG. 6 illustrates one embodiment of the combined arbitrator component and method of operation of FIG. 5 in accordance with the present invention. FIG.

7 is a diagram illustrating an embodiment of the switching performance of the distributed combining packet switching device according to the present invention.

Embodiment for Invention

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an embodiment of a distribution combining packet switching device according to the present invention.

As shown in FIG. 1, a distributed combining packet switching apparatus 1000 according to the present invention is as follows.

First, the internal structure has a traditional "CLOS" switch fabric structure, where i (where i is any natural number) distribution stage 1100 consisting of m _1i x n ₁ unit switch modules 1110, 1120, 1130, j (Where j is an arbitrary natural number) a switching stage 1200 composed of m ₂ xn ₂ unit switch modules 1210, 1220 and 1230, where l is an arbitrary natural number m ₃ xn _3l units Coupling end 1300 composed of switch modules 1310, 1320, and 1330, and connection links 1510 and 1610 connecting the distribution end 1100 and the switching end 1200, the switching end 1200 and the coupling end 1300. It consists of an interconnection network consisting of

Further, the distribution end (1110) i dog m _1i xn ₁ unit switch modules (1110,1120,1130) inside one m ₃ xn _3l unit switch modules (1310,1320,1330) at the coupling end 1300 of the With one queue 1111 to 1113 equal to the number, it is possible to directly accommodate subscriber stations or network matching devices of various speeds according to the space priority designated for each queue for use of the internal link, so that one switching Information exchange is possible through one hop switching.

An interconnection network connecting the distribution stage 1100 and the switching stage 1200 defines a multilink connection element k ₁ and introduces a relation of (k ₁ xj = n ₁ ) and (k ₁ xi = m ₂ ). It is coupled (n ₁ , m ₂ ) in the form of a full shuffle (Full shuffle) by the multiple connection link 1510 having a.

In addition, the same interconnection network connecting the switching stage 1200 and the coupling stage 1300 is defined by introducing a multilink connection element k ₂ (k ₂ xl = n ₂ ) and (k ₂ xj = m ₃₎ having gwangyesikreul by multiple connecting link _{(1610) (n 2, m} 3 in) is coupled to a full shuffle (full shuffle) form.

Accordingly, the network topology of the distributed combining packet switching apparatus 1000 may be described by variables consisting of (m _1i , n _3l , i, j, l, k ₁ , k ₂ ). Thus, in the case of (k ₁ = k ₂ = 1, m _1i = m ₁ , n _3l = n ₃ ), the distributed combining switching device 1000 is the same as the “CLOS” switch network in terms of network topology. In addition, when (m _1i = m ₁ , n _3l = n ₃ ), the size of the distributed packet switching device 1000 using (m ₁ , n ₃ , i, l), which is a network topology element. May be represented by (N _i = m ₁ xi), (N _o = n ₃ xl).

Hereinafter, the unit switch modules 1110, 1120, and 1130 in the distribution stage 1100 are referred to as distribution switches 1110, 1120, and 1130.

The distribution switches 1110, 1120, and 1130 are output queuing type switches. The distribution switches 1110, 1120, and 1130 are provided with one queue 1111 to 1113 equal to the number of unit switch modalities 1310, 1320, and 1330 in the defect stage 1300.

Packets that are introduced through the m _1i input links 1410 of the distribution switches 1110, 1120, and 1130 are multiplexed and classified according to the destination information of the packets, and then the unit switch module of the combined terminal 1300 to output the packets. The queues 1111 to 1113 correspond to the queues 1310, 1320, and 1330.

The n ₁ output terminals 1510 and one queue 1111 to 1113 in the distribution switches 1110, 1120, and 1130 form an n ₁ xl bipartite matching graph. Packets entering and queuing at the distribution switches 1110, 1120, and 1130 are units in the switching stage 1200 using output links 1510 determined by an internal blocking arbiter (FIG. 2 below) according to the present invention. Output to the switch module 1210, 1220, 1230.

The switching stage 1200 includes unit switch modules 1210, 1220, and 1230 configured as a general output buffer switch or a crossbar space division switch.

The individual unit switch modules 1210, 1220, and 1230 classify incoming packets through m ₂ input links according to destination information, and unit switch modules 1310, 1320, and 1330 of the coupling stage 1300 to output the packets. Outputs to n ₂ output links 1610 connected to the "

If k ₁ = k ₂ = 1, that is, when the switch fabrics are connected by single links, the unit switch modules 1210 to 1230 of the switching stage 1200 may serve as simple crossbar space partitioning switches.

However, if k ₁ = a, k ₂ = b (where a and b are constants other than 1), that is, connected by multiple links, a packet can be stored for each output, and each output buffer can contain b outputs. You must use an output buffer switch with a link.

Coupling stage 1300 is composed of a combination switch (1310, 1320, 1330) as a unit switch module.

The combination switches 1310, 1320, and 1330 are at least common output buffer switches or shared buffer switches that queue at each output stage.

Coupling switches 1310, 1320, and 1330 classify packets coming through m ₃ input links 1610 according to destination information, queue them in the corresponding buffers 1331 and 1332, and then output the packets to be output. Output to 1710.

As described above, the distributed combining packet switching apparatus 1000 has a multirate subscriber or network matching capability. That is, a relatively low speed end subscriber and a high speed network matching device through a large capacity Dense Wavelength Division Multiplexing (DWDM) transmission line can be directly connected to the same switch fabric. This feature is essential for one-hpp switching required in next-generation networks.

The distributed combining packet switching apparatus 1000 may use a link that operates at different physical speeds or a group link method that uses a plurality of links operating at a specific speed as a group to support various line rates. Can be. At this time, the group link method is excellent in terms of system modularity, but has a disadvantage of requiring a lot of input resources.

The internal connection of the distributed combining packet switching device 1000 is a relatively uniform structure. That is, by the multiple connection link (1510, 1610) (n ₁ , m ₂ ) or (n ₂ , m ₃ ) form of a full shuffle (Full shuffle) is coupled. In this case, it is assumed that any distribution switch input stage link 1410 speed is v _i , output stage link 1510 speed of the distribution stage 1100 is v _j , and output link 1610 speed of the switching stage 1200 is v _k . In this case, "m _1i xv _i ≤ n ₁ xv _j ≤ n ₂ xv _k ", the distributed combining packet switching device 1000 is non-blocking.

FIG. 2 is a diagram illustrating an embodiment of an internal blocking arbiter for the distributed combining packet switch of FIG. 1 according to the present invention.

As shown in FIG. 2, the internal blocking arbiter 2000 for the distributed combining packet switch is configured for one queue 1111 to 1113 included in the distribution switches 1110, 1120, and 1130 in the distribution stage 1100. I queue controllers 2110, 2120, and 2130 that control packet input and output, and packets stored in one queues 1111 to 1113 in the queue controllers 2110, 2120, and 2130. Distribution scheduler 2210 for distributing to the output link 1510 of the distribution switch 1110, 1120, 1130 or the unit switch module 1210, 1220, 1230 of the switching stage 1200 as the number thereof. 2220, 2230, encoders 22120, 22220, and 22320 encoding n ₂ bits distribution information (22111 to 22113) into log (1) bits queue numbers allocated to the link, and encoded log (1) bits distribution information, respectively. decoder for decoding the restored to ₂ n bits distribution information (23120,23220,23320), recovers only the switching of packets in a distributed (2210-2230) (1200) of the distribution or Hapdan 1300 comprises a combination of arbitration j groups (2310,2320,2330) that mediates the input and output link contention.

The internal blocking arbiter 2000 for the distributed combining packet switching device 1000 includes i queue controllers 2110, 2120, and 2130, i distribution schedulers 2210, 2220, and 2230. j coupling arbitrators 2310, 2320, 2330, and signal connection lines 21111 to 21131, 21211, 21311, and the like. Here, the signal connection line has a topology similar to that of the interconnection network of FIG. 1 and is composed of two networks having opposite signal directions.

The operation of the queue controllers 2110, 2120, 2130 and the distribution mediators 2210, 2220, 2230 will be described in more detail with an example where the unit switch module size is the same as 3 × 3.

When i = j = l = 3, k ₁ = k ₂ = 1, i.e., the unit switch module sizes of the distribution stage 1100, the switching stage 1200, and the coupling stage 1300 are equally 3 x 3, and these In the case of connecting the interconnection through a single link, the queue controller 2110 controls packet queues divided by three coupling switches 1310, 1320, and 1330. Here, the packet output to the queue 21110 is made through three output links 1510 in the distribution switch 1110, where these three output links are recognized as "0", "1", "2". Give a number. As shown in Fig. 2, when outputting a packet, the "21110" queue has an output link priority of "0->2->1", the "21120" queue has a priority of "1->0->2", and The "21130" queue may be used with priority of "2->1->0". When a plurality of queues "21110" to "21130" compete to use a particular output link, the queue having the highest use priority for that output link wins the contention. For example, if there are packets queued in all the queues "21110" to "21130", the link "0" is a "21110"queue; Link "1" is queue "21120"; Link "2" is assigned to serve the "21130" queue.

That is, the distribution mediator 22110 cyclically allocates the output links that can be used when there is an output request in the individual queues in order of priority. At this time, the number of output links that can be allocated per individual queue is maximum in unit packet time, as much as the packets that can be drawn in and stored in the distribution switch 1110 at the output link "unit packet output time". Or the total link number. Here, "unit packet output time" means the time taken for the distribution switch to output one packet using the output link.

In addition, when distributing an output link to queues cyclically as mentioned above, the same output link should not be assigned to different queues at the same priority at the same packet output time.

That is, when the output link is allocated to one queue as "0-> 2-> 1" and the other queue as "1-> 2-> 0", link 2 is overlapped at the second priority. Likewise, it violates the link allocation method for queues.

In general, if there are fewer output links than the number of queues of the distribution switch 1110, that is, if there are four queues but two links, two queues may be set to "0" and "1". Q1 "," Q2 "," Q3 ", and" Q4 "," Q1: 0-> 1 "," Q2: 1-> 0 "," Q3: 0-> 1 "," Q4: 1- Priority> 0 "and links must be assigned to each queue. Accordingly, the above allocation requires two packet fetch cycles ("unit packet output time"). That is, in the first cycle, links are allocated with the temporal and spatial priority of (Q1: 0-> 1, Q2: 1-> 0), (Q3: 0-> 1, Q4: 1-> 0). In the first cycle, links are allocated with the temporal and spatial priority of (Q3: 0-> 1, Q4: 1-> 0) and (Q1: 0-> 1, Q2: 1-> 0). Here, parenthesis means that the same space priority.

For queues belonging to different queue controllers 2110, 2120, and 2130, the queues 21110, 21210, and 21310 corresponding to the same combined switch 1310 are not allocated the same output link with the same priority at the same packet output time. Assign cyclically. That is, the queues 21110, 21210, and 21310 which store packets destined for the first combining end are “0-> 2-> 1”, “2-> 1-> 0”, and “1” as shown in FIG. 2. Output link allocation priority of-> 0-> 2 ".

This queue-specific output link allocation is performed by a distribution scheduler 2210, 2220, and 2230. That is, when the queue controller 2110 sends the packet number information stored in the corresponding queue through the signal lines 21111, 21121, and 21131 to the distribution arbiter 2210, the distribution arbiter 2210 has the same output link. It is assigned to only one queue during the fetch cycle and controls the output links to be assigned to the above-mentioned space priority for each queue. As shown in FIG. 2, the distribution arbiter 2210 displays matrices 22110, 22210, and 2210 that are divided into three sections so that the cues correspond to the vertical axis and the output links correspond to the horizontal axis. Each element of the matrix is divided into black, checkered, and diagonal lines, which represent spatial priorities in the order described.

The distribution arbiters 2210, 2220, and 2230 perform contention control on the distribution end output links for the individual queues, and then output the contention control results to the encoder 22120 using the signal lines 22111 to 22113. These distribution information (22111 to 22113, 22211, 22311) are n ₁ bits, respectively, and indicate that a specific queue is assigned per specific distribution switch output link. Using these characteristics, the encoders 22120, 22220, and 22320 encode these distribution information 22111 to 22113, which are a total of lxn ₁ bits per individual distribution arbiters 2210, 2220, and 2230, to a queue number allocated per output link. Distribution information (22114 to 22116), abbreviated as n ₁ x log (1) bits, is output to the combined arbitrators 2310, 2320, and 2330. Accordingly, the distribution contention control result output from the distribution arbiters 2210 to 2230 is log (1) bits corresponding to the queue number allocated to each of the n ₁ distribution end output links, and is fetched to indicate priority information. Cycle identification information may be added.

The contention-controlled distribution information 22111 ˜ 22113, 22211, and 22311 may be fetched by the respective distribution arbiters 2210, 2220, and 2230 so that packets queued through the output terminal of the distribution switch may be fetched. Classified by the unit switch module (1210, 1220, 1230) and the contention control again for the switching stage 1200 output links by the coupling arbitrator (2310 ~ 2330). That is, in FIG. 2, the signals 22111, 22211, and 22311, which are the distribution control results for the queues 21110, 21210, and 21310, correspond to packets destined for the same switching stage 1200 as the switch module 1210, 1220, 1230. As it is the distribution contention / control result signals, the contention control is input to the coupling arbiter 2310 to perform contention control on the output stage 1610 of the switching stage 1200.

Coupling arbiters 2310, 2320, and 2330 control packet contention occurring at the coupling stage 1300, the input link 1610, or the switching stage 1200, the output link 1610. The information 23111 decoded the arbitration information 22114 ˜ 22116, 22214, and 22314, which are abbreviated to log (1) bits, indicates that a bit corresponding to a specific queue number indicates a logical value true. This means that the packet can be drawn out to the coupling end 1300 through the output link. A maximum of ixk ₁ packets can be introduced from different distribution switches to the same switching stage unit switch module, and the incoming packets in this particular packet entry cycle are specified via k ₂ output links 1610 in subsequent packet output cycles. It may be input to the coupling switch 1310.

Coupling the arbiter (2310,2320,2330) is finally allowed output from the ixk _one distributing arbitration information generated for the one coupling end, a single switching stage 1200, a unit switch modules (1210,1220,1230) per The function of selecting k ₂ which may be performed is performed for all the unit switch modules 1210, 1220, 1230 of the switching stage 1200.

Accordingly, the combined arbiters 2310, 2320, 2330 are matrixes whose logical values are true in the (ixk ₁ ) xl distributed mediation signal matrix 23110, 2210, 2233 composed of the output signals of the distributed arbiters 2210, 2220, 2230. Select k ₂ elements per each time. This selection process is performed according to the spatial priority according to the output link selection priority procedure in which the destination-specific queue can be used as described above, and simple round-robin with a fixed priority when k ₁ = k ₂ = 1. Same as the matching operation,

As shown in Fig. 2, the coupling arbiter matrices 23110,23210,23310 are cases where k ₁ = k ₂ = 1, and three cues correspond to the vertical axis, and three links correspond to the three axes on the horizontal axis. Each matrix in the matrix is divided into black, checkered, and diagonal lines, each of which has a spatial priority in the order mentioned. Here, the coupling arbiter 2310 performs contention control for the coupling end input links by a known round-robin matching operation starting from a black pattern row for each column and proceeding in a checkered row direction.

An internal blocking contention control is performed on the distribution end and the switching end output links by the joint arbitrators 2310, 2320, and 2330 so that a destination-specific queue distributed through the corresponding link can transmit a packet. The arbitration results in 23110,23210,23310 are encoded by the encoders 23120,23220,23320 and converted into 1 bit result information 23112, which then enters the decoder 22120 in the distribution arbiter 2210. ) Is compared with the combined arbitration request signals 22111 ˜ 22113 inputted at the beginning of the arbitration cycle, decoded (21112, 21122, 21132), and distributed to the queue controllers 2110, 2120, 2130 by destination and queue. At this time, the queue controllers 2110, 2120, and 2130 control to fetch packets sequentially in the order of packets stored in the HOL to output links allocated to their own queues as described in the arbitration result information, and transmit them to the distribution terminal.

As described above, the internal blocking arbiter 2000 for the distributed combining packet switch has a feature of assigning a fixed spatial priority to every arbitration cycle for the links to be used by the unit switching modules. Here, the reason for limiting the fixed link space priority allocation to each outgoing arbitration cycle is that the space priority allocation for each arbitration cycle can be reset for the fair performance of the switch per link circuit. Arbitration cycle information must be available in synchronization. Due to this feature, we can simulate that only one withdrawal arbitration cycle, that is, distribution arbiter and combined arbiter, can achieve more than 90% of processing efficiency under all switch input load conditions even with one arbitration.

If all destination queues in all distribution switches 1110 to 1130 have queued packets, then all destination queues have k ₁ dedicated packet outgoing links that are definitely allocated according to link allocation space priority. Have. Thus, under random and fair packet input conditions, they operate as M / D / 1 queues. Therefore, in this case, the processing delay time of the distributed combining packet switch 1000 has a value of (k ₁ +1) Do / k ₁ when Do is the processing delay time of the ideal output buffer switch, and k ₁ is sufficiently larger than 1. It is close to the ideal output buffer characteristics, and has an excellent performance of only twice the output buffer switch performance even in an economical structure with k ₁ . Of course, the switch saturation throughput is 100%. That is, strictly non-blocking.

3 and 4, the configuration and operation of the distribution arbiters 2210, 2220, and 2230 for the internal blocking arbiter will be described in more detail.

4 shows the components of the distribution arbiter and its operation algorithm,

FIG. 3 shows a distribution arbiter for a distribution stage switch with five cues and five output links, constructed using 25 components of FIG.

As shown in FIG. 4, the component 4000 of the distribution arbiter may include an operation initialization signal rst, an operation synchronization signal tck, remaining number of queue input information rqn_i, and remaining number of queue output information rqn_o. Link reservation input information (grh_i), link reservation output information (grh_o) indicating whether the corresponding link has been selected by another component having a high spatial priority, and outputting packets to queues and links corresponding to the component. It has an input / output signal containing information (odisel) indicating whether this reservation is made.

The component 4000 of the distribution arbiter performs the following operations using "rqn_i", which is information about the remaining number of queues, and "grh_i", which is information indicating whether a packet has been allocated by a previous component in a corresponding output link. do.

If the remaining number information "rqn_i" of the queue is not "0" (that is, if there are remaining packets that can be allocated) and "grh_i" is "0" (that is, the previous component with a higher space priority) If the corresponding output link is not preempted), the value "-1" in "rqn_i" is assigned to "rqn_o", and the logical value "1" is assigned to "grh_o" and output. At this time, "odisel" has a logical value "1" which means that the packet is allocated to the corresponding queue and the corresponding output link.

However, the remaining component information "rqn_i" of the queue is not "0" (that is, if there are remaining packets that can be allocated) and "grh_i" is not "0" (ie, the previous component with higher space priority). In the case where the corresponding output link is preempted, " rqn_o " is inputted with the " rqn_i " input value and " grh_o " In the same case, "odisel" has a logical value of "0" which means that no packet is allocated to the corresponding queue and the corresponding output link.

Further, even when the remaining number information "rqn_i" of the queue is "0" (that is, no remaining packets that can be allocated), the "rqn_o" input value "rqn_i", "grh_o" input value "grh_i" It is assigned as is and output. In addition, "odisel" has a logical value "0" which means that no packet is allocated to the corresponding queue and the corresponding output link.

The operation as described above is the same as the component operation algorithm indicated by "4100" in FIG. The " rst " and " tck " signals shown in Fig. 4 are synchronization clock and component operation initialization signals that control every arbitration cycle.

3 shows an example of a configuration of a distribution arbiter 3000 consisting of components 4000.

The distribution arbiter 3000 includes a space switch 3200, components of FIG. 4 (3800, 3900, etc.), connection signal lines 3600 and 3700 connecting them, and distribution arbitrator input and output signal terminals 3100 and 3500. do.

The spatial switch 3200 variably assigns the output link spatial priority for the queues 1111 to 1113 according to the packet fetch cycle ("unit packet output time") and the position in the switch of the distribution arbiter. .

The input of the spatial switch 3200 modulates the distribution switch position information to the queued packet number information signal 21111 ˜ 21131 (3100) and the number of elapsed packet fetch cycles emitted by the queue controllers 2110, 2120, and 2130 by modulo operation. The sum signal is 3400, and the input signal 3100 is cyclically rotated and output to the output terminal 3300 according to the signal of "3400". Here, the position information of the distribution switch 1110 to 1130 means that the position order in the switch of the distribution switch module is assigned to the 1110 position and the 1120 position. That is, the space switch 3200 performs a barrel shifter operation of rotating and outputting the input signals 3100 according to the "3400" signal.

The core part of the distribution arbiter, which forms a rectangular matrix with the components of Fig. 4, the queues correspond to the column axis, and the output link of the distribution switch corresponds to the row axis. Remaining number input information " rqn_i " of the queue for the component on the diagonal axis receives the remaining packet information of the queue controller input according to the spatial priority determined by the spatial switch 3200. In addition, since the link reservation information "grh_i" for the components on the diagonal axis is fixedly drawn into logical value "0" 3810, these positions are the starting point of the distribution arbitration and have the highest priority. In addition, the components located on the diagonal also block the asynchronous feedback loop in the hardware implementation.

In the matrix of the components of FIG. 4, the row axis signals grh_i and grh_o are connected by signal lines 3600 to form loops, and these row loop signal lines are broken through the diagonal components. In addition, the column axes signals rqn_i and rqn_o are connected by signal lines 3700 to form loops, and the column loop signal lines pass through diagonal components and the loops are broken.

Meanwhile, for convenience, a signal "rst" and "tck" commonly introduced into the component is not shown in FIG. 3.

When queue residual packet information is input to the distribution arbiter of FIG. 3, the distribution arbiter performs a function of equally distributing packets to be output to the output link according to the above-described queue-level link space priority. The distributed result is a signal of n ₂ bits per cue and is led to the coupling arbitrator through the output terminal 3500.

The implementation of the distribution arbiter using 0.2 um CMOS semiconductor technology required a logic element of about 250 kgates in a 64 x 64 matrix and a maximum operating speed of about 37 ns. Assuming that the packet slot time is four times the maximum operating speed, a distribution controller for about 15 Terabit / sec distribution-coupled packet switches can be implemented using conventional semiconductor technology.

Now, the configuration and operation of the combined arbiter 2310 for the internal blocking arbiter will be described in more detail with reference to FIGS. 5 and 6.

FIG. 6 shows the components of the combined arbitrator and its operation algorithm. FIG. 5 shows a distribution switch with five cues and a combined switch with five input links, constructed using 25 components of FIG. Shows a combined mediator.

The combined arbiter component 6000 shown in FIG. 6 is an operation initialization signal rst, information (init_d) for indicating whether it is located at the diagonal axis 5300 of the component matrix, indicating the starting point of the arbitration operation upon initialization, Arbiter operation synchronization signal (tck), remaining number of unallocated combined end input links (rqn_i), remaining number of unallocated combined end input links (rqn_o), other components with high spatial priority Link reservation information (grh_i), link reservation output information (grh_o), indicating whether the corresponding link is selected by means of a pointer input for specifying the starting point of the arbitration operation, that is, the component having the highest priority, every arbitration cycle. signal (po_i), the pointer output signal (po_o), 1 bit arbitration type information (disel) corresponding to the component of n ₂ bits input signal to be output in a distributed arbiter, and And has the input and output signals of the configuration queue and the packet output is coupled arbitration information groups (ocsel) indicating that the reservation by the link corresponding to the element. The component 6000 of the coupling arbiter performs the following operations using the input signals.

In FIG. 6, reference numeral 6100 denotes an operation initialization operation of the component 6000. That is, if "rst" is true and located on the diagonal axis of the component matrix, it means that the component has the highest priority, and in hardware, the asynchronous loop signal in the arbiter 5000 Initializing "po_o", which serves as a feedback cutoff point, to a logical value of "1", declares that the corresponding element is located on the diagonal axis of the matrix (5300). In addition, if "rst" is true, since the operation is initiating, it declares that the arbitration result signal "ocsel" is not arbitrated by setting "ocsel" as "0".

In FIG. 6, reference numeral 6200 describes the present operating state of the component 6000. That is, if the pointer output signal "po_o" is true, the component is located diagonally in the matrix, and thus has the highest spatial priority. Accordingly, if k ₂ coupling end input links that can be allocated to the corresponding queue are unassigned, if the 1-bit arbitration input information "disel" is true, "rqn_o" is assigned "k ₂ -1". "Grh_o" and "ocsel", which mean that the element is reserved for arbitration, are assigned a logical value of true. However, if the 1-bit arbitration input information "disel" is false, the component has the highest priority, but since there is no distribution arbitration result, "rqn_o" is assigned k ₂ , meaning that the element is reserved for arbitration. grh_o "and" ocsel "are assigned logical false.

On the other hand, if "po_o" is false, i.e., the component is located outside of the matrix diagonal, "disel" is true and "grh_i" is false, and "rqn_i" is not "0", i.e. If a packet can be forwarded to queues and links, and that link is not preempted by a higher priority component and there is a joint input link that can be allocated, then "rqn_o" is equal to the value of "rqn_i" entered. Is assigned a value of -1 ", and" grh_o "and" ocsel ", which mean that the element is reserved for arbitration, are assigned a logical value of true. However, if "disel" is false, "grh_i" is true, or "rqn_i" is "0", there will be no distribution mediation result, so "rqn_o" is assigned the value of "rqn_i" entered, "Grh_o" and "ocsel", which mean that an arbitration is reserved, are assigned logical false.

In Fig. 6, the pointer signal po_o, which means to be positioned on the matrix diagonal axis after the initialization operation at "6000", is shifted to a component located on the right side (or left side) every arbitration cycle.

In FIG. 5, reference numeral 5000 denotes a combined arbiter, receives an input signal 5100 that is a distribution mediation result of 1 x n ₂ bits, and distributes the same to each of the corresponding components 5300. By selecting _two components k of the distribution mediation result (disel) is true among the components located by each row axis, the corresponding packet can be reached to the final coupling switch without internal blocking. 5200 is used to notify the queue controller. Here, the row loop signal line 5600 represents passages connecting the signals "po_i", "po_o", "rqn_i", and "rsn_o", and the column loop signal line 5700 has "grh_o" and The paths connecting the "grh_i" signals are shown.

Now, with reference to FIG. 7, the performance of the distributed combining packet switching device according to the present invention will be described.

The distribution switch, the switching stage unit switch, and the combined switches are equally 64x64, and the distributed switch is applied evenly and randomly to the 4096x4096 split-packet packet switch configured in the form of a "CLOS" switch network with a single link connection. The switching delay characteristics of the computer simulation test results are shown in FIG.

As shown in Fig. 7, the delay value is about twice that of the ideal output buffer switch characteristic as a whole.

As described above, the present invention has an effect of enabling large-scale multirate packet switching for next-generation packet networks by using an arbitration technique having a high throughput by using a spatial priority designated for each queue to use an inner link.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

Disclosure of Invention The present invention has been proposed to solve the above-mentioned problems and meet the demands. The present invention proposes a distributed combining packet having concise arbitration communication information for enabling information exchange with one hop switching in a next-generation packet network. It is an object of the present invention to provide a switching device and an internal blocking arbitration device using the same.

The apparatus of the present invention for achieving the above object is a distributed combining packet switching device in a next-generation packet network, comprising a second predetermined number of unit switch modules each having a first predetermined number of queues, the predetermined number Distribution means for distributing packets of; Queue control means for controlling packet input and output with respect to the first predetermined number of queues; Distribution arbitration means for distributing the packet to an output link of the distribution means by inputting a predetermined number of packets stored in a predetermined number of queues in the queue control means; Combined arbitration means for mediating and distributing contention of packets distributed by the distribution mediation means; Switching means configured to constitute the second predetermined number of unit switch modules to classify and output packets according to the combined arbitration information of the combined arbitration means; Combining means for constituting a predetermined number of unit switch modules, classifying packets output from the combining arbitration means according to destination information, queuing them in a corresponding buffer, and outputting the packet data to a means for outputting the packet data; And connecting means for connecting the distribution means and the switching means, the switching means and the coupling means.

Another apparatus of the present invention provides an internal blocking arbitration apparatus, comprising: queue control means for controlling packet input / output with respect to a predetermined number of queues of distribution switches of a distributed combining packet switching apparatus; Distribution arbitration means for distributing the number of packets stored in a predetermined number of queues in the queue control means to be distributed to switches in the output link / switching device of the distribution switch; An encoder for encoding predetermined bit distribution information into a log (1) bit queue number assigned to the link; A decoder for decoding the encoded log (1) bit distribution information and restoring the predetermined bit distribution information; And combining arbitration means for arbitrating the switching means / combining means input / output link contention of the packets distributed by the distribution arbiter.

The present invention relates to a large packet switch having a system information processing capacity of several Terabit / sec to several tens of Terabit / sec, and proposes a switching algorithm and structure suitable for a large packet switch capable of accommodating end subscribers in thousands to hundreds of thousands. .

In addition, in the present invention, it is possible to simultaneously accommodate end subscriber matching devices ranging from tens of thousands to hundreds of thousands of lines and network matching devices ranging from several Gigabit / sec to several tens of Gigabit / sec, thereby enabling one-hop switching for next-generation packet communication networks. We present a switching algorithm and structure for a large packet switch that can exchange information.

In addition, the present invention proposes a switching algorithm and structure for a large packet switch having 100% throughput without internal link expansion or speedup.

In addition, the present invention proposes a switching algorithm and a structure for a large packet switch that can easily cope with the increase in the switch capacity according to the increase of subscribers because of the scalability and modularity of the switching modules.

The present invention provides a large-scale switching device (distributed combined packet switching device) that enables one-hop switching in a next-generation packet network. The large-capacity packet switching device includes a current telephone subscriber or an Internet xDSL subscriber or an IMT-2000. Given the reality of network evolution as a wireless subscriber, it must be physically acceptable within an existing public switched telephone network (PSTN) telephone company. In addition, for one hop switching, a terminal subscriber matching device (UNI) and a network access matching device (NNI) must be directly connected to one switch. Typically, subscribers accepted by PSTN telephone companies range from about 50,000 to 200,000 revolutions, and service information rates from xDSL and IMT-2000 range from 2 Mbps to 20 Mbps. In view of the above, a large packet switching apparatus that can be implemented by the present invention has a switching capacity of several Terabit (10 ¹² bit / sec) to several tens of Terabit, terminal subscriber matching capability of several tens of thousands of lines, and several tens of Gigabit (10 ⁹ bit / sec). It must be capable of accommodating hundreds of lines of capacity for network access.

To solve this, the internal structure of the present invention has a traditional "CLOS" switch fabric structure, consisting of a distribution stage, switching stage, coupling stage, distribution mediator, coupling mediator, and connecting links connecting them.

In particular, the present invention efficiently communicates the internal link resources because only the log (1) bit corresponding to the queue number in the per-link distribution switch, the 1 bit indicating whether arbitration is allowed, and the identification signal for arbitration cycle synchronization are communicated. Because it can be used, it is very suitable to implement a large capacity switch.

The processing delay time of the distributed combining packet switching device according to the present invention has a value of (k ₁ +1) Do / k ₁ when the processing delay time of an ideal output buffer switch is Do and the number of internal multilink connections is k ₁ . _{When 1} is greater than _{1, it} is close to the ideal output buffer characteristics, and the economic structure of k ₁ is 1, which is only twice the performance of the output buffer switch. The switch saturation throughput is 100%. In other words, it is strictly non-blocking. In addition, it is possible to implement a distributed-combined packet switch with 15 Terabit / sec throughput using the existing 0.2um CMOS semiconductor technology.

In conclusion, the present invention can satisfy the requirements for the next-generation switch, thereby enabling information exchange with one hop switching in the next-generation packet network.

Claims (18)

A distributed combining packet switching device in a next generation packet network, Distribution means for distributing a predetermined number of packets each configured by a second predetermined number of unit switch modules each having a first predetermined number of queues; Queue control means for controlling packet input and output with respect to the first predetermined number of queues; Distribution arbitration means for distributing the packet to an output link of the distribution means by inputting a predetermined number of packets stored in a predetermined number of queues in the queue control means; Combined arbitration means for mediating and distributing contention of packets distributed by the distribution mediation means; Switching means configured to constitute the second predetermined number of unit switch modules to classify and output packets according to the combined arbitration information of the combined arbitration means; Combining means for constituting a predetermined number of unit switch modules, classifying packets output from the combining arbitration means according to destination information, queuing them in a corresponding buffer, and outputting the packet data to a means for outputting the packet data; And Connecting means for connecting said distribution means and said switching means, said switching means and said coupling means; Distributed packet switching device comprising a. The method of claim 1, The distribution means, The predetermined number of unit switch modules are provided with a predetermined number of queues equal to the number of predetermined number of unit switch modules in the coupling means, and can directly accommodate subscriber terminal / network matching devices of various speeds. Distributed packet switching device, characterized in that to enable one hop switching in one switching. The method of claim 1, The queue control means, Distributed packet packet switching device characterized in that for controlling the packet queue divided by the predetermined number of coupling means. The method of claim 1, The distribution arbitration means, The distributed output packet switching device of claim 1, wherein the same output link is allocated to only one queue in the same fetch cycle, and the output links are assigned to space priority by individual queues. The method of claim 1, The combined arbitration means, Distributed packet packet switching device characterized in that for controlling the contention of packets occurring in the input link of the coupling means, the output link of the switching means. The method of claim 1, The distribution arbitration means, As an element, it corresponds to the operation initialization signal rst, the operation synchronization signal tck, the remaining number of queue input information rqn_i, the remaining number of queue output information rqn_o, and other components having a high spatial priority. A queue including input / output signals of information (grh_i) indicating whether a link is to be committed, link reservation output information (grh_o), and information (odisel) indicating whether packet output is reserved for a link corresponding to a corresponding component, and a queue; A rectangular matrix is formed of the above components by using the remaining number information rqn_i and information (grh_i) indicating whether a packet has been allocated to a corresponding output link by a previous component, and the column axis is a distribution switch queue. The row axis corresponds to the output link of the distribution switch, and the rqn_i of the component on the diagonal axis is input with the spatial priority determined by the spatial switch. Receive the remaining packet information of the queue controller, the "grh_i" of the component on the diagonal axis is fixed fixed to the logical value '0', so that these positions are the starting point of the distribution arbitration and have the highest priority, and these diagonal The components located on the axis block the asynchronous feedback loop in hardware implementation, receive the queue remaining packet information, and distribute the packets to be distributed evenly to the output link according to the link space priority of each queue. Combined packet switching device. The method of claim 6, The component is, When the "rqn_i" is not 0 and the "grh_i" is '0', the value "-1" in the "rqn_i" is assigned to the "rqn_o". A logical value "1" is assigned to the "grh_o" and outputted, wherein the "odisel" has a logical value "1" indicating that a packet has been allocated to the corresponding queue and the corresponding output link, and otherwise, the "rqn_o". The "rqn_i" input value, and the "grh_i" input value is assigned to the "grh_o" is output as it is, and if the same, the "odisel" is a logical value that means that no packet is allocated to the queue and the corresponding output link. A distributed combining packet switching device, characterized in that it has "0". The method of claim 6, The combined arbitration means, As an element, an operation initialization signal (rst), information (init_d) for indicating whether the mediation operation is initiated at initialization and located on a diagonal axis of the component matrix, an arbitrator operation synchronization signal (tck), an unassigned combination The remaining number of input links (rqn_i), the remaining number of unallocated combined end input links (rqn_o), the information indicating whether the corresponding link is selected by other components having a high spatial priority (grh_i) ), Link reservation output information (grh_o), a pointer input signal (po_i) for specifying the start point of the arbitration operation, i.e., the component having the highest priority, in every arbitration cycle, the pointer output signal (po_o), and the Arbitration input information (disel) corresponding to the corresponding component among the bit input signals outputted from the distribution arbiter, and to the queue and link corresponding to the corresponding component It contains input and output signals of information (ocsel) indicating whether the packet output is reserved by the coordinator, and forms a rectangular matrix of the components, and receives the input signals resulting from the distribution mediation and distributes them to the respective components. After that, the components of the distribution mediation result (disel) among the components located in each row axis are selected and the packets corresponding to them can be reached to the final combining switch without internal blocking. Distribution-combined packet switching device for notifying queue control means. The method of claim 8, The component is, In the initializing operation of the combined arbitration means, if the synchronous clock rst controlling every arbitration cycle is true, the corresponding component has the highest priority, and in hardware, it is asynchronous in the arbitrator. Initialize "po_o", which serves as a feedback cutoff point of the loop signal, to logical value "1" to declare that the corresponding component is located on the diagonal axis of the matrix, and operate if "rst" is true. In the initializing step, the mediation result signal "ocsel" is set to "0" to declare that the mediation is not mediated. When "po_o" is true when the combined mediation means is performed, the component is placed on the diagonal of the matrix. Since the location has the highest spatial priority, if the distribution arbitration result (disel) is true because the predetermined number of coupling means input links that can be assigned to the corresponding queue is "rqn_o" "-1" is assigned a predetermined number, and "grh_o" and "ocsel" are assigned to TRUE, meaning that the element is reserved for arbitration. If "disel" is false, the corresponding element is assigned. Since "rqn_o" is allocated the predetermined number, and "grh_o" and "ocsel", which means that the element is reserved for arbitration, are assigned the logical value false because they have the highest priority but no distribution mediation result. If "po_o" is false, "disel" is true and "grh_i" is false, and if "rqn_i" is not "0", the "rqn_o" is entered in the value of "rqn_i". -1 "," grh_o "and" ocsel "are assigned logically true, meaning that the element is reserved for arbitration, and" disel "is false or" grh_i "is true If "rqn_i" is "0", there is no distribution arbitration result. The "rqn_o" input is assigned the value of the "rqn_i", distributed distribution packet switching device, characterized in that the "grh_o" and "ocsel" that means that the element is reserved arbitration is assigned logically false . An internal blocking arbitration apparatus, Queue control means for controlling packet input / output with respect to a predetermined number of queues of distribution switches of the distributed combining packet switching device; Distribution arbitration means for distributing the number of packets stored in a predetermined number of queues in the queue control means to be distributed to switches in the output link / switching device of the distribution switch; An encoder for encoding predetermined bit distribution information into a log (1) bit queue number assigned to the link; A decoder for decoding the encoded log (1) bit distribution information and restoring the predetermined bit distribution information; And Combined arbitration means for arbitrating the switching means / combining means input / output link contention of packets distributed in the distribution arbiter Internal blocking arbitration device comprising a. The method of claim 10, The queue control means, Internal blocking arbitration apparatus, characterized in that for controlling the packet queue divided by the predetermined number of coupling means. The method of claim 10, The distribution arbitration means, An internal blocking arbitration apparatus, wherein the same output link is allocated to only one queue in the same withdrawal cycle and controls the output links to be assigned in space priority for each queue. The method of claim 10, The combined arbitration means, And an internal blocking arbitration apparatus for controlling packet contention occurring at an input link of the coupling means and an output link of the switching means. The method according to any one of claims 10 to 13, The distribution arbitration means, As an element, it corresponds to the operation initialization signal rst, the operation synchronization signal tck, the remaining number of queue input information rqn_i, the remaining number of queue output information rqn_o, and other components having a high spatial priority. A queue including input / output signals of information (grh_i) indicating whether a link is to be committed, link reservation output information (grh_o), and information (odisel) indicating whether packet output is reserved for a link corresponding to a corresponding component, and a queue; A rectangular matrix is formed of the above components by using the remaining number information rqn_i and information (grh_i) indicating whether a packet has been allocated to a corresponding output link by a previous component, and the column axis is a distribution switch queue. The row axis corresponds to the output link of the distribution switch, and the rqn_i of the component on the diagonal axis is input with the spatial priority determined by the spatial switch. Receive the remaining packet information of the queue controller, the "grh_i" of the component on the diagonal axis is fixed fixed to the logical value '0', so that these positions are the starting point of the distribution arbitration and have the highest priority, and these diagonal The components located on the axis block the asynchronous feedback loop in hardware implementation, and receive queue residual packet information, and distribute the packets to be distributed evenly to the output link according to link space priority of each queue. Blocking Arbitration Device. The method of claim 14, The component is, When the "rqn_i" is not 0 and the "grh_i" is "0", the value "-1" in the "rqn_i" is assigned to the "rqn_o". A logical value "1" is assigned to the "grh_o" and outputted, wherein the "odisel" has a logical value "1" indicating that a packet has been allocated to the corresponding queue and the corresponding output link, and otherwise, the "rqn_o". The "rqn_i" input value, and the "grh_i" input value is assigned to the "grh_o" is output as it is, and if the same, the "odisel" is a logical value that means that no packet is allocated to the queue and the corresponding output link. Internal blocking arbitration device, characterized in that it has a "0". The method of claim 14, The combined arbitration means, As an element, an operation initialization signal (rst), information (init_d) for indicating whether the mediation operation is initiated at initialization and located on a diagonal axis of the component matrix, an arbitrator operation synchronization signal (tck), an unassigned combination The remaining number of input links (rqn_i), the remaining number of unallocated combined end input links (rqn_o), the information indicating whether the corresponding link is selected by other components having a high spatial priority (grh_i) ), Link reservation output information (grh_o), a pointer input signal (po_i) for specifying the start point of the arbitration operation, i.e., the component having the highest priority, in every arbitration cycle, the pointer output signal (po_o), and the Arbitration input information (disel) corresponding to the corresponding component among the bit input signals outputted from the distribution arbiter, and to the queue and link corresponding to the corresponding component It contains input and output signals of information (ocsel) indicating whether the packet output is reserved by the coordinator, and forms a rectangular matrix of the components, and receives the input signals resulting from the distribution mediation and distributes them to the respective components. After that, the components of the distribution mediation result (disel) among the components located in each row axis are selected and the packets corresponding to them can be reached to the final combining switch without internal blocking. And an internal blocking arbitration device, which notifies the queue control means. The method of claim 16, The component is, In the initializing operation of the combined arbitration means, if the synchronous clock rst controlling every arbitration cycle is true, the corresponding component has the highest priority, and in hardware, it is asynchronous in the arbitrator. Initialize "po_o", which serves as a feedback cutoff point of the loop signal, to logical value "1" to declare that the corresponding component is located on the diagonal axis of the matrix, and operate if "rst" is true. In the initializing step, the mediation result signal "ocsel" is set to "0" to declare that the mediation is not mediated. When "po_o" is true when the combined mediation means is performed, the component is placed on the diagonal of the matrix. Since the location has the highest spatial priority, if the distribution arbitration result (disel) is true because the predetermined number of coupling means input links that can be assigned to the corresponding queue is "rqn_o" "-1" is assigned a predetermined number, and "grh_o" and "ocsel" are assigned to TRUE, meaning that the element is reserved for arbitration. If "disel" is false, the corresponding element is assigned. Since "rqn_o" is allocated the predetermined number, and "grh_o" and "ocsel", which means that the element is reserved for arbitration, are assigned the logical value false because they have the highest priority but no distribution mediation result. If "po_o" is false, "disel" is true and "grh_i" is false, and if "rqn_i" is not "0", the "rqn_o" is entered in the value of "rqn_i". -1 "," grh_o "and" ocsel "are assigned logically true, meaning that the element is reserved for arbitration, and" disel "is false or" grh_i "is true If "rqn_i" is "0", there is no distribution arbitration result. And an input of the value of "rqn_i" to which "rqn_o" is input, and the "grh_o" and the "ocsel", which mean that the corresponding element is reserved for arbitration, are allocated as logical false. The method of claim 14, The internal blocking arbitration device, In internal blocking arbitration operation, it is recommended to efficiently use internal link resources by communicating only log (1) bits corresponding to queue numbers in the distributed switch per link, 1 bit indicating whether arbitration is allowed, and identification signals for arbitration cycle synchronization. An internal blocking arbitration device.