KR20020053664A - Terabit Packet Switching Apparatus with Brief Communicating Information for intermediation - Google Patents

Abstract

PURPOSE: A distribution-combination packet switching system having simple correspondence information for arbitration is provided to achieve information exchange at one hop switching in an advanced packet network. CONSTITUTION: An internal blocking arbitrator(2000) in a distribution-combination packet switching system consists of queue controllers(2110-2130), distribution schedulers(2210-2230), encoders(22120-22113), decoders(23120-23320), and combination schedulers(2310-2330). The queue controllers(2110-2130) control packet input and output for l numbers of queues that the distribution switches of a distribution unit have. The distribution schedulers(2210-2230) take the packets stored in the queues of each individual queue controller(2110-2130) as input and distribute them to the output links of the distribution switches or the switches of a switching unit. The encoders(22120-22113) encode n2-bit distribution data(22111-22113) with log(l)-bit queue numbers respectively. The decoders(23120-23320) decode the encoded log(l)-bit distribution data into n2-bit distribution data. The combination schedulers(2310-2330) arbitrate the input-output link contention of the packets distributed from the distribution scheduler(2230).

Description

Distributed Packet Switching Apparatus with Brief Communicating Information for intermediation

The present invention relates to a distributed combined packet switching device having concise arbitration communication information that enables one hop switching in a next-generation packet network.

Next-generation converged networks maintain ATMs' virtual paths while maintaining advantages such as Internet Protocol (IP) Asynchronous Transfer Mode (ATM), that is, guaranteeing ATM's Quality of Service (QoS). It is widely expected to be an ATM + network that solves the problem of not directly accepting a connectionless Internet service according to its characteristics, or an IP + network that solves the problems of QoS and network stability of an ATM network. In other words, the next generation communication network is composed of a packet switched network.

However, the delay performance of the Internet, which has recently increased explosively among existing packet networks, shows about 400 ms 90 percentile delay. However, for quality assurance similar to the voice service quality of conventional public switched telephone network (PSTN) telephones, a performance of about "90 percentile delay of less than 50 ms is required."

The low latency performance of the Internet can be attributed to the existing multi-hop switching / routing architecture. In other words, due to the difficulty in the efficient implementation of large-scale routing / switching functions, the existing Internet forms a network by connecting multiple small switches / routers. Inevitably, packets originating from the sender are routed through a complex multi-stage path and are delivered to the receiver with a large number of switching delays.

Now, the conventional packet switch will be described in more detail.

Packet switches can be classified into output buffering, shared buffering, input buffering, and input and output buffering according to packet buffer positions.

The output buffering method operates at a speed that is N times the number of the input and output terminals of the switch compared to the switching input and output link speeds, so that up to N packets can be transmitted to one output terminal during a unit time. Thus, buffering of packets occurs only at the output and shows ideal performance in terms of throughput and packet latency. However, in the output buffering scheme, the individual output buffers require N + 1 double speed operation, resulting in high implementation cost and difficulty in implementing large switches.

On the other hand, the shared buffering method uses a shared buffer that has 2N times the bandwidth of the I / O link, so that N writes and N reads per unit time are possible, which shows optimal throughput and packet delay characteristics as well as output buffering. . In addition, since N inputs and N outputs share a buffer, a minimum packet loss rate can be obtained with the same amount of buffers. However, since it is difficult to implement a 2N double-speed buffer, there is a limit to applying it to a high-speed large-scale switch, and a switch having a maximum throughput of about 40 Gigabit / sec can be manufactured using the currently available 0.2 um CMOS semiconductor technology. .

In input buffering, the input buffer and the switching fabric operate at link speed. Therefore, only one packet can be transmitted to the output at one input, and the transport blocked packets are stored in the input buffer. In addition, input buffering is the least of the buffering schemes where the buffer memory bandwidth required for packet storage is twice the packet input rate.

However, although the input buffering method has the advantages as described above, if the destination output terminal of the first packet stored in a specific input buffer is preempted by the first packet of another input terminal, the destination output terminal of the first and subsequent packets is idle. Even in the state, the maximum throughput is limited to 58.6% due to HOL (Head-of-Line) blocking, which prevents transmission of these packets.

This occurs when an NxN switching fabric is used with a single first in first out (FIFO) queue at the input, so extensive research has been conducted to improve the maximum throughput of the input buffering switch by mitigating this condition. Among these, a widely used technique is to perform virtual output queueing or N FIFO queuing on individual input buffers to make the best use of the switching fabric's capabilities, and then to avoid output collisions when selecting packets to be sent to the output. It is a method of selecting the maximum possible number of packets that can be transmitted. That is, in the NxN switch, there are N output queues for each input, and the input packets are stored in their own output queue. There are N ² queues throughout the switch, and the I / O arbitration arbiter of the switch performs a procedure for efficiently and efficiently allocating packets that may exist in these N ² input queues to N outputs.

Among the algorithms of operation of these arbitration arbitrators are well known PIM (T. Anderson, S. Owicki, J. Saxe, and C. Thacker. "High Speed Switch Scheduling for Local Area Networks," ACM Transactions on Computer Systems 11, 4 , November 1993.), RRM, iSLIP (Nick McKeown, "iSLIP: A Scheduling Algorithm for Input-Queued Switches," IEEE Transactions on Networking, April 1999.), 2DRR (RO LaMaire et al, "Two-dimensioanl round-robin schedulers for packet switches with multiple input queues. "IEEE / ACM Trans. Networking., Vol. 2., No. 5., Oct. 1994), WFA (C. Partridge, et al.," A 50-Gb / s IP router, "IEEE / ACM Trans. Networking, vol. 6, pp. 237-248, June 1998), MUCS (H. Duan, A High-performance OC-12 / OC-48 Queue Design Prototype for Input-buffered ATM Switches, IEEE Infocom '97, Kobe, Japan, pp 20-28, April 7-11, 1997), RRGS (A. Smiljanic, "RRGS-Round-Robin Greedy Scheduling for Electronic / Optical Terabit Switches," IEEE GLOBECOM'99 , pp 1244-1250,1999), and CORP (Cavendish, D., "High Performan ce Switching and routing, "ATM 2000, Proceedings of the IEEE Conference on High Performance Switching and routing, Page (s): 55-64, 2000).

In the switch using these arbitration control algorithms, since the input packet is stored and managed for each destination, HOL blocking is eliminated and high throughput can be obtained. Among them, Mckeown, developer of iSLIP (Nick McKeown, et-al, "Achieving 100% Throughput in an Input-Queued Switch," IEEE Transactions on Communications, Vol. 47, No. 8, August 1999, pp. 1260-1267) We proved that the maximum size matching algorithm can achieve 100% throughput when the input traffic is uniform and the maximum weight matching algorithm can achieve 100% throughput even in non-uniform traffic environment.

However, these input buffer type VOQ switches require N ² cues, the switching delay characteristic increases with N in proportion to N at high input loads, and a large number of repetitive contention controls are required for high throughput contention control. Control device needs to operate at high speed, and it is possible to realistically implement the space switch in which switching operation is performed when using the currently available 0.2um CMOS semiconductor technology.The maximum speed is only about 80 Gigabit / sec. Compared to 40 Gigabit / sec, which is the maximum possible speed, the switching delay characteristic is increased in proportion to the number of switch input / output terminals, N, so the number of input / output terminals cannot be increased. It is not suitable for the next-generation switch that is aimed at one hop switching because it is suitable for the structure that high speed link operates. The structure of that, and the signal path in space switches that operate at a high speed with each other at the output terminal of the packet synchronization is difficult in relation to the other in practice, it has the problems that require the packet buffer to the output of the space switch.

Accordingly, new methods are being sought for next-generation switches in which the number of matching stages is N to thousands to tens of thousands, and information processing capacity is several Terabit / sec to several tens of Terabit / sec. The results of research on such a large switch generally have packet buffers at the input / output stage. In order to overcome the physical limitations, these large-capacity switch structures are composed of several unit switches, most of which have a small switching capability, and thus internal blocking occurs in the switch, thus inevitably requiring arbitration or buffering. I / O buffers are needed.

The developed large-capacity switches are first-generation structures developed by Bell Labs, which are represented by StarLite, MoonLite, and SunLite. They operate according to the algorithm of the Batcher-Banyan switch network. These structures were not commercialized due to the necessity of huge interconnection networks and the difficulty of guaranteeing QoS due to the packet loss rate being linked to the input traffic patterns.

As the second generation series large capacity switch structure developed following the first generation structure, Tandem Banyan, ReRouting Banyan, Knockout switch, Growable switch, and MSM switches are representative. These structures feature stochastic internal blocking arbitration control. Although these switch structures are reduced compared to the first generation structures, they still do not completely overcome the disadvantages of the first generation structures such as the need for a large interconnection network and difficulty in guaranteeing QoS due to stochastic arbitration control.

Another second generation method is to switch the buffered Banyan structure of CLOS or BENES network to mediate the internal blocking using the packet buffer in the Banyan network. Widely used as a structure for exchangers. Alcatel's ATM switches, developed by HAN-BISDN, are buffered banyan switches.

Recently, methods for arbitration-deterministically controlling internal blocking in a large input / output buffer structure have been developed. Of these, Obara's time scheduling technique (H. Obara, et al., "Input and output queueing ATM switch architecture with spatial and temporal slot reservation control," Electronics Letters, Vol. 28, No. 1, Jan. 1992) When a request is sent from the input buffer module to the arbitration arbiter, the arbitration arbiter sets a transmission permission time for each request and sends it to the input buffer module. Here, the number of I / O ports is grouped several times to reduce the number of queues for each input port, thereby reducing the number of transmission requests used in contention control. In addition, the statistical multiplexing gain according to the input port grouping improves the overall switch performance.

However, the paper uses time information in contention control. Therefore, in the case of a large-capacity switch, the amount of time information is increased and high speed operation is difficult. In addition, when only one crossbar is used as the switch fabric and the number of input / output ports increases, the number of crossbar input / output links increases, making it difficult to implement a large-scale switch.

FALAN M. Chiussi, et-al. "The ATLANTA Architecture and Chipset: A Low-Cost Scalable Solution for ATM Networking," ISS'97, p43-52, 1997) (us5689500, us5689505, us5689506). The switch has a known CLOS switch fabric structure. In fact, the CLOS switch fabric is non-blocking under certain conditions for circuit switched traffic. In addition, packet-blocking traffic may be non-blocking when packet path control is performed. The non-blocking properties mentioned above for CLOS or BENES switch fabrics are of interest and are well known in that they can be obtained within minimal crossbar input resources (Joseph Y. Hui, "Switching and traffic theory for integrated broadband networks, "Kluwer Academic Publishers, 1990). Accordingly, the ATLANTA switch structure is superior in scalability compared to the Obara structure.

The internal blocking arbitration control scheme of the ATLANTA switch is similar to SLIP in that the first failed packet in the contention for the crossbar output is re-engaged in the next contention opportunity. Each input buffer module has packet buffers for queuing by output and class of service. For the packets stored in these buffers, the second round robin arbiter in the input buffer module has an input buffer module for each packet slot. Packets corresponding to the number of links connecting the crossbar and the crossbar are selected. Information on the final output end of the selected packet and the class of service is transmitted to the arbiter in the crossbar through the link, and the arbiter in the crossbar selects one packet for each crossbar output and sends it to the input buffer module attached to the selected link. Send a signal At this time, the packet that is not allowed to transmit due to the crossbar output end contention by the arbiter in the crossbar will rejoin the next contention arbitration. That is, a round robin pointer movement method similar to SLIP is used.

However, the internal blocking arbitration control scheme of the ATLANTA switch is not disclosed in more detail than mentioned above, and according to the above-mentioned reference, the non-blocking feature is maintained when the internal links are extended by at least 8/6 times. It is announced. Accordingly, the saturation throughput of the internal blocking arbitration control scheme of the ATLANTA switch is expected to reach about 75%.

As another arbitration control algorithm for CLOS type I / O buffer switch architecture, MS Han et al, "Fast scheduling algorithm for input and output buffered ATM switch with multiple switching planes," Electronics Letters, Vol. 35, No. 23, pp 1999-2000, Nov. 1999).

Like 2DRR, 2DRRMS uses a transmission request matrix and a search pattern matrix to search the transmission request matrix in the order defined in the search form matrix to determine a transmission request. At this time, the 2DRRMS method performs contention arbitration control only for the HOL packet, and transmits the transmission permission and the crossbar information to be used to the input buffer module. As such, many crossbars are used, but they are used to improve switch throughput and are not used directly for processing capacity expansion.

Therefore, there is a need for a method capable of enabling one hop switching in a single switching in a next generation packet network.

The present invention has been proposed to solve the above problems, and provides a distributed combined packet switching apparatus having concise arbitration communication information for enabling one hop switching in a next-generation packet network. Its purpose is to.

1 is a block diagram of an embodiment of a distributed combining packet switching device (distributed combined packet switch) according to the present invention.

2 is a block diagram of an embodiment of an internal blocking arbiter for the distributed combining packet switch of FIG. 1 according to the present invention;

3 is a detailed block diagram of an embodiment of a distribution arbiter for the internal blocking arbiter of FIG. 2 according to the present invention;

4 illustrates one embodiment of the distribution arbiter component and method of operation of FIG. 3 in accordance with the present invention.

FIG. 5 is a detailed block diagram of an embodiment of a combined arbitrator for the internal blocking arbitrator of FIG. 2 according to the present invention; FIG.

FIG. 6 illustrates one embodiment of the combined arbitrator component and method of operation of FIG. 5 in accordance with the present invention. FIG.

7 is a diagram illustrating an exemplary embodiment of switching performance of a distributed combining packet switch according to the present invention.

* Explanation of symbols for the main parts of the drawings

1100: distribution stage 1200: switching stage

1300: coupling end 1510,1610: connection link

According to an aspect of the present invention, there is provided a distributed combining packet switching device in a next generation packet network, comprising: distribution means including i (where i is any natural number) m _1i xn ₁ unit switch modules; Switching means consisting of j (where j is any natural number) m ₂ x n ₂ unit switch modules; coupling means consisting of l ₃ x n _3l unit switch modules (where l is any natural number); And l of m ₃ xn _3l unit switches on the distribution means and the switching means, comprising: a connection means for connecting said engagement means and said switching means, the i of m _1i xn ₁ unit switch module inside the coupling means With the same number of queues as the number of modules, distribution-coupling-mediated switching is performed according to the cyclical space and time priority assigned to each queue for use of the inner link, and the subscriber station or network matching devices of various speeds are switched. It can be accommodated directly, so that one hop switching is possible with one switching.

The present invention relates to a large packet switch having a system information processing capacity of several Terabit / sec to several tens of Terabit / sec, and proposes a switching algorithm and structure suitable for a large packet switch capable of accommodating end subscribers in thousands to hundreds of thousands. .

In addition, in the present invention, it is possible to simultaneously accommodate end subscriber matching devices ranging from tens of thousands to hundreds of thousands of lines and network matching devices ranging from several Gigabit / sec to several tens of Gigabit / sec, thereby enabling one hop switching for next-generation packet communication networks. We present a switching algorithm and architecture for a large packet switch.

In addition, the present invention proposes a switching algorithm and structure for a large packet switch having 100% throughput without internal link expansion or speedup.

In addition, the present invention proposes a switching algorithm and a structure for a large packet switch that can easily cope with the increase in the switch capacity according to the increase of subscribers because of the scalability and modularity of the switching module.

The present invention provides a large-scale switching device (distributed combined packet switching device) that enables one hopswitching in a next-generation packet network. The large-capacity packet switching device includes a current telephone subscriber or an Internet xDSL subscriber or an IMT-2000 radio. Given the reality of network evolution as a subscriber, it must be physically acceptable within the existing PSTN telephone company. In addition, for one hop switching, a terminal subscriber matching device (UNI) and a network access matching device (NNI) must be directly connected to one switch. In general, considering that the number of subscribers accommodated by PSTN telephone companies ranges from about 50,000 to 200,000 lines, and that the service information rates provided by xDSL and IMT-2000 range from 2 Mbps to 20 Mbps, A large packet switching apparatus that can be implemented by the present invention includes a switching capacity of several Terabits (10 ¹² bit / sec) to several tens of Terabits, terminal subscriber matching capability of several tens of thousands of lines, and a network of tens of Gigabits (10 ⁹ bit / sec) capacity. It must have the capacity to accommodate hundreds of connections.

To solve this problem, the internal structure of the present invention has a traditional CLOS switch fabric structure, and is composed of distribution stages, switching stages, coupling stages, distribution mediators, coupling mediators, and connection links connecting them.

In particular, the present invention efficiently communicates the internal link resources because only the log (l) bit corresponding to the queue number in the per-link distribution switch, the 1 bit indicating whether arbitration is allowed, and the identification signal for arbitration cycle synchronization are communicated during the internal blocking arbitration operation. Because it can be used, it is very suitable to implement a large capacity switch.

The processing delay time of the distributed combining packet switching apparatus of the present invention has a value of (k ₁ +1) Do / k _{1 when} Do is an ideal output buffer switch processing delay time and the number of internal multilink connections is k ₁ , and k ₁ If is greater than 1, it is close to the ideal output buffer characteristics, and the economic structure of k ₁ is 1, which is only twice the performance of the output buffer switch. The switch saturation throughput is 100%. In other words, it is strictly non-blocking. In addition, it is possible to implement a distributed-combined packet switch with 15 Terabit / sec throughput using the existing 0.2um CMOS semiconductor technology.

In conclusion, the present invention can satisfy the requirements for the next-generation switch, thereby enabling one-hop switching in a next-switch packet network.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an embodiment of a distributed combining packet switching device (distributed combined packet switch) according to the present invention.

Referring to FIG. 1, the distributed combination packet switching device 1000 according to the present invention has an internal structure of a conventional CLOS switch fabric structure, i (where i is an arbitrary natural number) m _1i xn ₁ unit switch modules ( Distribution stage 1100 consisting of 1110 ~ 1130, j (where j is any natural number) switching stage 1200 consisting of m ₂ x n ₂ unit switch module 1210 ~ 1230, and l ( l is an arbitrary natural number) coupling stage 1300 composed of m ₃ x n _3l unit switch modules 1310 to 1330, distribution stage 1100, switching stage 1200, switching stage 1200 and coupling stage ( doedoe configured as an internal network consisting of a connecting link (1510,1610) for connecting 1300), i of m _1i xn ₁ unit switch modules (1110-1130) inside the l of ₃ m xn _3l unit in the mounting platform 1300 There are l queues equal to the number of switch modules 1310 to 1330, and vary in speed depending on the space priority assigned to each queue for use of the internal link. It is possible to directly accommodate the subscriber terminal or the network matching device, which it is possible to exchange information (one hop switching) with one switch.

An internal connection network connecting the distribution stage 1100 and the switching stage 1200 is defined by introducing a multi-link connection element k _1, and thus (k ₁ xj = n ₁ ) and (k ₁ xi = m ₂ ). It is coupled in the form of (n ₁ , m ₂ ) full shuffle by the multiple connection link 1510 having a relationship.

Equally, when the interconnection network connecting the switching stage 1200 and the coupling stage 1300 is introduced by defining a multilink connection element k ₂ (k ₂ xl = n ₂ ) and (k ₂ xj = m ₃₎ having gwangyesikreul by multiple connecting link (1610) (n _2, of m ₃₎ is coupled to a full shuffle (full shuffle) form.

Accordingly, the network topology of the distributed combining packet switching apparatus 1000 may be described by variables consisting of (m _1i , n _3l , i, j, l, k ₁ , k ₂ ). Therefore, in the case of (k ₁ = k ₂ = 1, m _1i = m ₁ , n _3l = n ₃ ), the distributed coupling switching device 1000 is the same as the CLOS switch network in terms of network topology. In addition, when (m _1i = m ₁ , n _3l = n ₃ ), the size of the distributed packet switching device 1000 using (m ₁ , n ₃ , i, l), which is a network topology element. May be represented by (N _i = m ₁ xi), (N _o = n ₃ xl).

Hereinafter, the unit switch modules 1110 to 1130 in the distribution stage 1100 are referred to as distribution switches 1110 to 1130.

The distribution switches 1110 to 1130 are output queuing switches.

In the distribution switches 1110 to 1130, there are l queues 1111 to 1113 equal to the number of unit switch modules 1310 to 1130 in the coupling end 1300.

Packets introduced through the m _1i input links 1410 of the distribution switches 1110 to 1130 are multiplexed and then classified according to the destination information of the packets, and the switch modules 1310 to the combined terminals 1300 to output the packets. It enters the queues 1111 to 1113 corresponding to 1130.

The n ₁ output terminals 1510 and the l queues 1111 to 1113 in the distribution switches 1110 to 1130 form an n ₁ xl bipartite matching graph. Packets entering and queuing into the distribution switches 1110-1130 are unit switch modules 1210 in the switching stage 1200 using an output link 1510 determined by the switching arbiter (FIG. 2 below) of the present invention. ~ 1230).

The switching stage 1200 includes switch modules 1210 to 1230 constituted by a general output buffer switch or a crossbar space division switch.

The individual switch modules 1210 to 1230 classify packets introduced through m ₂ input links according to destination information and n ₂ connected to the switch modules 1310 to 1330 of the coupling terminal 1300 to which the packets are to be output. Output to output link 1610.

If k ₁ = k ₂ = 1, that is, when the switch fabric is connected with single links, the switch modules 1210 to 1230 may serve as simple crossbar space partitioning switches.

On the other hand, when k ₁ = a, k ₂ = b, where a and b are constants other than 1, that is, when connected in multiple links, a packet may be stored for each output stage, and each output buffer may have b output links. The output buffer switch must be used.

Coupling stage 1300 is composed of a combination switch (1310 ~ 1330).

Coupling switches 1310-1330 are common output buffer switches or shared buffer switches that perform at least output-level queuing.

Coupling switches 1310 to 1330 classify incoming packets through m ₃ input links according to destination information, queue them in corresponding buffers 1331 to 1332, and output the packets to an output terminal 1710 to which the packets are to be output. .

As described above, the distributed combined packet switching device 1000 has a multirate subscriber or network matching capability. That is, a relatively low speed end subscriber and a high speed network matching device through a large capacity DWDM transmission line can be directly connected to the same switch fabric. This feature is essential for one hop switching required in next generation networks.

The distributed combining packet switching apparatus 1000 may use a link that operates at different physical speeds or a group link method that uses a plurality of links operating at a specific speed as a group to support various line rates. Can be. In this case, the latter method is excellent in terms of system modularity, but has a disadvantage of requiring a lot of input resources.

The internal connection of the distributed combining packet switching device 1000 is a relatively uniform structure. That is, by the multiple connection link (1510, 1610) (n ₁ , m ₂ ) or (n ₂ , m ₃ ) form of a full shuffle (Full shuffle) is coupled. In this case, it is assumed that any distribution switch input stage link 1410 speed is v _i , the output stage link 1510 speed of the distribution stage 1100 is v _j , and the output link 1610 speed of the switching stage 1200 is v _k . For example, when m _1i xv _i ≤ n ₁ xv _j ≤ n ₂ xv _k , the distributed packet switching device 1000 is non-blocking.

FIG. 2 is a diagram illustrating an embodiment of an internal blocking arbiter for the distributed combining packet switch of FIG. 1 according to the present invention.

As shown in FIG. 2, the internal blocking arbiter 2000 for the distributed combining packet switch is configured to input / output packets to the l queues 1111 to 1113 included in the distribution switches 1110 to 1130 in the distribution stage 1100. The number of packets stored in the queues 1111 to 1113 in the i queue controllers 2110 to 2130 and the individual queue controllers 2110 to 2130 are distributed as inputs. Distribution schedulers 2210 to 2230 allocated to the output links 1510 of the switches 1110 to 1130 or the switches 1210 to 1230 of the switching stage 1200, respectively, n ₂ bits distribution information 22111 to Encoders 22120 to 22113 for encoding the log (l) bits queue number allocated to the link, and decoders 23120 to 23320 for decoding the encoded log (l) bits distribution information and restoring them to n ₂ bits distribution information. J, which arbitrates the switching stage 1200 or combining stage 1300 input / output link contention of the packets distributed by the distribution arbiter 2230. Combination arbitrators 2310-2330.

The internal blocking arbiter 2000 for the distributed combining packet switch includes i queue controllers 2110 to 2130, i distribution schedulers 2210 to 2230, and l combined arbiters 2310 to. 2330 and signal lines 21111 to 21131, 21211, and 21311 connecting them. Here, the signal connection line has a topology similar to that of the interconnection network of FIG. 1, and is composed of two networks having opposite signal directions.

The operation of the queue controllers 2110 to 2130 will be described in more detail with reference to the queue controller 2110 as an example.

Queue controller when i = j = l = 3, k ₁ = k ₂ = 1, i.e., the unit switches of the distribution, switching and coupling stages have the same size of 3 x 3 and connect them together in a single link 2110 must control the packet queue divided by three coupling switches 1310 to 1330. Here, the packet output to the queue 21110 can be made through three output links 1510 in the distribution switch 1110, where these three output links are assigned identification numbers of 0, 1 and 2. When the packet is output, the queue 21110 has an output link of 0->2-> 1 priority, the queue 21120 has a priority of 1->0-> 2, and the queue 21130 has a priority. Can be used with priority of 2->1-> 0.

That is, cyclically allocates output links that can be used by individual queues. At this time, the number of output links that can be allocated per individual queue is maximum as long as it can pull out all packets that can be input and stored in the distribution switch 1110 at the unit packet time at the output time of the output link unit packet or the entire link. It becomes a number. In addition, when distributing output links to queues cyclically, the same output link should not be allocated to different queues at the same priority at the same packet output time.

In other words, when assigning an output link as 0-> 2-1 to one queue and 1-> 2-> 0 to another queue, link 2 is duplicated at the second priority, so as to the link to the queue as described above. The allocation violates the allocation method. In general, if the number of output link is small compared to the number of queues of the distribution switch 1110, that is, if there are four queues but two links, four queues with two links 0 and 1 are Q1, Q2, and Q3. , Q4, Q1: 0-> 1, Q2: 1-> 0, Q3: 0-> 1, Q4: 1-> 0. Links must be assigned to each queue. Accordingly, two packet fetch cycles are required for the above allocation. That is, in the first cycle, links are allocated with the temporal and spatial priority of (Q1: 0-> 1, Q2: 1-> 0), (Q3: 0-> 1, Q4: 1-> 0). In the first cycle, links are allocated with the temporal and spatial priority of (Q3: 0-> 1, Q4: 1-> 0) and (Q1: 0-> 1, Q2: 1-> 0). Here, parenthesis means that the same space priority.

The queues belonging to different queue controllers 2110 to 2230 are cyclically so that the queues 21110, 21210, and 21310 corresponding to the same combined switch 1310 are not allocated the same output link with the same priority at the same packet output time. Assign. That is, the queues 21110, 21210, and 21310 storing packets destined for the first combining end are 0-> 2-> 1, 2-> 1-> 0, 1-> 0-> as shown in FIG. It may have an output link allocation priority of two.

This queue-specific output link allocation is performed by a distribution scheduler 2210-2230. That is, when the queue controller 2110 sends the packet number information stored in the queue to the distribution arbiter 2210 through the signal lines 21111 to 21131, the distribution arbiter 2210 causes the same output link to have the same withdraw cycle. In this case, the output links are allocated to the above-mentioned space priority for each queue. As shown in FIG. 2, the distribution arbiter 2210 displays a matrix in which the cues correspond to the vertical axis, and are divided into three such that the output link corresponds to the horizontal axis. Each element of the matrix is divided into black, checkered, and diagonal lines, which represent spatial priorities in the order described.

The distribution arbiters 2210 to 2230 perform contention control on distribution stage output links for individual queues, and then output the contention control results to the encoder 22120 using the signal lines 22111 to 22113. These distribution information (22111-3, 22211, 22311) are n ₁ bits, respectively, indicating that a specific queue is assigned per specific distribution switch output link. Using this property, these distribution information (22111 to 22113), which are a total of lxn ₁ bits per individual distribution arbitrator, are encoded (22120 to 22210) with a queue number allocated per output link and reduced to n ₁ x log (l) bits. The information 22114 to 22116 is output to the combined arbitrators 23110 to 23310. Accordingly, the distribution contention control result output from the distribution arbiters 2210 to 2230 is log (l) bits corresponding to the queue number allocated to each of the n ₁ distribution end output links, and is fetched to indicate priority information. Cycle identification information is added.

The contention-controlled distribution information 22111 ˜ 3, 22211, and 22311 are unit-switched at the same switching stage 1200 so that the queued packets may be fetched through the output terminal of the distribution switch by each distribution arbiter 2210 ˜ 2230. Classified by modules 1210-1230, contention control is again performed on output links of the switching stage 1200 by the coupling arbiters 2310-2330. That is, in FIG. 2, the signals 22111, 22211, and 22311, which are the distribution control results for the queues 21110, 21210, and 21310, are distributed contention for packets destined for the same switching stage 1200 unit switch modules 1210 to 1230. Since the control result signals are input to the coupling arbiter 2310, contention control for the switching stage 1200 output link 1610 is performed.

Coupling arbitrators 2310 to 2330 control packet contention occurring at the coupling stage 1300, the input link 1610, or the switching stage 1200, the output link 1610. The information 23110 decoded the arbitration information 22114 ˜ 6, 22214, and 22314, abbreviated to log (l) bits, corresponds to the corresponding value of the distribution switch when a bit corresponding to a specific queue number indicates a logical value true. This means that the packet can be drawn out to the coupling end 1300 through the output link. A maximum of ixk ₁ packets can be introduced from different distribution switches to the same switching stage unit switch module, and the incoming packets in this particular packet entry cycle are specified via k ₂ output links 1610 in subsequent packet output cycles. It may be input to the coupling switch 1310.

Coupling the arbiter (2310-2330) is k _2, which may be eventually allow output in the ixk ₁ of distributing arbitration information generated for l of coupling a single switching stage per stage 1200, a unit switch modules (1210-1230) The function of selecting a dog is performed on all the unit switch modules 1210 to 1230 of the switching stage 1200.

Accordingly, the combined arbiters 2310-2330 are k k l for each matrix element whose logical value is true in the (ixk ₁ ) xl distributed mediation signal matrix 23110-23310 which is composed of the output signals of the distributed arbiters 2210-2230. It performs the task of selecting _two. This selection process is performed according to the spatial priority according to the output link selection priority procedure available to the destination queue as described above, and simple round-robin with fixed priority when k ₁ = k ₂ = 1. Same as the matching operation.

As shown in FIG. 2, the coupling arbiter matrix 23110 is a case in which k ₁ = k ₂ = 1, and three queues correspond to the vertical axis, and a matrix divided into three such that three links correspond to the horizontal axis is displayed. It is. Each element of the matrix is divided into black, checkered, and diagonal lines, each of which has the spatial priority of the order mentioned. Here, the coupling arbiter 2310 performs contention control for the coupling end input links by a known round-robin matching operation starting from a black pattern row for each column and proceeding in a checkered row direction.

Internal blocking contention control is performed on the distribution end and switching end output links by the coupling arbiters 2310-2330 to indicate whether a destination-specific queue distributed through the link can transmit a packet. The arbitration result in 23310 is encoded by the encoders 23120 to 23320, converted into 1-bit result information 23112, and introduced into the decoder 22120 in the distribution arbiter 2210. The inputted and stored combined arbitration request signals 22111 to 22113 are initially input and decoded (21112 to 21132), and distributed to the queue controllers 2110 to 2130 for each destination queue. At this time, the queue controllers 2110 to 2130 control to fetch packets sequentially in the order of packets stored in the HOL to output links allocated to their own queues, as indicated in the arbitration result information, and transmit them to the distribution end.

As described above, the internal blocking arbiter 2000 for the distributed combining packet switch has a feature of assigning a fixed spatial priority to every arbitration cycle for the links to be used by the unit switching modules. Here, the reason for limiting the fixed link space priority allocation to each outgoing arbitration cycle is that the space priority allocation for each arbitration cycle can be reset for the fair performance of the switch per link circuit. Arbitration cycle information must be available in synchronization. Due to this feature, we can simulate that only one withdrawal arbitration cycle, that is, distribution arbiter and combined arbiter, can achieve more than 90% of processing efficiency under all switch input load conditions even with one arbitration.

In high load operation, where all destination queues have stored packets, every queue has k ₁ dedicated packet outgoing links that are fixedly allocated according to link allocation space priority. Thus, under random and fair packet input conditions, they operate as M / D / 1 queues. Therefore, in this case, the processing delay time of the distributed combining packet switch 1000 has a value of (k ₁ +1) Do / k ₁ when the ideal processing delay time of the output buffer switch is Do, and k ₁ is sufficiently larger than one. It is close to the ideal output buffer characteristics, and has an excellent performance of only twice the output buffer switch performance even in an economical structure with k ₁ . Of course, the switch saturation throughput is 100%. That is, strictly non-blocking.

3 and 4, the configuration and operation of the distribution arbiter 2210 for the internal blocking arbiter will be described in more detail.

FIG. 4 shows the components of the distribution arbiter and its operation algorithm. FIG. 3 shows the distribution arbiter for distribution switch with five queues and five output links, constructed using 25 components of FIG. have.

As shown in FIG. 4, the component 4000 of the distribution arbiter may include an operation initialization signal rst, an operation synchronization signal tck, remaining number of queue input information rqn_i, and remaining number of queue output information rqn_o. , Packet reservation input information (grh_i), link reservation output information (grh_o) indicating whether a corresponding link is selected by another component having a high spatial priority, and a packet output is output to queues and links corresponding to the component. It has an input / output signal containing information (odisel) indicating whether it is reserved.

The component 4000 of the distribution arbiter performs the following operation by using rqn_i, which is information on the remaining number of queues, and grh_i, which is information indicating whether a packet has been allocated to a corresponding output link by a previous component.

If rqn_i is not zero (i.e., there are remaining packets that can be allocated) and grh_i is '0' (i.e. no corresponding output link is preempted by the previous component with higher spatial priority) , rqn_i -1 is assigned to rqn_o, and logical value '1' is assigned to grh_o for output. At this time, odisel has a logical value '1' indicating that a packet is allocated to a corresponding queue and a corresponding output link.

Otherwise, rqn_o is outputted with rqn_i input value and grh_o with grh_i input value. In the same case, odisel has a logical value of '0', meaning that no packet is allocated to the queue and the corresponding output link.

The operation as described above is the same as the component operation algorithm indicated by "4100" in FIG. The rst and tck signals shown in FIG. 4 are synchronization clock and component operation initialization signals that control every arbitration cycle.

3 shows an example of a configuration of a distribution arbiter 3000 consisting of components 4000.

The distribution arbiter 3000 may include a space switch 3200, components of FIG. 4 (3800, 3810, 3900, etc.), connection signal lines 3700 and 3600 connecting them, and distribution arbitrator I / O signal stages 3100 and 3500. It consists of.

The spatial switch 3200 variably assigns the output link spatial priority of the queues 1111 to 1113 according to the arbitration drawing cycle and the position in the switch of the distribution arbiter.

Inputs of the spatial switch 3200 are the remaining packet information signals 21111-21131 3100 emitted from the queue controllers 2110-2130, and the in-switch position information signal 3400 of the arbitration withdraw cycle and distribution arbiter, " The input signal 3100 is rotated and output to the output terminal 3300 according to the signal of 3400 ". That is, the space switch 3200 performs a barrel shifter operation.

The core part of the distribution arbiter, which forms a rectangular matrix with the components of Fig. 4, the queues correspond to the column axis, and the output link of the distribution switch corresponds to the row axis. The rqn_i of the component on the diagonal axis receives the remaining packet information of the queue controller input according to the spatial priority determined by the spatial switch 3200. In addition, grh_i of the component on the diagonal axis is fixed to the logical value '0' (3810), so that these positions are the starting point of the distribution arbitration, and has the highest priority. In addition, the components located on the diagonal axis also block the asynchronous feedback loop in the hardware implementation.

In the matrix composed of the components of FIG. 4, the row axis signals grh_i and grh_o are connected by the signal lines 3600 to form loops, and the row loop signal lines pass through the diagonal components and the loops are broken. In addition, the column axis signals rqn_i and rqn_o are connected by the signal line 3600 to form a loop, and these column loop signal lines are broken through the diagonal components. For convenience, the rst and tck signals commonly input to the components are not shown in FIG. 3.

When the queue remaining packet information is input to the distribution arbiter of FIG. 3, the distribution arbiter performs a function of equally distributing packets to be output to the output link according to the link space priority of each queue. The distributed result is a signal of n ₂ bits per cue and is led to the coupling arbitrator through the output terminal 3500. The implementation of the distribution arbiter using 0.2 um CMOS semiconductor technology required a logic element of about 250 kgates in a 64 x 64 matrix and a maximum operating speed of about 37 ns. Assuming that the packet slot time is four times the maximum operating speed, a distribution controller for about 15 Terabit / sec distribution-coupled packet switches can be implemented using conventional semiconductor technology.

Now, the configuration and operation of the combined arbiter 2310 for the internal blocking arbiter will be described in more detail with reference to FIGS. 5 and 6.

FIG. 6 shows the components of the combined arbitrator and its operating algorithm. FIG. 5 shows a distribution switch with five queues and a combined switch with five input links configured using 25 components of FIG. Shows a combined mediator.

The combined arbitrator component 6000 shown in FIG. 6 is an operation initialization signal rst, information (init_d) for indicating whether it is located at the diagonal axis 5300 of the component matrix, indicating the start point of the arbitration operation upon initialization, Arbiter operation synchronization signal (tck), remaining number of unallocated combined end input links (rqn_i), remaining number of unallocated combined end input links (rqn_o), other components with high spatial priority Information indicating whether a corresponding link has been selected by (grh_i), link reservation output information (grh_o), and a pointer input signal for specifying a component having the highest priority, that is, the starting point of the arbitration operation every arbitration cycle ( po_i), the pointer output signal po_o, the 1 bit arbitration input information corresponding to the corresponding component among the n ₂ bits input signals output from the distribution arbiter, and the corresponding The queues and links corresponding to the component have input and output signals of ocsels indicating whether the packet output has been reserved by the joint arbiter. The component 6000 of the coupling arbiter performs the following operations using the input signals.

In FIG. 6, reference numeral 6100 describes an operation initialization operation of the component 6000. That is, if rst is true, it means that the corresponding component has the highest priority. In hardware, it is possible to logically set po_o, which serves as a feedback blocking point of the asynchronous loop signal in the arbiter 5000. Initialize to '1' to declare that the component is located on the diagonal axis of the matrix (5300). In addition, if rst is true, since the operation is initiating, it declares that the mediation result signal ocsel is '0' and is not mediated.

In FIG. 6, reference numeral 6200 describes the present operating state of component 6000. In other words, if po_o is true, the component is on the diagonal of the matrix and therefore has the highest spatial priority. Accordingly, if the distribution arbitration result is true because k ₂ coupling end input links that can be assigned to the queue are unassigned, rqn_o is assigned k ₂ -1, and grh_o means that the element is reserved for arbitration. And ocsel are assigned logical value true. However, if disel is false, the component has the highest priority, but rqn_o is assigned k ₂ because there is no distribution arbitration result, and grh_o and ocsel are logically assigned false, meaning that the element is reserved for arbitration. Receive.

On the other hand, if po_o is false, i.e., the component is located outside the diagonal of the matrix, disel is true, grh_i is false, and rqn_i is not zero, i.e., distribution mediation results in packets being delivered to the corresponding queue and link, and higher If the link is not preempted by the priority component and there is a join input link that can be assigned, rqn_o is assigned a value of -1 from the value of the entered rqn_i, grh_o meaning that the element is reserved for arbitration. And ocsel are assigned logical value true. However, if disel is false, disel is false, grh_i is true, or rqn_i is 0, rqn_o is assigned the value of the entered rqn_i because there is no distribution arbitration result, meaning grh_o and ocsel mean that the element is reserved for arbitration. Is assigned the logical false.

In FIG. 6, the pointer signal po_o, which means to be positioned on the matrix diagonal axis after the initializing operation at 6000, is shifted to a component located on the right side (or left side) every arbitration cycle.

In FIG. 5, reference numeral 5000 denotes a combined arbiter, receives an input signal 5100 that is a distribution arbitration result of lxn ₂ bits, and distributes the same to the corresponding components 5300. Among the components located in each row axis, _two components k whose distribution mediation results are true are selected and the packets corresponding to them can be reached until the final coupling switch without internal blocking. To notify the queue controller. Here, the row loop signal line 5600 represents passages connecting the po_i, po_o and rqn_i, rqn_o signals, and the column loop signal line 5700 shows the passages connecting the grh_o and grh_i signals.

Now, with reference to FIG. 7, the performance of the distributed packet switching device (distributed packet packet switch) according to the present invention will be described.

The distribution switch, the switching unit unit switch, and the combined switch are equally 64x64, and the distribution switch is switched when the load is equally and randomly applied to the 4096x4096 distributed packet packet switch configured in the form of a CLOS switch network with a single link connection. The delay characteristic computer simulation results are shown in FIG. 7.

As shown in FIG. 7, the delay value of about twice the ideal output buffer switch characteristic is shown as a whole.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

As described above, the present invention provides an effect of enabling one hop switching in a next-generation packet network through an arbitration scheme having a high throughput by using a spatial priority assigned to each queue to use an inner link. There is.

Claims (8)

A distributed combining packet switching device in a next generation packet network, distribution means consisting of i (where i is any natural number) m _1i xn ₁ unit switch modules; Switching means consisting of j (where j is any natural number) m ₂ x n ₂ unit switch modules; coupling means consisting of l ₃ x n _3l unit switch modules (where l is any natural number); And Connecting means for connecting said distribution means and said switching means, said switching means and said coupling means; _Wherein i m _1i xn ₁ unit switch module is provided with l queues (equal to the number of l m ₃ x n _3l unit switch modules in the coupling means), the queue for each internal link use Distributed arbitration-mediated switching according to the specified cyclic space and time priority, and can directly accommodate various speeds of subscriber station or network matching devices, enabling one hop switching in one switching. Distributing combined packet switching device, characterized in that. The method of claim 1, Each unit switch module of the distribution means, I queue controllers for controlling packet input / output for the l queues of the distribution switches; A distribution arbiter for inputting the number of packets stored in the l queues of the i queue controllers (individual queue controllers) to an output link of the distribution switch or to switches in the switching means; And A joint arbiter for arbitrating the switching means output link contention of packets distributed in the distribution arbiter And cyclically distribute spatial and temporal priorities that do not overlap each other in the link links in the switch, and the arbitration information communicating between the distribution arbiter and the combined arbiter is log (l) +1+. And (mediation cycle identification) bits. The method of claim 1, Each unit switch module of the distribution means, I queue controllers for controlling packet input / output for the l queues of the distribution switches; A distribution arbiter for inputting the number of packets stored in the l queues of the i queue controllers (individual queue controllers) to an output link of the distribution switch or to switches in the switching means; an encoder for encoding n ₂ bit distribution information into a log (l) bit queue number assigned to the link; A decoder for decoding the encoded log (l) bit distribution information and restoring it to n ₂ bit distribution information; And J combining arbiters for arbitrating the switching means or the combining means input / output link contention of packets distributed in the distribution arbiter Distributed packet switching device comprising a. The method of claim 3, wherein Each unit switch module of the distribution means, In internal blocking arbitration operation, it is recommended to efficiently use internal link resources by communicating only log (l) bits corresponding to queue numbers in the distributed switch per link, 1 bit indicating whether arbitration is allowed, and identification signals for arbitration cycle synchronization. Distributing combined packet switching device characterized in that. The method according to any one of claims 2 to 4, The distribution arbitrator, As an element, it corresponds to the operation initialization signal rst, the operation synchronization signal tck, the remaining number of queue input information rqn_i, the remaining number of queue output information rqn_o, and other components having a high spatial priority. It has input and output signals of information (grh_i), link reservation output information (grh_o), and information (odisel) indicating whether the packet output is reserved to the queue and link corresponding to the component, Using the remaining number information (rqn_i) of the queue and information (grh_i) indicating whether a packet has been allocated by a previous component to a corresponding output link, The components form a rectangular matrix, the column axis corresponding to the distribution switch queues, the output link of the distribution switch corresponding to the row axis, and the rqn_i of the component on the diagonal axis being defined by a spatial switch. The remaining packet information of the queue controller inputted at the determined spatial priority is input, and the grh_i of the component on the diagonal axis is fixed to the logical value '0' 3810, and these positions are the starting point of the distribution arbitration. The components having the highest priority, and these diagonally arranged components, block the asynchronous feedback loop in hardware implementation, receive queue remaining packet information, and send packets to the output link to be released according to link space priority of each queue. Distribution-combined packet switching device, characterized in that evenly distributed. The method of claim 5, The component is, If rqn_i is not 0 (i.e., there are remaining packets that can be allocated) and grh_i is '0' (i.e., no corresponding output link is preempted by a previous component with a higher spatial priority) ), And assigns the value -1 from rqn_i to the rqn_o. Logical value '1' is allocated to the grh_o and output, and the odisel has a logical value '1' indicating that a packet is allocated to the corresponding queue and the corresponding output link. Otherwise, the rqn_o is the rqn_i input value, The grh_o input value is allocated to the grh_o as it is and is outputted. In the same case, the odisel has a logical value '0' indicating that a packet is not allocated to the corresponding queue and the corresponding output link. . The method according to any one of claims 2 to 4, The combined mediator, As an element, an operation initialization signal (rst), information (init_d) for indicating whether the mediation operation is initiated at initialization and located on a diagonal axis of the component matrix, an arbitrator operation synchronization signal (tck), an unassigned combination The remaining number of input links (rqn_i), the remaining number of unallocated combined end input links (rqn_o), the information indicating whether the corresponding link is selected by other components having a high spatial priority (grh_i) ), Link reservation output information (grh_o), a pointer input signal (po_i) for specifying the start point of the arbitration operation, i.e., the component having the highest priority, in every arbitration cycle, the pointer output signal (po_o), and the Arbitration input information (disel) corresponding to the corresponding component among the bit input signals outputted from the distribution arbiter, and to the queue and link corresponding to the corresponding component Has input and output signals of ocsels indicating whether the packet output is reserved by the coordinator, A rectangular matrix is formed of the components, the input signals resulting from the distribution mediation are received, distributed to the corresponding components, and the components having the distribution mediation result (disel) are selected among the components located in each row axis. A distributed combining packet switching device, comprising notifying the queue controller using the combined arbitration result output signal that packets corresponding to them can be reached without the internal blocking. The method of claim 7, wherein The component is, In the initialization operation, if the synchronous clock (rst) that controls the mediation cycle is true, it means that the component has the highest priority, and in hardware, the feedback of the asynchronous loop signal in the arbiter Initialize the po_o acting as a blocking point to a logical value '1' to declare that the corresponding component is located on the diagonal axis of the matrix, and if the rst is true, the operation initialization step if the rst is true, the ocsel as an arbitration result signal Declares an unmediated state with '0', In the present operation, if po_o is true, since the component is positioned diagonally to the matrix, the component has the highest spatial priority. Thus, a predetermined number of coupling means input links that can be allocated to the corresponding queue are not assigned. If the distribution mediation result (disel) is true, the rqn_o is assigned -1 in a predetermined number, and the grh_o and the ocsel are assigned the logical value true, meaning that the element is reserved for arbitration, and if the disel is false Since the component has the highest priority but there is no distribution arbitration result, the rqn_o is allocated the predetermined number, and the grh_o and the ocsel, which mean that the element is reserved for arbitration, are assigned as logical false, If po_o is false (i.e. component is located outside of the matrix diagonal), if disel is true and grh_i is false and rqn_i is not zero (i.e., distribution mediation results in a packet forwarded to the corresponding queue and link) If the link is not preempted by a higher priority component and there is a combined input link that can be allocated), the value of -1 from the value of the rqn_i inputted by the rqn_o is assigned. The grh_o and the ocsel are assigned a logical value of true, meaning that the element is reserved for arbitration, If the disel is false, the disel is false, the grh_i is true, or the rqn_i is 0, there is no distribution arbitration result, so the rqn_o is assigned the value of the rqn_i inputted, and that the element is reserved for arbitration. The apparatus of claim 1, wherein the grh_o and ocsel are allocated as logical false.