KR20030071199A - Method of manufacturing dram cell transistor - Google Patents

Abstract

PURPOSE: A method for fabricating a dynamic random access memory(DRAM) cell transistor is provided to reduce a threshold voltage of a cell transistor and a decrease of current by using an inverse narrow width effect without changing a cell size. CONSTITUTION: An ISO pattern(1) defining an active region(2) is designed to have a serif in its center. The serif extends to have a size corresponding to the entire width of a gate pattern overlapping the serif so that the transistor increases in width. Both ends of the ISO pattern have a relatively narrow width to broaden the spacing between adjacent ISO patterns.

Description

DRAM cell transistor manufacturing method {METHOD OF MANUFACTURING DRAM CELL TRANSISTOR}

The present invention relates to a method of manufacturing a DRAM cell transistor, and more particularly, to a layout of a DRAM cell transistor capable of preventing a threshold voltage Vt decrease and a current decrease of a cell transistor without increasing a cell size or changing a process. .

As is well known, semiconductor devices are implemented based on layouts. The layout corresponds to a schematic drawing, and various patterns in the semiconductor device are formed as designed in the layout, and thus the layout is designed to optimize various patterns implemented horizontally and vertically on the substrate.

In addition, since the layout affects not only the device structure finally obtained but also the manufacturing process for implementing the device, the layout is designed in consideration of a process margin.

1 is a layout diagram of an ISO and a gate pattern for manufacturing a DRAM cell transistor according to the prior art.

As shown, the ISO pattern 1 is designed to have a serif (S) at the center thereof in consideration of the process margin, and the gate pattern 3 has a line shape as a whole, and the ISO pattern in consideration of device characteristics. The part overlapping with both ends of (1) is designed to have a relatively narrow width.

Here, the serif S is provided only in the center of the ISO pattern 1, so that the width of the center of the mask pattern formed to cover the active area in the semiconductor manufacturing process, more precisely, the photolithography process is relatively smaller than the edge width. Loss is to prevent the phenomenon, and is usually provided in a size overlapping with a portion of the gate pattern.

In addition, relatively narrowing the width of the gate pattern portion overlapping the both ends of the ISO pattern 1 corresponds to the junction region of the actual cell transistor, more precisely, the source region 4, and thus the source region ( This is to secure stable device characteristics by widening the area of 4).

In Fig. 1, reference numeral 2 denotes an active region defined by the ISO pattern, 5 denotes a drain region in a cell transistor, and 6 denotes an isolation region other than the active region.

However, when the DRAM cell transistor is manufactured using the layout as shown in FIG. 1, the following problem exists.

The ISO pattern must be reduced in size in accordance with the trend toward high integration. However, since the ISO pattern corresponds to the active region in the actual semiconductor device, if the size of the ISO pattern is reduced, the channel size of the cell transistor is reduced as a result, and thus the inverse narrow effect is obtained in the actually obtained semiconductor device. The threshold voltage (Vt) of the cell transistor and the current (Current) decrease due to the width effect), and thus device characteristics cannot be secured.

Accordingly, the present invention has been made to solve the above problems, a method of manufacturing a DRAM cell transistor that can prevent the threshold voltage (Vt) decrease and current reduction of the cell transistor by the inverse narrow whistle effect due to high integration The purpose is to provide.

1 is a layout diagram of an ISO and a gate pattern for manufacturing a conventional DRAM cell transistor.

2 is a layout diagram of an ISO and a gate pattern for manufacturing a DRAM cell transistor according to an embodiment of the present invention.

3 is a layout diagram of an ISO and a gate pattern for fabricating a DRAM cell transistor according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1: ISO pattern 2: Active area

3: gate line 4: source region

5: drain region 6: device isolation region

In the method for manufacturing a DRAM cell transistor of the present invention for achieving the above object, in the method for manufacturing a DRAM cell transistor based on a layout, when designing a DRAM cell layout, an ISO pattern defining an active region is located at the center thereof. Designed to have a serif, it is characterized in that the transistor width is increased by expanding the design to have a size corresponding to all of the width of the gate pattern overlapping the serif.

According to the present invention, it is possible to reduce the threshold voltage drop and the current decrease of the cell transistor due to the inverse narrow whis effect by maximizing the size of the active region under the gate pattern without changing the cell size.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a layout diagram of an ISO and a gate pattern for fabricating a DRAM cell transistor according to an embodiment of the present invention. Here, the same parts as in Fig. 1 are designated by the same reference numerals.

As shown, according to the present invention, in the DRAM cell layout for manufacturing a DRAM cell transistor, the gate pattern 3 has a line shape as in the prior art, and a portion where the gate pattern 3 overlaps with both ends of the ISO pattern 1 has a relatively narrow width. While the ISO pattern 1 defining the active region 2 and the device isolation region 6 is designed to have a serif S at the center thereof, the serif S is shown in FIG. 1. It is designed to extend from the conventional one. In other words, the present invention is not designed to overlap the serif S with a part of the gate pattern 3, but is designed to be extended to overlap the entire width of the gate pattern.

In this case, the ISO pattern 1 substantially limits the width of the cell transistor while limiting the size of the active region 2. When the width of the gate pattern 3 overlapping with the serif S is widened, the gate Since the width of the active region under the pattern 3, that is, the substantial channel width of the cell transistor is increased, the threshold voltage of the cell transistor due to the inverse narrow whis effect due to the high integration of the semiconductor device without additional cell size increase or process change. Degradation and current reduction can be reduced.

In FIG. 2, unexplained reference numerals 4 and 5 denote source and drain regions.

3 is a layout diagram of an ISO and a gate pattern for fabricating a DRAM cell transistor according to another embodiment of the present invention, as shown, the layout in this embodiment is compared with that of the previous embodiment. 2), and more precisely, the width of the portion of the ISO pattern which does not play a role in the cell transistor is relatively reduced.

In this case, the spacing between neighboring ISO patterns 1, which are relatively reduced due to the size expansion of the serif S, may be widened, thereby securing a process margin. At this time, since both ends of the ISO pattern overlapping the gate pattern 3 have no role in the actual cell transistor, even if the width thereof is reduced, the device is not affected.

Therefore, when the size of the serif in the ISO pattern is extended and the width of both ends thereof is reduced, process margins can be secured while preventing defects due to high integration without increasing the cell size and changing the process.

As described above, the present invention can increase the channel width of the cell transistor under the gate pattern to the maximum by expanding the size of the serif included in the ISO pattern, and thus, the inverse narrow whis effect without changing the cell size. By reducing the threshold voltage and the current reduction of the cell transistor, the device characteristics can be secured.

Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (2)

In the method for manufacturing a DRAM cell transistor based on the layout, When designing a DRAM cell layout, an ISO pattern defining an active area is designed to have a serif at the center thereof, but an extended design is designed to have a size corresponding to all of the gate pattern widths overlapping the serif so that the transistor width is increased. A method of manufacturing a DRAM cell transistor, characterized in that. The method of claim 1, wherein the ISO pattern is A method of manufacturing a DRAM cell transistor, in which both ends thereof are designed to have a relatively narrow width in order to widen spacing between adjacent ISO patterns.