KR20030067932A - Method and apparatus for dispersing sustaing current of plasma display panel - Google Patents

Abstract

PURPOSE: A method and an apparatus for dispersing sustain current of a PDP are provided to stabilize a sustain operation and reduce EMI(Electro-Magnetic Interference) by dispersing the current in a sustain discharge process. CONSTITUTION: A discharge operation is performed by supplying the first sustain pulse to the first electrode of an electrode group. The discharge operation is performed by supplying the second sustain pulse to the second electrode of an electrode group. The first sustain pulse and the second sustain pulse are delayed. The discharge operation is performed by supplying the first sustain pulse to the third electrode of the electrode group. The discharge operation is performed by supplying the second sustain pulse to the fourth electrode of the electrode group.

Description

METHOD AND APPARATUS FOR DISPERSING SUSTAING CURRENT OF PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method and apparatus for dispersing a sustain current of a plasma display panel to disperse current during sustain discharge to stabilize sustain operation and to reduce electromagnetic interference (EMI).

The plasma display panel (hereinafter referred to as "PDP") displays an image using visible light generated from the phosphor when ultraviolet rays generated by gas discharge excite the phosphor. PDP is thinner and lighter than the cathode ray tube (CRT), which has been the dominant display device, and has the advantage of enabling high-definition / large screens.

The PDP is driven by dividing one frame into several subfields having different number of emission times in order to realize gray level of an image. Each subfield is divided into an initialization period for initializing cells on the full screen, an address period for selecting discharge cells, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields. In addition, each of the eight subfields is divided into an address period and a sustain period. Here, the initialization period and the address period of each subfield are the same for each subfield, while the sustain period and the number of discharges thereof are 2 ⁿ (n = 0,1,2,3) in each subfield in proportion to the number of sustain pulses. , 4,5,6,7). As described above, since the sustain period is changed in each subfield, gray levels of an image can be realized.

1 shows an example of a driving waveform supplied to a PDP during one subfield period. In Fig. 1, Y represents a scan electrode and Z represents a sustain electrode. And X represents an address electrode.

Referring to FIG. 3, a rising ramp waveform Ramp-up is simultaneously applied to all scan electrodes Y in the initialization period. Ramp-up causes a slight discharge to occur in the cells of the full screen, creating wall charges in the cells. After the rising ramp waveform Ramp-up is supplied, the falling ramp waveform Ramp-down is simultaneously applied to the scan electrodes Y. The falling ramp waveform causes a slight erase discharge in the cells, thereby uniformly retaining wall charges necessary for the address discharge in the cells of the full screen.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

The sustain electrode Z is supplied with a positive DC voltage Zdc during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the common sustain electrodes Z. FIG. The cell selected by the address discharge is sustain discharge discharged in the form of surface discharge between the scan electrode (Y) and the sustain electrode (Z) each time the sustain pulse (sus) is applied as the wall voltage and the sustain pulse (sus) in the cell are added. This will happen.

However, in the conventional PDP, since the peak value of the current generated due to the sustain pulse applied to the scan electrodes Y or the sustain electrodes Z simultaneously during the sustain period is very large, the electromagnetic interference is large and the sustain is high. There is a problem that the margin is small. This will be described in detail with reference to FIGS. 2 and 3 as follows.

Referring to FIG. 2, the sustain pulse is applied to all the scan electrodes Y1 to Yn at the same time and then to the sustain electrodes Z at the same time. In each of the sustain pulses, a sustain discharge occurs in the cells selected by the address discharge and a discharge current i is generated. The discharge current i flows from the scan electrodes Y1 to Yn toward the sustain electrodes Z at time t1 as shown in FIG. 3A, and from the scan electrodes Y1 to Yn at time t2 as shown in FIG. 3A. Flow toward the field (Z). This discharge current (i) may vary for every horizontal line. This is because the number of cells selected by the address discharge is different for each horizontal line. In the case of 42 ″ PDP, the sum of the discharge currents i is approximately 100 [A] or more when the full screen simultaneously sustains discharge. This large discharge current (i) increases the EMI. In addition, the discharge current i causes a voltage drop of the sustain voltage of the sustain pulse. When the full discharge cell is turned on, that is, when the discharge current i becomes maximum, the voltage drop amount of the sustain voltage becomes maximum. As a result of the voltage drop of the sustain voltage, the sustain discharge is weakly generated, the luminance is lowered, the sustain voltage margin is reduced, and the sustain discharge may not occur even when the sustain pulse is applied.

Accordingly, it is an object of the present invention to provide a method and apparatus for dispersing sustain current of a PDP to stabilize the sustain operation and reduce electromagnetic interference (EMI) by distributing current during sustain discharge.

1 is a waveform diagram showing a driving waveform for driving a conventional plasma display panel.

2 is a waveform diagram showing a discharge pulse generated during sustain pulses and sustain discharge in a conventional plasma display panel.

FIG. 3A is a diagram showing a discharge current flowing at a time point t1 in the waveform diagram shown in FIG. 2.

3B is a view showing a discharge current flowing at a time point t2 in the waveform diagram shown in FIG. 2.

4 is a block diagram illustrating a sustain current spreading apparatus of a plasma display panel according to a first embodiment of the present invention.

FIG. 5 is a waveform diagram illustrating driving waveforms generated from each driver shown in FIG. 4.

FIG. 6 is an enlarged waveform diagram of the sustain pulse shown in FIG. 5 and illustrates a waveform of the discharge current generated during the sustain discharge.

7 is a block diagram illustrating a sustain current spreading apparatus of a plasma display panel according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating in detail the delayer illustrated in FIG. 7.

FIG. 9 is a waveform diagram illustrating sustain pulses and a discharge current in the sustain current spreader of the plasma display panel shown in FIG.

<Description of Symbols for Main Parts of Drawings>

41, 71: address driver 42a, 42b, 72: scan driver

43a, 43b, 73: sustain driver 44, 76: timing controller

74a to 74d, 75a to 75d: Delay 81: Delay circuit

In order to achieve the above object, the sustain current dispersion method of the PDP according to the embodiment of the present invention to supply a first sustain pulse to the first electrode to cause a discharge, and to the second electrode facing the first electrode second Supplying sustain pulses to cause discharge, delaying the first and second sustain pulses, supplying delayed first sustain pulses to a third electrode to cause discharge, and performing the delayed second sustain pulses. Causing a discharge to the fourth electrode opposite the three electrodes.

The sustain current dispersion method of the PDP according to the embodiment of the present invention further includes generating a control signal indicative of the start point of the sustain pulse.

The sustain current dispersion method of the PDP according to the embodiment of the present invention is characterized in that the sustain pulses are delayed in response to the control signal.

The sustain current dispersion method of the PDP according to the embodiment of the present invention is characterized in that the sustain pulses are delayed by using a delay element.

According to an embodiment of the present invention, a sustain current spreader of a PDP includes a first driver configured to supply a first sustain pulse to a first electrode to generate a discharge, and a second electrode included in an electrode group and opposed to the first electrode. A second driver for supplying sustain pulses to cause discharge, a delay for delaying the first and second sustain pulses, a third driver for supplying delayed first sustain pulses to the third electrode to cause discharge, and a delayed second sustain And a fourth driver for discharging the pulse to the fourth electrode facing the third electrode.

The retarder may generate a control signal indicative of the time when the sustain pulse is generated, and supply a control signal to each of the driving units to control the time when the sustain pulse is generated.

The retarder is characterized in that to delay the sustain pulses using a delay element.

The delay unit includes a timing controller for generating a control signal indicative of a period in which the sustain pulse is supplied, a delay unit connected between the driving units and the electrodes to delay the sustain pulse having only a predetermined delay value, and a driving unit in response to the control signal. And a switch element for switching a current path between the field and the delay unit.

The retarder is characterized by delaying the sustain pulse by the RC time constant determined by the combination of the resistor and the capacitor.

Other objects and features of the present invention in addition to the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 9.

FIG. 4 schematically shows a sustain current dispersing device of a PDP according to a first embodiment of the present invention, and FIG. 5 shows signals output from the respective driving units shown in FIG.

4 and 5, the sustain current dispersing apparatus of the PDP according to the first embodiment of the present invention is configured to drive the odd scan electrodes Y1, Y3, ... Yn-1 of the PDP 40. The first scan driver 42a, the second scan driver 42b for driving the even scan electrodes Y2, Y4 ... Yn of the PDP 40, and the odd sustain electrodes Z1 of the PDP 40. The first sustain driver 43a for driving Z3... Zn-1 and the second sustain driver 43b for driving even sustain electrodes Z2, Z4 ... Zn of the PDP 40. ) And a timing controller 44 for controlling the respective driving units 42a, 42b, 43a, 43b.

In the PDP 40, m address electrodes X1 to Xm and n sustain electrode pairs Y1 to Yn and Z1 to Zn are orthogonal to each other, and m × n cells are formed at each intersection thereof. The address electrodes X1 to Xm of the PDP 40 are driven by the address driver 41.

The address driver 41 performs inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like, and then stores data mapped to each subfield by the subfield mapping circuit to the address electrodes X1. To Xm) at the same time.

The first scan driver 42a supplies the ramp ramps Ramp-down to the odd scan electrodes Y1, Y3 ... Yn-1 simultaneously after the ramp ramps are supplied during the initialization period. Done. Subsequently, the first scan driver 42a sequentially supplies the scan pulse SCAN to the odd scan electrodes Y1, Y3 ... Yn-1 to select a scan line, and then the odd scan electrodes The sustain pulse SUSY1 is simultaneously supplied to Y1, Y3 ... Yn-1).

The second scan driver 42b supplies the rising ramp waveform Ramp-down to the even scan electrodes Y2, Y4 ... Yn at the same time after the rising ramp waveform Ramp-up is supplied during the initialization period. . Subsequently, the second scan driver 42b sequentially supplies the scan pulse SCAN to the even scan electrodes Y2, Y4 ... Yn to select a scan line, and then the even scan electrodes Y2, during the sustain period. The sustain pulse SUSY2 is simultaneously supplied to Y4 ... Yn).

The sustain pulse SUSY1 supplied to the odd scan electrodes Y1, Y3 ... Yn-1 and the sustain pulse SUSY2 supplied to the even scan electrodes Y2, Y4 ... Yn have a predetermined time difference. Δt) is out of phase.

The first sustain driver 43a supplies a positive DC voltage to the odd sustain electrodes Z1, Z3 ... Zn-1 in a sustain period during which a falling ramp waveform is supplied and an address period. During this period, the sustain pulse SUSZ1 is supplied to the odd sustain electrodes Z1, Z3... Zn-1 alternately with the first scan driver 42a.

The second sustain driver 43b supplies the positive DC voltage to the excellent sustain electrodes Z2, Z4... Zn during the period in which the falling ramp waveform is supplied and the address period, and then during the sustain period. The sustain pulse SUSZ2 is supplied to the even sustain electrodes Z2, Z4... Zn alternately with the one scan driver 42b.

The sustain pulse SUSZ1 supplied to the odd sustain electrodes Z1, Z3 ... Zn-1 and the sustain pulse SUSZ2 supplied to the even scan electrodes Z2, Z4 ... Zn have a predetermined time difference. Δt) is out of phase.

Each of the address driver 41, the first and second scan drivers 42a and 42b, and the first and second sustain drivers 43a and 43b may include an energy recovery circuit.

The timing controller 44 receives the vertical / horizontal synchronization signals H and V, and receives the timing control signals CAdd, Cscan1, Cscan2, Csus1, and Csus2 necessary for each of the driving units 41, 42a, 42b, 43a, and 43b. And the timing control signals CAdd, Cscan1, Cscan2, Csus1, and Csus2 are supplied to the corresponding driving units 41, 42a, 42b, 43a, 43b. Here, the control signal CAdd supplied to the address driver 41 includes a sampling clock of the shift register, a latch / output signal of a latch, and the like. The control elements Cscan1, Cscan2, Csus1, and Csus2 supplied to the first and second scan drivers 42a and 42b and the first and second sustain drivers 43a and 43b, respectively, are switched on or off. switch control signal for off) is included.

In contrast to the sustain current dispersing device of the PDP according to the embodiment of the present invention and the conventional driving device of the PDP, the conventional PDP driving device has the same phase of the timing control signal for each electrode indicating the start point of the sustain pulse. In contrast, in the PDP sustain current dispersing apparatus according to the present invention, the phase of the timing control signals Cscan1 and Cscan2 indicating the start point of the sustain pulse is out of phase by a predetermined time difference? T at the odd or even electrodes.

Therefore, in the PDP according to the present invention, as shown in FIG. 6, the discharge current i generated during the sustain discharge is dispersed on the time axis by the phase difference of the sustain pulse, and the size thereof is smaller than that of the conventional art. As a result, as the discharge current i becomes smaller, EMI is reduced, as well as the influence on the line load is reduced, and the voltage drop of the sustain voltage is minimized. In addition, since the voltage drop of the sustain voltage is minimized, the sustain discharge is strongly generated and the luminance is increased, and the sustain voltage margin is increased.

The method and apparatus for dispersing the sustain current of the PDP according to the present invention distributes the discharge current by dividing the discharge current into two parts, even and odd, on each of the scan electrode Y and the sustain electrode Z, but the scan electrode Y and the sustain are distributed. Each of the electrodes Z may be divided into K-th (where K is a positive integer), K + 1-th, and K + 2-th electrodes to disperse the sustain discharge and discharge current three times or more times.

7 schematically shows a sustain current dispersing device of a PDP according to a second embodiment of the present invention.

Referring to FIG. 7, the sustain current spreader of the PDP according to the second embodiment of the present invention includes a scan driver 72 for driving the scan electrodes Y1 to Yn of the PDP 40, and a scan driver 72. ) And the retarders 74a to 74d connected between the scan electrodes Y1 to Yn of the PDP 40 and the sustain driver 73 for driving the sustain electrodes Z1 to Zn of the PDP 40. ), The retarders 75a to 75d connected between the sustain driver 73 and the sustain electrodes Z1 to Zn of the PDP 40, and the respective drive units 72 and 73 and the retarders 74a to 74d. And a timing controller 76 for controlling 75a to 75d.

The address electrodes X1 to Xm of the PDP 40 are driven by the address driver 41.

The address driver 71 performs inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like, and then stores the data data mapped to each subfield by the subfield mapping circuit to the address electrodes X1. To Xm) at the same time.

The scan driver 72 includes a plurality of scan drive integrated circuits (hereinafter, referred to as "D-ICs") 72a to 72d. Each D-IC 72a to 72d is connected to K scan electrodes, respectively. The scan driver 72 supplies the ramp ramps Ramp-down to the scan electrodes Y1 to Yn at the same time after the ramp ramps are supplied during the initialization period. Subsequently, the scan driver 72 sequentially selects a scan line by supplying scan pulses SCAN to the scan electrodes Y1 to Yn, and then radix scan electrodes Y1, Y3 ... Yn-1 during the sustain period. At the same time, sustain pulse is supplied.

The Y-side sustain delayers 74a to 74d connected between the scan driver 72 and the scan electrodes Y1 to Yn are connected to the scan electrodes Y1 to Yn from the scan driver 72 during the initialization period and the address period. While passing the drive signals supplied to the circuit, the sustain pulses supplied in the sustain period under the control of the timing controller 76 are delayed for each of the D-ICs 72a to 72d. The delay values of the Y-side sustain delayers 74a to 74d are determined as follows. The delay value of the second Y-side sustain delayer 74b is set larger than the delay value of the first Y-side sustain delayer 74a. The delay value of the third Y-side sustain delayer 74c is set larger than the delay value of the second Y-side sustain delayer 74b, and the delay value of the fourth Y-side sustain delayer 74d is the third Y. It is set larger than the delay value of the side sustain delay device 74c.

The sustain driver 73 supplies the positive DC voltage to the sustain electrodes Z1 to Zn during the initialization period and the address period, and then alternates with the scan driver 72 during the sustain period to supply the sustain pulses Z1 to Zn. ) Will be supplied.

The Z-side sustain delayers 75a to 75d connected between the sustain driver 73 and the sustain electrodes Z1 to Zn are sustained from the sustain driver 73 during the initialization period and the address period. While passing the drive signals supplied to the same, the sustain pulses supplied in the sustain period are delayed under the control of the timing controller 76. The delay values of the Z side sustain delay units 75a to 75d are determined as follows. The delay value of the second Z-side sustain delayer 75b is set larger than the delay value of the first Z-side sustain delayer 75a, and becomes the same as the delay value of the second Y-side sustain delayer 74b. . The delay value of the third Z-side sustain delayer 75c is set larger than the delay value of the second Z-side sustain delayer 75b, and is equal to the delay value of the third Y-side sustain delayer 74c. . The delay value of the fourth Z-side sustain delayer 75d is set to be larger than the delay value of the third Z-side sustain delayer 75c, and is equal to the delay value of the fourth Y-side sustain delayer 74d. .

Each of the address driver 71, the scan driver 72, and the sustain driver 73 may include an energy recovery circuit.

The timing controller 76 receives the vertical / horizontal synchronization signals H and V to generate timing control signals CAdd, Cscan, and Csus necessary for the driving units 71, 72, and 73, and the timing control signals ( CAdd, Cscan, and Csus are supplied to the corresponding driving units 71, 72, and 73. The control signal CAdd supplied to the address driver 71 includes a sampling clock of the shift register, a latch / output signal of a latch, and the like. The control signals Cscan and Csus supplied to each of the scan driver 72 and the sustain driver 73 include a switch control signal for turning on / off the switch element. In addition, the timing controller 76 supplies the control signals Cdelay1 and Cdelay2 indicating the sustain period to the sustain delayers 74a to 74d and 75a to 75d to sustain sustainers 74a to 74d and 75a to 75d. To control.

The sustain delayers 74a to 74d and 75a to 75d are composed of RLC combinations to delay the sustain pulse by a predetermined time. 8 shows an example of the sustain delayers 74a to 74d and 75a to 75d.

Referring to FIG. 8, each of the retarders 74a to 74d and 75a to 75d is a switch SW connected between the scan driver 72 or the sustain driver 73 and the scan electrode Y or the sustain electrode Z. And a RC delay circuit 81 and a diode D connected between one output terminal of the switch SW and the scan electrode Y or the sustain electrode Z.

The switch SW is the scan driver 72 or the sustain driver 73 and the scan electrode Y or the sustain electrode Z during the initialization period and the address period in response to the control signals Cdelay1 and Cdelay2 from the timing controller 76. ), While the scan driver 72 or the sustain driver 73 is connected to the RC delay circuit 81 during the sustain period. That is, the switch SW supplies the driving voltages generated from the scan driver 72 or the sustain driver 73 to the scan electrode Y or the sustain electrode Z as they are during the initialization period and the address period, and during the sustain period. The scan voltage is supplied to the RC delay circuit 81 to delay the sustain voltage supplied from the scan driver 72 or the sustain driver 73.

The RC delay circuit 81 serves to delay the sustain voltage supplied during the sustain period by a predetermined RC time constant to supply the scan electrode Y or the sustain electrode Z. The delay value of this RC delay circuit 81 can be adjusted by adjusting the resistance value R or the capacitance value C. FIG. Therefore, the delay value of each of the delayers 74a to 74d and 75a to 75d is selected as the resistance value R or the capacitance value C. The resistor R and the capacitor C may both be made of variable elements.

The diode D is the scan electrode Y or the sustain electrode Y when the scan electrode Y or the sustain electrode Z is directly connected to the scan driver 72 or the sustain driver 73 during the initialization period or the address period. ) To block the reverse current flowing toward the RC delay circuit 81.

The sustain current dispersing apparatus of the PDP according to the second embodiment of the present invention includes a scan electrode group Y1 to YK, YK + 1 to Y2K, Y2K + 1 to Y3K, as shown in FIG. Discharge current i is dispersed in units of Y3K + 1 to Yn or sustain groups (Z1 to ZK, ZK + 1 to Z2K, Z2K + 1 to Z3K, Z3K + 1 to Zn), and the magnitude of the discharge current (i) Is smaller than the conventional one.

As described above, the method and apparatus for dispersing the sustain current of the PDP according to the present invention can stabilize the sustain operation and reduce electromagnetic interference (EMI) by distributing the current during the sustain discharge. Furthermore, according to the method and apparatus for dispersing the sustain current of the PDP according to the present invention, since the discharge current generated during the sustain discharge is dispersed by the phase difference of the sustain pulse, the size of the sustain current is reduced, and thus, the EMI is reduced and the influence on the line load is reduced. The voltage drop of sustain voltage is minimized. When the voltage drop of the sustain voltage is minimized, the sustain discharge occurs strongly, resulting in high luminance and a sustain voltage margin.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A method for driving a plasma display panel having an electrode group for causing sustain discharge, Supplying a first sustain pulse to a first electrode included in the electrode group to cause discharge; Supplying a second sustain pulse to a second electrode included in the electrode group and opposed to the first electrode to cause a discharge; Delaying the first and second sustain pulses; Supplying the delayed first sustain pulse to a third electrode included in the electrode group to cause discharge; And discharging the delayed second sustain pulses to a fourth electrode included in the electrode group and opposed to the third electrodes. The method of claim 1, And generating a control signal indicative of a time point at which the sustain pulses are generated. The method of claim 1, And sustaining the sustain pulses in response to the control signal. The method of claim 1, The sustain current dispersion method of the plasma display panel, characterized in that for delaying the sustain pulses using a delay element. An apparatus for driving a plasma display panel having an electrode group for causing sustain discharge, A first driving unit supplying a first sustain pulse to a first electrode included in the electrode group to cause a discharge; A second driving part included in the electrode group and supplying a second sustain pulse to a second electrode facing the first electrode to cause discharge; A delay unit for delaying the first and second sustain pulses; A third driver configured to supply the delayed first sustain pulse to a third electrode included in the electrode group to cause discharge; And a fourth driving unit including the delayed second sustain pulse in the electrode group and generating a discharge to a fourth electrode facing the third electrode. The method of claim 5, And the retarder generates a control signal indicative of the time when the sustain pulse is generated and supplies the control signal to each of the driving units to control the time when the sustain pulse is generated. The method of claim 5, And the retarder delays the sustain pulses by using a delay element. The method of claim 5, The delay unit includes a timing controller for generating a control signal indicating a period during which the sustain pulse is supplied; A delay unit connected between the driving units and the electrodes to delay the sustain pulse having only a predetermined delay value; And a switch element for switching a current path between the driving units and the retarder in response to the control signal. The method of claim 8, And the retarder delays the sustain pulse by an RC time constant determined by a combination of a resistor and a capacitor.