KR20030066919A - Structure and method for manufacturing solder bump of flip chip package - Google Patents
Structure and method for manufacturing solder bump of flip chip package Download PDFInfo
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- KR20030066919A KR20030066919A KR1020020006670A KR20020006670A KR20030066919A KR 20030066919 A KR20030066919 A KR 20030066919A KR 1020020006670 A KR1020020006670 A KR 1020020006670A KR 20020006670 A KR20020006670 A KR 20020006670A KR 20030066919 A KR20030066919 A KR 20030066919A
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- layer
- solder bump
- pad
- alloy layer
- metal
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- 229910000679 solder Inorganic materials 0.000 title claims abstract description 81
- 238000000034 method Methods 0.000 title claims description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000002184 metal Substances 0.000 claims abstract description 85
- 229910052751 metal Inorganic materials 0.000 claims abstract description 85
- 229910018054 Ni-Cu Inorganic materials 0.000 claims abstract description 76
- 229910018481 Ni—Cu Inorganic materials 0.000 claims abstract description 76
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 76
- 239000000956 alloy Substances 0.000 claims abstract description 76
- 239000004065 semiconductor Substances 0.000 claims abstract description 41
- 238000002161 passivation Methods 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 184
- 239000012790 adhesive layer Substances 0.000 claims description 42
- 230000003064 anti-oxidating effect Effects 0.000 claims description 37
- 229920006254 polymer film Polymers 0.000 claims description 29
- 230000001681 protective effect Effects 0.000 claims description 11
- 238000004544 sputter deposition Methods 0.000 claims description 11
- 238000007772 electroless plating Methods 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 8
- 238000007740 vapor deposition Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 229910052804 chromium Inorganic materials 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 4
- 229920000642 polymer Polymers 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims 1
- 229910052802 copper Inorganic materials 0.000 abstract description 9
- 229910052759 nickel Inorganic materials 0.000 abstract description 6
- 230000009257 reactivity Effects 0.000 abstract description 2
- 238000001465 metallisation Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 229910000765 intermetallic Inorganic materials 0.000 description 15
- 238000006243 chemical reaction Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 230000005496 eutectics Effects 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 3
- 229910018104 Ni-P Inorganic materials 0.000 description 2
- 229910018536 Ni—P Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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Abstract
Description
본 발명은 반도체 플립칩 패키지 기술에 관한 것으로서, 특히 고융점 납 솔더(High lead solder), 공융 솔더(Eutectic solder) 및 무연솔더(Pb-free solder)를 위한 반도체 플립칩 패키지를 위한 솔더 범프 구조 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor flip chip package technology, and more particularly to solder bump structures for semiconductor flip chip packages for high lead solder, eutectic solder, and lead-free solder. The manufacturing method is related.
반도체 소자의 고속화, 고집적화에 따라 소자의 크기가 미세화되고 I/O 수가 증가하고 있다. 이에 따라 기존의 플라스틱 패키지로는 다수의 외부 리드들을 형성하는데 제약이 있어 패키지 구조가 핀 삽입형에서 표면실장형으로 급격히 변화되어 회로 기판에 대한 실장밀도를 높여왔다.As the speed of semiconductor devices increases, the size of devices becomes smaller and the number of I / Os increases. Accordingly, the conventional plastic package has a limitation in forming a plurality of external leads, so the package structure is rapidly changed from a pin insertion type to a surface mount type, thereby increasing the mounting density of the circuit board.
이러한 요구에 따라 최근 반도체 칩을 최소한의 공간상에 패키징하는 볼 그리드 어레이(Ball Grid Array) 패키지, 칩 스케일 패키지(Chip Scale Package) 등이 등장하게 되었으며, 이러한 패키지는 와이어 본딩(Wire Bonding), 탭(TAB; Tape Automated Bonding) 및 플립 칩 본딩(Flip Chip Bonding) 등의 다양한 전기적 접속 방법으로 실장된다. 이들 전기적 접속 방법 중에서 고속, 고기능, 고밀도 실장에 가장 효과적인 방법은 플립 칩 본딩이며, 플립 칩 본딩 공정에는 접속의 매개체로서 반도체 칩의 또는 반도체 칩 패드 상에 솔더 범프(Solder Bump)가 필요하다.In response to these demands, ball grid array packages and chip scale packages, which package semiconductor chips in a minimal space, have recently emerged. Such packages include wire bonding and tabs. (TAB; Tape Automated Bonding) and Flip Chip Bonding (Flip Chip Bonding). Among these electrical connection methods, the most effective method for high speed, high function, and high density mounting is flip chip bonding. A flip chip bonding process requires solder bumps on a semiconductor chip or on a semiconductor chip pad as a connection medium.
그런데, 종래 플립칩 본딩 기술에서는 솔더 범프 아래 금속층(Under Bump Metallization : 이하 UBM이라 칭함)을 형성하고 있다. 이러한 UMB층은 솔더가 잘 접착할 수 있도록 솔더 웨팅층(wetting layer)을 제공해야 하며, 솔더 성분이 반도체 칩 내부로 침투하지 못하도록 막아주는 확산 방지의 역할을 해야한다. 또한 솔더가 열처리 과정에서도 패드와 잘 접착될 수 있도록 패드와 접착성을 제공해야 하며 외부로부터 패드를 보호하는 역할을 해야한다.However, in the conventional flip chip bonding technology, a metal layer (hereinafter referred to as UBM) is formed under a solder bump. The UMB layer should provide a solder wetting layer to allow the solder to adhere well and act as a diffusion barrier to prevent the solder component from penetrating into the semiconductor chip. In addition, the pads must provide adhesion with the pads so that the solder can bond well to the pads during the heat treatment process, and must protect the pads from the outside.
하지만, 전자제품의 소형화에 따라 패키지의 크기에 대한 관심이 고조되어 미세 피치의 솔더 범프를 형성하면서 패키지 신뢰성에 대한 문제가 발생하였다. 즉, 패키지 크기가 점차 칩(chip) 크기로 감소함에 따라 솔더 범프의 크기나 UBM층 의 두께가 감소하여 UBM층과 솔더 범프의 반응으로 성장하는 금속간 화합물로 인해 패키지의 신뢰성이 감소하게 되었다.However, with the miniaturization of electronic products, interest in the size of packages has increased, forming solder bumps with fine pitch, causing problems with package reliability. That is, as the package size gradually decreases to the chip size, the solder bump size or the thickness of the UBM layer decreases, thereby reducing the reliability of the package due to the intermetallic compound grown by the reaction between the UBM layer and the solder bump.
이러한 문제를 해결하기 위하여 종래에는 무전해 도금법으로 패드층 표면을 Ni-P로 도금하여 UBM층을 형성함으로써 금속간 화합물의 성장 속도를 늦추고 패키지의 신뢰성을 향상시킬 수 있다는 결과를 보였다.In order to solve this problem, conventionally, the surface of the pad layer was formed with Ni-P by electroless plating to form a UBM layer, which showed that the growth rate of the intermetallic compound may be slowed and the reliability of the package may be improved.
그러나, 무전해 Ni-P 도금은 도금층의 내부 응력을 높여 반도체 칩을 깨뜨리는 문제를 야기시켰다. 이외에도 스퍼터링 방법 또는 전해 도금법으로 형성시킨 Ni, NiV 이나 Cu층 등이 고려되고 있으나, 이는 고융점 납 솔더(High Lead solder) 또는 공융 솔더(Eutectic solder)에서 상용화해서 사용하고 있지만, 무연 솔더(Pb-free solder)의 경우 주석의 높은 반응으로 인하여 UBM층과 반응하여 금속간 화합물 생성이 급격히 발생함으로 적합하지 않다.However, electroless Ni-P plating caused a problem of breaking the semiconductor chip by increasing the internal stress of the plating layer. In addition, although Ni, NiV, or Cu layers formed by sputtering or electroplating are considered, they are commercially used in high lead solder or eutectic solder, but lead-free solder (Pb- In the case of free solder, it is not suitable to react with the UBM layer due to the high reaction of tin, so that the formation of intermetallic compound occurs rapidly.
더욱이 종래 기술에서는 솔더의 재료인 주석(Sn)의 조성이 증가할수록 금속간 화합물의 두께가 증가되기 때문에 패키지 신뢰성이 저하되는 문제가 있었다.Furthermore, in the related art, as the composition of tin (Sn), which is a solder material, increases, the thickness of the intermetallic compound increases, which causes a problem of deteriorating package reliability.
본 발명의 목적은 이와 같은 종래 기술의 문제점을 해결하기 위하여 솔더 범프 하부의 UBM 구조층에 Ni와 Cu를 포함한 Ni-Cu 합금층(alloy layer)을 추가 형성함으로써 고융점 솔더, 공융 솔더 및 무연 솔더용 UBM으로 사용할 수 있고 Ni-Cu 합금층과 솔더 사이의 반응으로 성장하는 금속간 화합물을 Cu 조성에 따라 성장 속도를 조정하여 그 두께가 얇아져 패키지의 신뢰성을 향상시킬 수 있는 반도체 플립칩 패키지를 위한 솔더 범프 구조 및 그 제조 방법을 제공하는데 있다.An object of the present invention is to solve the problems of the prior art by adding a Ni-Cu alloy layer containing Ni and Cu in the UBM structure layer under the solder bumps, high melting point solder, eutectic solder and lead-free solder For semiconductor flip chip package, which can be used as UBM for the semiconductor, and the intermetallic compound that grows by reaction between Ni-Cu alloy layer and solder can be grown by adjusting the growth rate according to Cu composition to improve the reliability of the package. The present invention provides a solder bump structure and a method of manufacturing the same.
상기 목적을 달성하기 위하여 본 발명은 솔더 범프를 이용한 플립칩 패키지 구조에 있어서, 반도체 칩상에 패드가 노출되는 개구부를 갖는 보호막과, 보호막의 개구부를 통해 패드와 접착된 금속 접착층과 Ni-Cu 합금층 및 산화방지 금속층이 순차 적층된 UBM 구조층과, UBM 구조층에 본딩된 솔더 범프를 구비한다.In order to achieve the above object, the present invention provides a flip chip package structure using solder bumps, the protective film having an opening through which a pad is exposed on a semiconductor chip, a metal adhesive layer and a Ni-Cu alloy layer bonded to the pad through the opening of the protective film. And a UBM structure layer in which anti-oxidation metal layers are sequentially stacked, and solder bumps bonded to the UBM structure layer.
상기 목적을 달성하기 위하여 본 발명은 반도체 칩의 패드 상부에 UBM층 및 솔더 범프를 형성하는 제조 방법에 있어서, 반도체 칩 상부에 패드가 노출된 개구부를 갖는 보호막을 형성하는 단계와, 보호막의 개구부를 통해 패드와 접착된 금속 접착층과 Ni-Cu 합금층 및 산화방지 금속층이 순차 적층된 UBM 구조층을 형성하는 단계와, UBM 구조층에 솔더 범프를 본딩하는 단계를 포함한다.In order to achieve the above object, the present invention provides a manufacturing method for forming a UBM layer and solder bumps on the pad of the semiconductor chip, forming a protective film having an opening exposed by the pad on the semiconductor chip, and the opening of the protective film Forming a UBM structure layer in which a metal adhesive layer, a Ni—Cu alloy layer, and an anti-oxidation metal layer, which are bonded to the pad through the pad, are sequentially stacked; and bonding solder bumps to the UBM structure layer.
도 1은 본 발명에 따른 반도체 플립칩 패키지를 위한 Ni-Cu 합금층을 이용한 UBM 구조층 및 솔더 범프 구조를 나타낸 도면,1 is a view showing a UBM structure layer and a solder bump structure using a Ni-Cu alloy layer for a semiconductor flip chip package according to the present invention,
도 2a 내지 2g는 본 발명의 일 실시예에 따른 반도체 플립칩 패키지를 위한 Ni-Cu 합금층을 이용한 UBM 및 솔더 범프의 제조 방법을 순차적으로 나타낸 공정 순서도,2A to 2G are flowcharts sequentially illustrating a method of manufacturing UBM and solder bumps using a Ni—Cu alloy layer for a semiconductor flip chip package according to an embodiment of the present invention;
도 3a 내지 도 3g는 본 발명의 다른 실시예에 따른 반도체 플립칩 패키지를 위한 Ni-Cu 합금층을 이용한 UBM 및 솔더 범프의 제조 방법을 순차적으로 나타낸 공정 순서도.3A to 3G are flowcharts sequentially illustrating a method of manufacturing UBM and solder bumps using a Ni—Cu alloy layer for a semiconductor flip chip package according to another embodiment of the present invention.
＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
10 : 반도체 칩 12 : 패드10 semiconductor chip 12 pad
14 : 보호막 16, 21 : 감광성 고분자막 패턴14: protective film 16, 21: photosensitive polymer film pattern
18 : 금속 접착층 20 : Ni-Cu 합금층18 metal bonding layer 20 Ni-Cu alloy layer
22 : 산화방지 금속층 23 : UBM 구조층22: anti-oxidation metal layer 23: UBM structure layer
24 : 솔더 범프24: solder bump
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 1은 본 발명에 따른 반도체 플립칩 패키지를 위한 Ni-Cu 합금층을 이용한 UBM 구조층 및 솔더 범프 구조를 나타낸 도면이다.1 is a view showing a UBM structure layer and a solder bump structure using a Ni-Cu alloy layer for a semiconductor flip chip package according to the present invention.
도 1을 참조하면, 본 발명의 솔더 범프 구조는 반도체 칩(10) 상에 형성된 패드(12)와, 패드(12)가 노출되도록 개구부를 갖고 반도체 칩(10) 상부에 형성된 보호막(14)과, 보호막(14)의 개구부를 통해 패드(12)와 접착된 금속 접착층(18)과 Ni-Cu 합금층(20) 및 산화방지 금속층(22)이 순차 적층된 UBM 구조층(23)과, UBM 구조층(23)에 본딩된 솔더 범프(24)로 이루어진다.Referring to FIG. 1, the solder bump structure of the present invention may include a pad 12 formed on the semiconductor chip 10, a protective film 14 formed on the semiconductor chip 10 and having an opening to expose the pad 12. The UBM structure layer 23 in which the metal adhesive layer 18, the Ni-Cu alloy layer 20, and the anti-oxidation metal layer 22, which are bonded to the pad 12 through the opening of the protective film 14, is sequentially stacked, and the UBM It consists of a solder bump 24 bonded to the structural layer 23.
여기서, UBM 구조층(23)의 금속 접착층(18)은 Ti, Cr, 또는 TiW으로 이루어지고 그 두께는 0.5∼10㎛이다. 그리고 Ni-Cu 합금층(20)은 Ni 및 Cu로 이루어지고 그 두께는 0.5∼10㎛이다. 이때, Ni-Cu 합금층(20)에서 Cu의 함량 조성을 1∼40 at%에서 조정하여 Ni-Cu 합금층(20)과 솔더 범프 사이에 성장되는 금속간 화합물의 성장 속도를 제어할 수 있다. 또한 산화방지 금속층(22)은 Au, Pt, Pd 또는 Cu로 이루어지고 그 두께는 0.5∼2㎛이다.Here, the metal adhesive layer 18 of the UBM structure layer 23 is made of Ti, Cr, or TiW, and its thickness is 0.5 to 10 mu m. And Ni-Cu alloy layer 20 is made of Ni and Cu and the thickness is 0.5 to 10㎛. In this case, the growth rate of the intermetallic compound grown between the Ni—Cu alloy layer 20 and the solder bumps may be controlled by adjusting the content of Cu in the Ni—Cu alloy layer 20 at 1 to 40 at%. The anti-oxidation metal layer 22 is made of Au, Pt, Pd or Cu, and has a thickness of 0.5 to 2 m.
그러므로, 본 발명에 따른 플립칩용 솔더범프 구조에 있어서, 솔더 범프(24) 하부의 UBM 구조층(23)에 주석(Sn)을 주로 함유한 솔더와의 반응성이 높은 Ni와 Cu를 포함한 Ni-Cu 합금층(20)을 추가 형성함으로써 UBM 구조층과 솔더 사이의 접착력을 향상시키고, 금속간 화합물의 성장을 억제하여 솔더 조인트부의 신뢰성을 향상시킨다.Therefore, in the solder bump structure for flip chip according to the present invention, Ni-Cu containing Ni and Cu having high reactivity with solder mainly containing tin (Sn) in the UBM structure layer 23 under the solder bump 24. By further forming the alloy layer 20, the adhesion between the UBM structure layer and the solder is improved, and the growth of the intermetallic compound is suppressed to improve the reliability of the solder joint.
도 2a 내지 2g는 본 발명의 일 실시예에 따른 반도체 플립칩 패키지의 본딩 제조 방법을 순차적으로 나타낸 공정 순서도로서, 이를 참조하면 본 발명의 일 실시예는 제조 공정은 다음과 같다. 본 실시예에서는 리프트 오프(lift-off) 방식을 적용하기로 한다.2A through 2G are flowcharts sequentially illustrating a method of manufacturing a bonding method of a semiconductor flip chip package according to an embodiment of the present invention. Referring to this, an embodiment of the present invention is a manufacturing process as follows. In this embodiment, a lift-off method is applied.
도 2a는 통상적으로 알려진 반도체 제조 공정을 이용하여 제조된 반도체 웨이퍼 칩(10) 상부 전면에 보호막(14)을 형성한 후, 칩의 패드(12)가 노출되도록 보호막(14)을 패터닝하여 개구부(15)를 형성한 모습을 나타낸 것이다.FIG. 2A illustrates a passivation layer 14 formed on a top surface of a semiconductor wafer chip 10 manufactured using a conventionally known semiconductor manufacturing process, and then patterning the passivation layer 14 to expose the pad 12 of the chip. 15) is formed.
다음 도 2b 내지 도 2f를 참조해서 보호막(14)의 개구부(15)를 통해 패드(12)와 접착된 본 발명의 일 실시예에 따라 UBM 구조층을 형성한다.Next, referring to FIGS. 2B through 2F, a UBM structure layer is formed according to an exemplary embodiment of the present invention, which is bonded to the pad 12 through the opening 15 of the passivation layer 14.
도 2b에 도시된 바와 같이, 상기 결과물 전면에 UBM 구조층 영역을 정의하고자 감광성 고분자막을 형성하고 이를 패터닝해서 보호막(14) 상부에 패드(12)가 노출되는 감광성 고분자막 패턴(16)을 형성한다.As shown in FIG. 2B, a photosensitive polymer film is formed on the entire surface of the resultant to define a UBM structure layer region, and is patterned to form a photosensitive polymer film pattern 16 on which the pad 12 is exposed on the passivation layer 14.
그리고 도 2c 및 도 2d에 도시된 바와 같이, 감광성 고분자막 패턴(16)이 있는 결과물에 금속 접착층(18)과 Ni-Cu 합금층(20)을 순차 적층한다. 이때 금속 접착층(18)은 Ti, Cr, 또는 TiW으로 이루어지고 그 두께는 0.5∼10㎛로 하는데, 스퍼터링 또는 증기법으로 증착한다. 그리고 Ni-Cu 합금층(20)의 두께는 0.5∼10㎛로 한다. 이때, Ni-Cu 합금층(20)에서 Cu의 함량 조성을 1∼40 at%에서 조정하여 Ni-Cu 합금층(20)과 솔더 범프 사이에 성장되는 금속간 화합물의 성장 속도를 제어할 수 있다. 역시 Ni-Cu 합금층(20)은 스퍼터링 또는 증기법으로 증착하고, 증착 중에 발생되는 응력을 감소시기 위하여 증착 중에 반도체 칩(10)을 수냉시키도록 하는 것이 바람직하다.2C and 2D, the metal adhesive layer 18 and the Ni—Cu alloy layer 20 are sequentially stacked on the resultant product having the photosensitive polymer film pattern 16. At this time, the metal adhesive layer 18 is made of Ti, Cr, or TiW and the thickness thereof is 0.5 to 10 탆, and is deposited by sputtering or vapor deposition. And the thickness of the Ni-Cu alloy layer 20 shall be 0.5-10 micrometers. In this case, the growth rate of the intermetallic compound grown between the Ni—Cu alloy layer 20 and the solder bumps may be controlled by adjusting the content of Cu in the Ni—Cu alloy layer 20 at 1 to 40 at%. Ni-Cu alloy layer 20 is also preferably deposited by sputtering or vapor deposition, and it is preferable to cool the semiconductor chip 10 during deposition in order to reduce stress generated during deposition.
이어서 도 2e에 도시된 바와 같이, 감광성 고분자막 패턴(16)과 그 상부의 금속 접착층(18)과 Ni-Cu 합금층(20)을 선택적으로 제거한다. 그래서 패드(12) 상부에만 금속 접착층(18)과 Ni-Cu 합금층(20)이 남도록 한다.Subsequently, as shown in FIG. 2E, the photosensitive polymer film pattern 16, the metal adhesive layer 18, and the Ni—Cu alloy layer 20 thereon are selectively removed. Therefore, the metal adhesive layer 18 and the Ni—Cu alloy layer 20 remain only on the pad 12.
그런 다음 도 2f에 도시된 바와 같이, Ni-Cu 합금층(20) 상부에 산화방지 금속층(22)을 무전해 도금으로 형성함으로써 패드(12)에 접착된 금속 접착층(18)과 Ni-Cu 합금층(20) 및 산화방지 금속층(22)이 순차 적층된 UBM 구조층(23)이 형성된다. 이때 산화방지 금속층(22)은 Au, Pt, Pd 또는 Cu로 이루어지며 0.5∼2㎛ 두께로 한다. 그리고 산화방지 금속층(22)은 스퍼터링, 증기법 등을 이용하여 증착한다.Then, as shown in FIG. 2F, the Ni-Cu alloy and the metal adhesive layer 18 bonded to the pad 12 are formed by electroless plating on the Ni-Cu alloy layer 20 by electroless plating. The UBM structure layer 23 in which the layer 20 and the anti-oxidation metal layer 22 are sequentially stacked is formed. At this time, the anti-oxidation metal layer 22 is made of Au, Pt, Pd or Cu and has a thickness of 0.5 to 2㎛. The anti-oxidation metal layer 22 is deposited by sputtering, vapor deposition, or the like.
그리고나서 도 2g에 도시된 바와 같이, 본 발명의 UBM 구조층(23)에 전해도금법, 스크린 프린트 방법, 볼 플레이스먼트(ball placement) 방법 등을 사용하여 솔더 범프(24)를 형성한다.Then, as shown in FIG. 2G, the solder bumps 24 are formed in the UBM structure layer 23 of the present invention using an electroplating method, a screen printing method, a ball placement method, or the like.
본 발명의 일 실시예에 있어서는, 상기 제조 공정대신에 다음과 같이 진행할 수 있다. 도 2d와 동일하게 공정을 진행하여 보호막(14) 상부에 패드가 노출되는 감광성 고분자막 패턴(16)과, 감광성 고분자막 패턴(16)이 있는 결과물에 금속 접착층(18)과 Ni-Cu 합금층(20)을 적층하고 그 위에 스퍼터링 방법 또는 증기법을 이용하여 산화방지 금속층(22)을 형성한다. 그리고 감광성 고분자막 패턴(16)과 그 상부의 금속 접착층(18)과 Ni-Cu 합금층(20) 및 산화방지 금속층(22)을 선택적으로 제거해서 패드(12) 상부에만 금속 접착층(18)과 Ni-Cu 합금층(20) 및 산화방지 금속층(22)이 남도록 하여 UBM 구조층(23)을 형성한다. 그리고 나서 도 2g에 도시된 바와 같이, 본 발명의 UBM 구조층(23)에 솔더 범프(24)를 형성한다.In one embodiment of the present invention, instead of the manufacturing process can proceed as follows. 2D, the metal adhesive layer 18 and the Ni—Cu alloy layer 20 are formed on the resulting photosensitive polymer film pattern 16 and the photosensitive polymer film pattern 16 having the pads exposed on the passivation layer 14. ) Is laminated and the anti-oxidation metal layer 22 is formed thereon using a sputtering method or a vapor method. The photosensitive polymer film pattern 16, the metal adhesive layer 18, the Ni-Cu alloy layer 20, and the anti-oxidation metal layer 22 are selectively removed, and the metal adhesive layer 18 and Ni are disposed only on the pad 12. The UBM structure layer 23 is formed with the Cu alloy layer 20 and the anti-oxidation metal layer 22 remaining. Then, as shown in FIG. 2G, solder bumps 24 are formed in the UBM structure layer 23 of the present invention.
그러므로, 본 발명의 일 실시예는 감광성 고분자막 패턴(16)을 이용한 리프트 오프 방식을 채택하여 감광성 고분자막 패턴(16)과 금속 접착층(18) 및 Ni-Cu합금층(20)을 형성한 후에 감광성 고분자막 패턴(16)을 제거해서 패드(12)에 연결된 UBM 구조층(23)의 금속 접착층(18)과 Ni-Cu 합금층(20)을 형성하고 무전해 도금방법을 이용하여 산화방지 금속층(22)을 형성하거나 감광성 고분자막 패턴(16)과 금속 접착층(18)과 Ni-Cu 합금층(20) 및 산화방지 금속막(22)을 순차 형성한 후에 감광성 고분자막 패턴(16)을 제거해서 패드(12)에 연결된 UBM 구조층(23)의 금속 접착층(18)과 Ni-Cu 합금층(20) 및 산화방지 금속층(22)을 형성함으로써 UBM 구조층(23)의 Ni-Cu 합금층(20)을 통해 솔더의 접착력이 향상되면서 금속간 화합물의 성장이 억제되어 솔더 조인트부의 신뢰성을 높일 수 있다. 이와 더불어, Ni-Cu 합금층(20)과 솔더 사이의 반응으로 성장하는 금속간 화합물을 Ni-Cu 합금층(20)내 Cu 조성 비율에 따라 성장 속도를 조정하여 그 두께를 얇게 할 수 있다.Therefore, an embodiment of the present invention adopts a lift-off method using the photosensitive polymer film pattern 16 to form the photosensitive polymer film pattern 16, the metal adhesive layer 18, and the Ni—Cu alloy layer 20, and then the photosensitive polymer film 20. The pattern 16 is removed to form the metal adhesive layer 18 and the Ni-Cu alloy layer 20 of the UBM structure layer 23 connected to the pad 12, and the anti-oxidation metal layer 22 using the electroless plating method. Or the photosensitive polymer film pattern 16, the metal adhesive layer 18, the Ni-Cu alloy layer 20, and the anti-oxidation metal film 22 are sequentially formed, and then the photosensitive polymer film pattern 16 is removed to form the pad 12. Through the Ni-Cu alloy layer 20 of the UBM structure layer 23 by forming the metal adhesive layer 18 and Ni-Cu alloy layer 20 and the anti-oxidation metal layer 22 of the UBM structure layer 23 connected to the As the adhesion of the solder is improved, the growth of the intermetallic compound is suppressed, thereby increasing the reliability of the solder joint. In addition, the thickness of the intermetallic compound grown by the reaction between the Ni—Cu alloy layer 20 and the solder may be reduced by adjusting the growth rate according to the Cu composition ratio in the Ni—Cu alloy layer 20.
도 3a 내지 도 3g는 본 발명의 다른 실시예에 따른 반도체 플립칩 패키지의 본딩 제조 방법을 순차적으로 나타낸 공정 순서도로서, 이를 참조하면 본 발명의 다른 실시예의 제조 공정은 다음과 같다.3A to 3G are flowcharts sequentially illustrating a bonding fabrication method of a semiconductor flip chip package according to another embodiment of the present invention. Referring to this, the fabrication process of another embodiment of the present invention is as follows.
도 3a는 기존에 알려진 반도체 공정을 이용하여 형성된 반도체 웨이퍼로, 기판(10) 상부 전면에 보호막(14)을 형성한 후, 패드(12)가 노출되도록 보호막(14)을 패터닝하여 개구부(15)를 형성한 모습이다.3A illustrates a semiconductor wafer formed by using a conventionally known semiconductor process. After the protective film 14 is formed on the entire upper surface of the substrate 10, the protective film 14 is patterned so that the pad 12 is exposed. Shaped to form.
다음 도 3b 내지 도 3f를 참조해서 보호막(14)의 개구부(15)를 통해 패드(12)와 접착된 본 발명의 다른 실시예에 따라 UBM 구조층을 형성한다.Next, referring to FIGS. 3B to 3F, a UBM structure layer is formed according to another exemplary embodiment of the present invention bonded to the pad 12 through the opening 15 of the passivation layer 14.
도 3b 및 도 3c에 도시된 바와 같이, 보호막(14) 및 패드(12) 전면에 금속 접착층(18)과 Ni-Cu 합금층(20)을 순차 적층한다. 이때 금속 접착층(18)은 Ti,Cr, 또는 TiW으로 이루어지고 그 두께는 0.5∼10㎛하는데, 스퍼터링 또는 증기법으로 증착한다. 그리고 Ni-Cu 합금층(20)은 Ni 및 Cu로 이루어지고 그 두께는 0.5∼10㎛이다. 이때, Ni-Cu 합금층(20)에서 Cu의 함량 조성을 1∼40 at%에서 조정하여 Ni-Cu 합금층(20)과 솔더 범프 사이에 성장되는 금속간 화합물의 성장 속도를 제어할 수 있다. 역시 Ni-Cu 합금층(20)은 스퍼터링 또는 증기법으로 증착하고, 증착 중에 발생되는 응력을 감소시기 위하여 증착 중에 반도체 칩(10)을 수냉시킨다.As shown in FIGS. 3B and 3C, the metal adhesive layer 18 and the Ni—Cu alloy layer 20 are sequentially stacked on the passivation layer 14 and the pad 12. At this time, the metal adhesive layer 18 is made of Ti, Cr, or TiW and the thickness thereof is 0.5 to 10 µm, and is deposited by sputtering or vapor deposition. And Ni-Cu alloy layer 20 is made of Ni and Cu and the thickness is 0.5 to 10㎛. In this case, the growth rate of the intermetallic compound grown between the Ni—Cu alloy layer 20 and the solder bumps may be controlled by adjusting the content of Cu in the Ni—Cu alloy layer 20 at 1 to 40 at%. The Ni—Cu alloy layer 20 is also deposited by sputtering or vapor deposition, and water-cools the semiconductor chip 10 during deposition to reduce the stress generated during deposition.
그리고 도 3d에 도시된 바와 같이, Ni-Cu 합금층(20) 상부에 UBM 구조층 영역을 정의하는 감광성 고분자막 패턴(21)을 형성한다.3D, the photosensitive polymer film pattern 21 defining the UBM structure layer region is formed on the Ni—Cu alloy layer 20.
도 3e에 도시된 바와 같이, 건식 식각 공정 또는 습식 식각 공정을 진행하여 감광성 고분자 패턴(21)에 맞추어 적층된 Ni-Cu 합금층(20) 및 금속 접착층(18)을 패터닝한 후에, 감광성 고분자 패턴(21)을 제거한다.As shown in FIG. 3E, after the dry etching process or the wet etching process is performed to pattern the Ni-Cu alloy layer 20 and the metal adhesive layer 18 laminated according to the photosensitive polymer pattern 21, the photosensitive polymer pattern is formed. Remove (21).
그 다음 도 3f에 도시된 바와 같이, Ni-Cu 합금층(20) 상부에 산화방지 금속층(22)을 무전해 도금함으로써 패드(12)에 접착된 금속 접착층(18)과 Ni-Cu 합금층(20) 및 산화방지 금속층(22)이 순차 적층된 UBM 구조층(23)이 형성된다. 이때 산화방지 금속층(22)은 Au, Pt, Pd 또는 Cu로 이루어지며 0.5∼2㎛ 두께로 한다.Then, as shown in FIG. 3F, the metal adhesion layer 18 and the Ni—Cu alloy layer bonded to the pad 12 by electroless plating an anti-oxidation metal layer 22 on the Ni—Cu alloy layer 20 ( 20) and the UBM structure layer 23 in which the anti-oxidation metal layer 22 is sequentially stacked is formed. At this time, the anti-oxidation metal layer 22 is made of Au, Pt, Pd or Cu and has a thickness of 0.5 to 2㎛.
그리고나서 도 3g에 도시된 바와 같이, 본 발명의 UBM 구조층(23)에 전해도금법, 스크린 프린트 방법, 볼 플레이스먼트 방법 등을 사용하여 솔더 범프(24)를 형성한다.Then, as shown in FIG. 3G, the solder bumps 24 are formed in the UBM structure layer 23 of the present invention by using an electroplating method, a screen printing method, a ball placement method, or the like.
한편, 본 발명의 다른 실시예에 있어서는, 상술한 제조 공정대신에 다음과 같이 UBM 구조층을 제조할 수도 있다. 우선 도 3c와 동일하게 공정을 진행하여 보호막(14) 및 패드(12) 전면에 금속 접착층(18)과 Ni-Cu 합금층(20)을 형성하고 스퍼터링, 증기법 등으로 산화방지 금속층(22)을 형성한다. 그리고 산화방지 금속층(22) 상부에 UBM 구조층 영역을 정의하는 감광성 고분자막 패턴(21)을 형성하고 식각 공정으로 감광성 고분자막 패턴(21)에 맞추어 적층된 산화방지 금속층(22)과 Ni-Cu 합금층(20) 및 금속 접착층(18)을 패터닝한 후에 감광성 고분자막 패턴(21)을 제거함으로써 UBM 구조층(23)을 형성한다.On the other hand, in another embodiment of the present invention, instead of the above-described manufacturing process, the UBM structure layer may be manufactured as follows. First, the process is performed in the same manner as in FIG. 3C to form the metal adhesive layer 18 and the Ni-Cu alloy layer 20 on the passivation layer 14 and the pad 12 in front, and the anti-oxidation metal layer 22 by sputtering or steam method. To form. An anti-oxidation metal layer 22 and a Ni-Cu alloy layer are formed on the anti-oxidation metal layer 22 to form a photosensitive polymer film pattern 21 defining a region of the UBM structure layer. The UBM structure layer 23 is formed by removing the photosensitive polymer film pattern 21 after patterning the 20 and the metal adhesive layer 18.
그러므로, 본 발명의 다른 실시예는 금속 접착층(18)과 Ni-Cu 합금층(20)을 증착하고 감광성 고분자막 패턴(21)을 이용하여 금속 접착층(18)과 Ni-Cu 합금층(20)을 식각한 후에 감광성 고분자막 패턴(21)을 제거하고 무전해 도금 방법으로 산화방지 금속층(22)을 형성하여 UBM 구조층(23)을 형성하거나, 금속 접착층(18)과 Ni-Cu 합금층(20) 및 산화방지 금속층(22)을 순차 증착하고 감광성 고분자막 패턴(21)을 이용하여 금속 접착층(18)과 Ni-Cu 합금층(20) 및 산화방지 금속층(22)을 식각해서 패드(12)에 연결된 UBM 구조층(23)을 형성함으로써 UBM 구조층(23)의 Ni-Cu 합금층(20)을 통해 솔더의 접착력이 향상되면서 금속간 화합물의 성장이 억제되어 솔더 조인트부의 신뢰성을 높일 수 있다. 이와 더불어, Ni-Cu 합금층(20)과 솔더 사이의 반응으로 성장하는 금속간 화합물을 Ni-Cu 합금층(20)내 Cu 조성 비율에 따라 성장 속도를 조정하여 그 두께를 얇게 할 수 있다.Therefore, another embodiment of the present invention deposits the metal adhesive layer 18 and the Ni-Cu alloy layer 20 and the metal adhesive layer 18 and the Ni-Cu alloy layer 20 by using the photosensitive polymer film pattern 21. After etching, the photosensitive polymer film pattern 21 is removed and an anti-oxidation metal layer 22 is formed by an electroless plating method to form the UBM structure layer 23, or the metal adhesive layer 18 and the Ni—Cu alloy layer 20. And sequentially depositing the anti-oxidation metal layer 22 and etching the metal adhesive layer 18, the Ni—Cu alloy layer 20, and the anti-oxidation metal layer 22 using the photosensitive polymer film pattern 21 to be connected to the pad 12. By forming the UBM structure layer 23, the adhesion of the solder is improved through the Ni—Cu alloy layer 20 of the UBM structure layer 23, and the growth of the intermetallic compound is suppressed, thereby increasing the reliability of the solder joint part. In addition, the thickness of the intermetallic compound grown by the reaction between the Ni—Cu alloy layer 20 and the solder may be reduced by adjusting the growth rate according to the Cu composition ratio in the Ni—Cu alloy layer 20.
이상 설명한 바와 같이, 본 발명은 UBM 구조층의 금속 접착층 상부에 솔더와 반응성이 높은 Ni과 Cu로 Ni-Cu 합금층을 추가 형성함으로써 솔더 범프와 패키지 사이의 접착력을 향상시킬 수 있다. 특히 무연 솔더의 경우 주석(Sn)의 함량이 높아서 UBM 구조층과 솔더 범프 사이에 금속간 화합물 두께가 증가하게 되는데, 본 발명을 적용할 경우 Ni-Cu 합금층의 Cu 조성을 조정하여 Ni-Cu 합금층과 솔더 범프 사이에 성장되는 금속간 화합물 성장 속도를 얇게 할 수 있다.As described above, the present invention can improve the adhesive force between the solder bump and the package by further forming a Ni-Cu alloy layer of Ni and Cu highly reactive with the solder on the metal adhesive layer of the UBM structure layer. Particularly, in the case of lead-free solders, the content of tin (Sn) is high to increase the intermetallic compound thickness between the UBM structure layer and the solder bumps. In the present invention, the Ni-Cu alloy is adjusted by adjusting the Cu composition of the Ni-Cu alloy layer. It is possible to reduce the growth rate of the intermetallic compound grown between the layer and the solder bumps.
따라서, 본 발명은 고융점 솔더, 공융 솔더 및 무연솔더에 적합한 얇은 두께의 UBM 구조층의 구현이 가능하므로 패키지의 신뢰성을 향상시킬 수 있다.Accordingly, the present invention enables the implementation of a thin UBM structure layer suitable for high melting point solders, eutectic solders, and lead-free solders, thereby improving package reliability.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
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| KR101037692B1 (en) * | 2004-04-16 | 2011-05-30 | 주식회사 하이닉스반도체 | Method for fabricating wafer level package |
| KR100861153B1 (en) | 2005-10-07 | 2008-09-30 | 가부시끼가이샤 르네사스 테크놀로지 | A semiconductor device |
| KR100933201B1 (en) * | 2005-10-07 | 2009-12-22 | 가부시끼가이샤 르네사스 테크놀로지 | Semiconductor device and manufacturing method |
| KR100762354B1 (en) * | 2006-09-11 | 2007-10-12 | 주식회사 네패스 | Flip chip semiconductor package and fabrication method thereof |
| KR101447505B1 (en) * | 2012-06-20 | 2014-10-08 | 서울과학기술대학교 산학협력단 | Solder joint structure having tooth-like structure with excellent efficiency for suppressing the formation of kirkendall voids and method of manufacturing the same |
| US9899584B2 (en) | 2014-11-10 | 2018-02-20 | Samsung Electronics Co., Ltd. | Semiconductor device and package including solder bumps with strengthened intermetallic compound |
| US11127658B2 (en) | 2016-07-18 | 2021-09-21 | Lbsemicon Co., Ltd. | Manufacturing method for reflowed solder balls and their under bump metallurgy structure |
| US11664297B2 (en) | 2016-07-18 | 2023-05-30 | Lbsemicon Co., Ltd. | Manufacturing method for reflowed solder balls and their under bump metallurgy structure |
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|---|---|
| KR100455678B1 (en) | 2004-11-06 |
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