KR20030065214A - Method for inspecting implantation-induced defects - Google Patents
Method for inspecting implantation-induced defects Download PDFInfo
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- KR20030065214A KR20030065214A KR1020020005725A KR20020005725A KR20030065214A KR 20030065214 A KR20030065214 A KR 20030065214A KR 1020020005725 A KR1020020005725 A KR 1020020005725A KR 20020005725 A KR20020005725 A KR 20020005725A KR 20030065214 A KR20030065214 A KR 20030065214A
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- 230000007547 defect Effects 0.000 title claims abstract description 60
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000002513 implantation Methods 0.000 title 1
- 238000005468 ion implantation Methods 0.000 claims abstract description 56
- 239000002245 particle Substances 0.000 claims abstract description 11
- 238000004458 analytical method Methods 0.000 claims description 13
- 238000005498 polishing Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 6
- 230000003287 optical effect Effects 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000007517 polishing process Methods 0.000 abstract description 5
- 238000004151 rapid thermal annealing Methods 0.000 abstract description 3
- 238000009826 distribution Methods 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 이온주입 공정으로 인하여 기판의 실리콘 격자가 파괴 될 때 발생하는 이온주입 결함의 정도를 웨이퍼 전면에서 쉽게 판별할 수 있도록 하는 이온주입 결함 검출방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an ion implantation defect detection method for easily determining the extent of ion implantation defects generated when a silicon lattice of a substrate is destroyed due to an ion implantation process from the front surface of a wafer. will be.
반도체 제조공정 중 이온주입 공정은, 기판으로 사용되는 웨이퍼의 반도체소자 작동영역에 필연적으로 이온주입 결함을 발생시킨다. 이러한 이온주입 결함은 후속 열처리 공정에 의해 적절히 그 분포를 조절할 수 있다. 그러나, 지금까지는 이러한 분포를 확인하기 위하여 웨이퍼를 단면으로 절단하여 단면 TEM을 이용하여 분석하는 방법이 주로 이용되어 왔다. 그러나, 단면 TEM 방법은, 전체 웨이퍼 내의 주입된 이온에 의해 격자 파괴 시, 이온이 어느 부위에 어느 정도 뭉쳐 있는 지를 확인할 수 없고, 국부적인 부분의 결함만을 관찰할 수 있었다. 또한, TEM 관찰을 위하여 시편을 별도로 제작하여야 하는데 많은 시간을 필요로 하여 소자의 제조단가가 높아지는 단점이 있었다. 더욱이, 이렇게 제작된 시편이라 할지라도 TEM 관찰시 이온주입 결함을 쉽게 찾을 수 없다는 단점 또한 있었다.The ion implantation process in the semiconductor manufacturing process inevitably causes ion implantation defects in the semiconductor device operating region of the wafer used as the substrate. Such ion implantation defects can be appropriately controlled by the subsequent heat treatment process. However, until now, in order to confirm such a distribution, a method of cutting a wafer into cross sections and analyzing using a cross section TEM has been mainly used. However, in the cross-sectional TEM method, when lattice breakdown was caused by the implanted ions in the entire wafer, it was not possible to confirm how much ions were aggregated in the region, and only defects in the local portions could be observed. In addition, the specimens must be manufactured separately for the TEM observation, which requires a lot of time, which increases the manufacturing cost of the device. In addition, even the specimen prepared as described above had a disadvantage in that the ion implantation defects were not easily found during the TEM observation.
본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 본 발명이 이루고자 하는 기술적 과제는, 이온주입 결함의 분석뿐만 아니라, 웨이퍼 내부의 결함 분포 및 분석에도 용이한 이온주입 결함 분석방법을 제공하는 데 있다.The present invention is to solve the problems of the prior art as described above, the technical problem to be achieved by the present invention, as well as the analysis of the ion implantation defects, provides an ion implantation defect analysis method that is easy to the defect distribution and analysis in the wafer. There is.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 이온주입 결함 분석방법을 설명하기 위해 순차적으로 나타낸 단면도이다.1A to 1C are cross-sectional views sequentially illustrating a method of analyzing an ion implantation defect analysis according to an exemplary embodiment of the present invention.
도 2은 측정된 이온주입 결함의 파티클 카운터 맵(map)을 나타낸 것이다.2 shows a particle counter map of the measured ion implantation defects.
도 3는 파티클 카운터로 측정한 부분에 대해 이온주입 결함을 확인하기 위하여, 식각용액을 사용하여 표면의 결함영역을 선택적으로 식각하여 현미경으로 관찰한 이온주입 결함 사진이다.FIG. 3 is a photograph of ion implantation defects observed under a microscope by selectively etching a defect region on a surface using an etching solution in order to identify an ion implantation defect with respect to a portion measured by a particle counter.
상기 과제를 이루기 위하여 본 발명에 의한 이온주입 결함 분석방법은, 이온주입 공정이 이루어진 웨이퍼를 열처리하는 단계와, 상기 웨이퍼의 표면을 폴리슁하는 단계, 및 폴리슁이 완료된 웨이퍼의 이온주입 결함을 파티클 카운터를 이용하여 측정하는 단계를 포함한다. 이 때,웨이퍼의 표면을 폴리슁하는 단계에서, 이온주입 결함의 단면 프로파일을 확인하기 위해 이온의 투사범위(Rp)까지 다단계로 폴리슁하는 것이 바람직하다. 상기 다단계 폴리슁 공정 시, 폴리슁 단계 및 측정단계를 반복하여 실시할 수도 있고, 상기 결함 측정 단계 후, 식각액을 사용하여 결함부위를 선택적으로 식각한 다음 광학 현미경으로 관찰할 수도 있다.In order to achieve the above object, the ion implantation defect analysis method according to the present invention comprises the steps of: heat treating a wafer on which an ion implantation process is performed, polishing a surface of the wafer, and ion implantation defects on a wafer on which a polyfin is completed. Measuring using a counter. At this time, in the step of polishing the surface of the wafer, in order to check the cross-sectional profile of the ion implantation defect, it is preferable to polish in multiple steps up to the projection range R p of ions. In the multi-stage polishing process, the polishing step and the measuring step may be repeated, or after the defect measuring step, the defect may be selectively etched using an etchant and then observed with an optical microscope.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
언급한 바와 같이, 반도체 제조공정 중 이온주입 공정에서 발생하는 이온주입 결함을 관찰하기 위해서는 이온주입 공정과 열처리 공정을 진행한 후, 웨이퍼의 단면을 절단하고, TEM을 이용하여 관찰하는 방법이 일반적인 방법이었다. 그러나, 이 방법은 웨이퍼의 면적 일부분만 관찰 할 수 있을 뿐, 웨이퍼 전면에 걸쳐 있는 이온주입 결함의 양상을 파악하기 어렵고 TEM 작업에 많은 시간을 소모한다는 단점이 있었다. 물론, 결함의 모습을 직접 볼 수 있다는 장점을 가지고 있기는 하다. 그러나, 단순한 결함의 정도를 측정하거나, 그 분포를 보고자할 때는 다른 방법이 없어, 단지 특정 예측만 하는 정도였다.As mentioned, in order to observe the ion implantation defects generated in the ion implantation process in the semiconductor manufacturing process, after the ion implantation process and the heat treatment process, the cross section of the wafer is cut and observed using a TEM is a common method It was. However, this method can only observe part of the area of the wafer, and it is difficult to identify the pattern of ion implantation defects across the wafer surface, and it takes a lot of time for TEM operation. Of course, it has the advantage of being able to see the appearance of defects directly. However, there is no other way to measure the degree of a simple defect or to see its distribution.
본 발명은 이러한 점을 극복하기 위하여 이온주입 공정이 완료된 웨이퍼와 파티클 카운터(particle counter)를 이용하여 웨이퍼 전면에 분포하고 있는 이온주입 결함을 쉽게 관찰할 수 있는 방법이다.The present invention is a method that can easily observe the ion implantation defects that are distributed on the entire surface of the wafer using a wafer and a particle counter is completed ion implantation process to overcome this point.
즉, 아르곤(Ar)과 레이져등의 라이트 소스(Light Source)를 이온주입 공정이 완료된 웨이퍼 전면에 주사해서 웨이퍼 표면의 먼지, 실리콘 덩어리 등과 같은 디펙트를 비춤으로써, 디펙트에 의해 반사되어 나오는 빛의 양 차이를 이용하여 웨이퍼 표면에 있는 드펙트를 크기별로 측정하는 파티클 카운터(particle counter)를 이용하여 웨이퍼 전면에 분포하고 있는 이온 주입시 발생된 디펙트로 웨이퍼 기판의 파괴된 격자구조나, 주입된 이온이 뭉쳐 덩어리 형태 등의 이온주입 결함을 쉽게 관찰할 수 있다.That is, a light source such as argon (Ar) and a laser is scanned on the entire surface of the wafer where the ion implantation process is completed, and the defects such as dust and silicon lumps on the surface of the wafer are reflected to light reflected by the defect. Defects generated during ion implantation on the front surface of the wafer using particle counters that measure the size of the defects on the wafer surface by using the difference in the amount of. Ion implantation defects such as lumps can be easily observed.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 이온주입 결함 분석방법을 설명하기 위해 순차적으로 나타낸 단면도이다.1A to 1C are cross-sectional views sequentially illustrating a method of analyzing an ion implantation defect analysis according to an exemplary embodiment of the present invention.
도 1a에 도시된 바와 같이, 이온주입 공정에 의한 결함분포를 확인하기 위하여 먼저 웨이퍼의 조건에 따른 이온주입 공정을 진행한다.As shown in FIG. 1A, in order to confirm a defect distribution by an ion implantation process, an ion implantation process according to a wafer condition is first performed.
이때, 상기 웨이퍼에 주입된 이온은 웨이퍼를 구성하고 있는 실리콘의 격자구조를 파괴하거나, 한곳에 뭉쳐 이온 덩어리 형상을 취하고 있다.At this time, the ions implanted into the wafer destroy the lattice structure of the silicon constituting the wafer, or aggregate into one place to form an ion mass.
그리고, 도 1b에 도시된 바와 같이, 웨이퍼에 주입된 이온을 균일하게 하기 위해 이온주입 공정이 완료된 웨이퍼를 적절한 조건에 따라 열처리를 실시하고, 즉 1000 ~ 1900℃의 온도에서 6 ~ 10시간 동안 질소(N2)분위기에서 열처리하며, 또한, 상기 열처리는 급속 열처리(RTA : Rapid Thermal Anneal)공정으로 진행할 수도 있다.In addition, as shown in FIG. 1B, in order to uniformize the ions implanted into the wafer, the wafer in which the ion implantation process is completed is subjected to heat treatment according to appropriate conditions, that is, nitrogen at a temperature of 1000 to 1900 ° C. for 6 to 10 hours. Heat treatment is performed in an (N 2 ) atmosphere, and the heat treatment may be performed by a rapid thermal annealing (RTA) process.
그러나, 상기 이온 주입 시, 웨이퍼의 이온주입 공정이 진행된 조건에 따른 투사범위(Rp; projection range) 근처에 이온이 집중되어 몰려 있기 때문에 열처리 공정에 의해 집중되어 있는 이온이 결합하여 투사범위(Rp; projection range) 근처에 이온결함이 집중되어 있다.However, in the ion implantation, since the ions are concentrated and concentrated near the projection range (R p ; projection range) according to the condition of the ion implantation process of the wafer, the concentrated ions are combined and the projection range (R) is combined. Ionic defects are concentrated near p ;
이어서, 도 1c에 도시된 바와 같이, 상기 웨이퍼 내부에 발생된 이온결함을 검출하기 위해 웨이퍼에 화학적 물리적 폴리슁(Chemical Mechanical Polishing; CMP) 장비 또는 웨이퍼 폴리슁 장비를 사용하여, 각 이온주입 공정이 진행된 조건에 따른 투사범위(Rp; projection range) 근처의 값 정도로 다단계로 폴리슁을 진행한다.Subsequently, as shown in FIG. 1C, each ion implantation process is performed using chemical mechanical polishing (CMP) equipment or wafer polishing equipment on the wafer to detect ion defects generated in the wafer. proceeds poly swing in multiple stages, so the value of the near; (projection range R p) the projection range in accordance with the advanced condition.
이때, 상기 투사범위(Rp; projection range) 근처의 값까지 폴리슁하는 이유는 이온주입 시, 투사범위 근처에 가장 많은 이온이 주입되어 그 만큼 이온주입 결함이 많이 발생하기 때문이다.At this time, the reason for polishing to the value near the projection range (R p ) is that when ion implantation, most of the ions are implanted near the projection range, so that many ion implantation defects occur.
그리고, 상기 폴리슁이 완료된 웨이퍼 표면에 나타난 디펙트인 이온주입결함(a)을 파티클 카운터(particle counter)로 측정하며 도 2는 파티클 카운터로 측정한 이온주입 결함의 파티클 카운터 맵(map)을 나타낸 것이고, 도 3는 파티클 카운터로 측정한 부분에 대해 이온주입 결함을 확인하기 위하여, 식각용액을 사용하여 표면의 결함영역을 선택적으로 식각하여 현미경으로 관찰한 이온주입 결함 사진이다.In addition, an ion implantation defect (a), which is a defect on the surface of the wafer on which polysilicon is completed, is measured by a particle counter, and FIG. 2 illustrates a particle counter map of ion implantation defects measured by a particle counter. 3 is a photograph of ion implantation defects observed under a microscope by selectively etching a defect region on a surface using an etching solution in order to identify ion implantation defects on a portion measured by a particle counter.
또한, 상기 웨이퍼의 내부 이온주입 결함 분포도를 알려할 경우에는 웨이퍼를 500 ∼ 10,000Å 정도로 단계적으로 폴리슁하여, 각 폴리슁되는 단계마다 파티클 카운터로 맵을 측정한다.In addition, when the internal ion implantation defect distribution map of the wafer is known, the wafer is polished stepwise to about 500 to 10,000 mm 3, and the map is measured by a particle counter for each step of polishing.
이 과정을 반복함으로써 웨이퍼 표면을 측정함으로써 웨이퍼 내부 어느 부위에 이온주입 결함이 가장 많은지 알 수 있어 이온주입 결함의 정도에 대한 정확한 프로파일을 얻을 수 있다.By repeating this process, the surface of the wafer can be measured to find out which part of the wafer has the most ion implantation defects, thereby obtaining an accurate profile of the extent of the ion implantation defects.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주 내에서 당업자에 의해 여러 가지 변형이 가능하다.Meanwhile, the present invention is not limited to the above-described embodiments, but various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims below.
상술한 본 발명에 의한 이온주입 결함 분석방법에 따르면, 기존의 TEM을 이용하는 분석방법보다 쉽게 제조공정 진행 중에 관찰할 수 있다. 또한, TEM 방법에 비해 비교적 짧은 시간 내에 전체 웨이퍼 내에서 결함의 분포를 쉽게 관찰할 수 있으며,이온주입 결함의 분석뿐만 아니라, 웨이퍼 내부의 결함 분포 및 분석에도 용이하다.According to the ion implantation defect analysis method according to the present invention described above, it can be observed during the manufacturing process easier than the conventional analysis method using a TEM. In addition, the distribution of defects within the entire wafer can be easily observed within a relatively short time compared to the TEM method, and it is easy to analyze not only the ion implantation defect but also the distribution and analysis of defects inside the wafer.
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| KR100479296B1 (en) * | 1998-01-12 | 2005-06-17 | 삼성전자주식회사 | Semiconductor Wafer Analysis Method |
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| KR100479296B1 (en) * | 1998-01-12 | 2005-06-17 | 삼성전자주식회사 | Semiconductor Wafer Analysis Method |
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