KR20030061035A - Method for manufacturing semiconductor memory device - Google Patents
Method for manufacturing semiconductor memory device Download PDFInfo
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- KR20030061035A KR20030061035A KR1020020000827A KR20020000827A KR20030061035A KR 20030061035 A KR20030061035 A KR 20030061035A KR 1020020000827 A KR1020020000827 A KR 1020020000827A KR 20020000827 A KR20020000827 A KR 20020000827A KR 20030061035 A KR20030061035 A KR 20030061035A
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- silicon nitride
- film
- spacer
- nitride film
- polysilicon
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 46
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 43
- 229920005591 polysilicon Polymers 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 125000006850 spacer group Chemical group 0.000 claims description 36
- 238000005530 etching Methods 0.000 claims description 10
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000005498 polishing Methods 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
Description
본 발명은 반도체 메모리소자의 제조방법에 관한 것으로써, 보다 상세하게는MFL(Merged flash embedded logic)소자 제조과정의 게이트폴리층의 마진을 확보할 수 있는 반도체 메모리소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device capable of securing a margin of a gate poly layer during a manufacturing process of a merged flash embedded logic (MFL) device.
최근에, 반도체 메모리소자로 셀영역에 2개의 게이트가 동시에 형성되는 스플릿트 게이트(Split gate)의 연구 개발에 대한 관심이 집중되고 있으며, 이와 같은 스플릿트 게이트(Split gate)를 채용한 반도체 메모리소자로 MFL(Merged flash embedded logic)소자 등이 있다.Recently, attention has been focused on the research and development of a split gate in which two gates are simultaneously formed in a cell region as a semiconductor memory device, and a semiconductor memory device employing such a split gate is employed. MFL (Merged Flash Embedded Logic) devices and the like.
종래의 MFL소자의 제조방법은, 도1a에 도시된 바와 같이 얇은 패드산화막(도시되지 않음)이 형성된 반도체기판(10) 상에 서로 이격된 폴리실리콘 재질의 제 1 부유게이트(12) 및 제 2 부유게이트(14)를 형성하고, 상기 제 1 부유게이트(12) 및 제 2 부유게이트(14) 상에 이산화규소(SiO2) 재질의 제 1 스페이서(16) 및 제 2 스페이서(18)를 형성하고, 상기 제 1 부유게이트(12) 및 제 2 부유게이트(14) 사이의 부유게이트(12, 14) 각 측벽에 이산화규소 재질의 제 3 스페이서(20) 및 제 4 스페이서(22)를 형성하고, 상기 제 1 부유게이트(12) 및 제 2 부유게이트(14) 사이에 불순물이 도핑된 폴리실리콘 재질의 공통소오스(24)를 형성하고, 상기 공통소오스(24) 상에 제 1 산화막(26)을 형성한다.In the conventional method of manufacturing an MFL device, as shown in FIG. 1A, a first floating gate 12 and a second floating gate 12 made of polysilicon are spaced apart from each other on a semiconductor substrate 10 on which a thin pad oxide film (not shown) is formed. The floating gate 14 is formed, and the first spacer 16 and the second spacer 18 of silicon dioxide (SiO 2 ) are formed on the first floating gate 12 and the second floating gate 14. The third spacer 20 and the fourth spacer 22 made of silicon dioxide are formed on each sidewall of the floating gates 12 and 14 between the first floating gate 12 and the second floating gate 14. And forming a common source 24 of polysilicon material doped with impurities between the first floating gate 12 and the second floating gate 14, and forming a first oxide layer 26 on the common source 24. To form.
그리고, 상기 제 1 산화막(26)이 형성된 반도체기판(10) 상에 소정두께의 폴리실리콘막(28)을 형성하고, 상기 폴리실리콘막(28) 상에 약 1,500Å정도의 두께로 실리콘나이트라이드막(30)을 형성한다.Then, a polysilicon film 28 having a predetermined thickness is formed on the semiconductor substrate 10 on which the first oxide film 26 is formed, and silicon nitride is formed on the polysilicon film 28 to a thickness of about 1,500 kPa. The film 30 is formed.
이어서, 도1b에 도시된 바와 같이 상기 폴리실리콘막(28) 및 제 1산화막(26)이 노출되도록 실리콘나이트라이드막(30) 및 폴리실리콘막(28)을 CMP(Chemical Mechanical Polishing)한다.Subsequently, as shown in FIG. 1B, the silicon nitride film 30 and the polysilicon film 28 are subjected to CMP (Chemical Mechanical Polishing) to expose the polysilicon film 28 and the first oxide film 26.
이때, 상기 실리콘나이트라이드막(30)은 약 1,500Å두께로 얇게 형성되어 함몰부가 형성됨으로써 CMP 과정에 제 2 스페이서(18) 측부의 실리콘나이트라이드막(30)의 여유 마진이 작아 실리리콘나이트라이드막(30)이 완전히 과식각된 후, 하부의 폴리실리콘막(28)이 외부로 노출 식각될 수도 있다.In this case, the silicon nitride film 30 is thinly formed to a thickness of about 1,500 Å so that the depression is formed, so that the margin of the silicon nitride film 30 at the side of the second spacer 18 is small during the CMP process. After the film 30 is completely overetched, the lower polysilicon film 28 may be exposed and etched to the outside.
다음으로, 도1c에 도시된 바와 같이 상기 CMP에 의해서 노출된 폴리실리콘막(28) 상에 열산화법 등의 방법으로 제 2 산화막(32)을 형성한다.Next, as shown in FIG. 1C, the second oxide film 32 is formed on the polysilicon film 28 exposed by the CMP by a thermal oxidation method or the like.
이때, 실리콘나이트라이드막(30) 상에는 실리콘나이트라이드막(30)의 재질특성에 의해서 제 2 산화막(32)이 형성되고, 도면에는 도시되지 않았으나 상기 CMP 과정에 실리리콘나이트라이드막(30)이 완전히 과식각된 후, 하부의 폴리실리콘막(28)이 외부로 노출된 부위에도 제 2 산화막(32)이 형성된다.In this case, the second oxide film 32 is formed on the silicon nitride film 30 by the material property of the silicon nitride film 30, and although not shown in the drawing, the silicon nitride film 30 is formed in the CMP process. After being completely overetched, the second oxide film 32 is also formed at a portion of the lower polysilicon film 28 exposed to the outside.
마지막으로, 도1d에 도시된 바와 같이 제 1 산화막(26) 및 제 2 산화막(32)을 식각 마스크로 사용하여 실리콘나이트라이드막(30) 및 폴리실리콘막(28)을 식각함으로써 채널층(34)을 형성한다.Lastly, as shown in FIG. 1D, the silicon nitride film 30 and the polysilicon film 28 are etched using the first oxide film 26 and the second oxide film 32 as an etching mask. ).
그러나, 종래의 반도체 메모리소자의 제조방법은, 상기 CMP 과정에 실리콘나이트라이드막의 여유 마진이 작아 실리리콘나이트라이드막이 완전히 과식각된 후, 하부의 폴리실리콘막이 외부로 노출되어 식각되었다.However, in the conventional method of manufacturing a semiconductor memory device, the margin of the silicon nitride film is so small that the silicon nitride film is completely overetched during the CMP process, and the lower polysilicon film is exposed to the outside for etching.
따라서, 상기 노출된 폴리실리콘막 상에 제 2 산화막이 형성됨으로써 후속 식각공정에서 마스크로 작용하여 ??리실리콘막을 잔류시키는 문제점이 있었다.Therefore, since the second oxide film is formed on the exposed polysilicon film, there is a problem of remaining the? Silicon film by acting as a mask in a subsequent etching process.
본 발명의 목적은, CMP 후, 제 2 스페이서 측부의 폴리실리콘막 상에 형성된 실리콘나이트라이드막의 여유 마진이 작아 CMP 과정에 실리콘나이트라이드막이 완전히 식각된 후, 폴리실리콘막이 외부로 노출되는 것을 방지할 수 있는 반도체 메모리소자의 제조방법을 제공하는 데 있다.An object of the present invention is that after the CMP, the margin of the silicon nitride film formed on the polysilicon film on the second spacer side is small so that the polysilicon film is prevented from being exposed to the outside after the silicon nitride film is completely etched during the CMP process. The present invention provides a method for manufacturing a semiconductor memory device.
도1a 내지 도1d는 종래의 반도체 MFL소자의 제조방법을 설명하기 위한 단면도들이다.1A to 1D are cross-sectional views illustrating a conventional method for manufacturing a semiconductor MFL device.
도2a 내지 도2e는 본 발명의 일 실시예에 따른 반도체 MFL소자의 제조방법을 설명하기 위한 단면도들이다.2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor MFL device according to an embodiment of the present invention.
※ 도면의 주요 부분에 대한 부호의 설명※ Explanation of codes for main parts of drawing
10, 40 : 반도체기판 12, 42 : 제 1 부유게이트10, 40: semiconductor substrate 12, 42: first floating gate
14, 44 : 제 2 부유게이트 16, 46 : 제 1 스페이서14, 44: second floating gate 16, 46: first spacer
18, 48 : 제 2 스페이서 20, 50 : 제 3 스페이서18, 48: second spacer 20, 50: third spacer
22, 52 : 제 4 스페이서 24, 54 : 공통소오스22, 52: fourth spacer 24, 54: common source
26, 56 : 제 1 산화막 28, 58 : 폴리실리콘막26, 56: first oxide film 28, 58: polysilicon film
30, 60 : 실리콘나이트라이드막 32, 62 : 제 2 산화막30, 60: silicon nitride film 32, 62: second oxide film
34, 64 : 채널층34, 64: channel layer
상기 목적들을 달성하기 위한 본 발명에 따른 반도체 메모리소자의 제조방법은, 소정간격 서로 이격된 절연재질의 제 1 스페이서 및 제 2 스페이서가 상부에 각각 형성된 제 1 부유게이트 및 제 2 부유게이트와 상기 제 1 부유게이트 및 제 2 부유게이트 측벽에 각각 형성된 절연재질의 제 3 스페이서 및 제 4 스페이서와 상기 제 1 스페이서 및 제 2 스페이서 사이에 매몰 형성된 공통소오스와 상기 공통소오스 상에 형성된 제 1 산화막을 구비하는 반도체기판을 준비하는 단계; 상기 반도체기판 상에 폴리실리콘막을 형성하는 단계; 상기 폴리실리콘막 상에 함몰부가 형성되지 않도록 실리콘나이트라이드막을 두껍게 형성하는 단계; 상기 실리콘나이트라이드막을 소정두께로 에치백(Etchback)하는 단계; 및 상기 에치백 후, 상기 제 1 산화막이 노출되도록 상기 실리콘나이트라이드막 및 폴리실리콘막을 CMP하는 단계;를 포함하여 이루어지는 것을 특징으로 한다.In accordance with an aspect of the present invention, there is provided a method of fabricating a semiconductor memory device, the first floating gate and the second floating gate each having a first spacer and a second spacer of an insulating material spaced apart from each other by a predetermined distance therebetween. A third spacer and an insulating material formed on the sidewalls of the first floating gate and the second floating gate, respectively, and a common source buried between the first spacer and the second spacer, and a first oxide film formed on the common source. Preparing a semiconductor substrate; Forming a polysilicon film on the semiconductor substrate; Forming a thick silicon nitride film such that a depression is not formed on the polysilicon film; Etching back the silicon nitride film to a predetermined thickness; And after the etch back, CMPing the silicon nitride film and the polysilicon film to expose the first oxide film.
여기서, 상기 실리콘나이트라이드막은 4,000Å 내지 6,000Å의 두께로 형성할 수 있고, 상기 CMP는 상기 실리콘나이트라이드막을 1,000Å 내지 2,000Å의 두께로 형성할 수 있다.Here, the silicon nitride film may be formed to a thickness of 4,000 kPa to 6,000 kPa, and the CMP may form the silicon nitride film to a thickness of 1,000 kPa to 2,000 kPa.
그리고, 상기 CMP후, 상기 노출된 폴리실리콘막 상에 제 2 산화막을 형성하는 공정이 더 수행되고, 상기 제 2 산화막을 마스크로 사용하여 상기 실리콘나이트라이드막 및 폴리실리콘막을 식각하는 공정이 더 수행됨이 바람직하다.After the CMP, a process of forming a second oxide film on the exposed polysilicon film is further performed, and a process of etching the silicon nitride film and the polysilicon film using the second oxide film as a mask is further performed. This is preferred.
이하, 첨부한 도면을 참고로 하여 본 발명의 구체적인 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도2a 내지 도2e는 본 발명의 일 실시예에 따른 MFL 반도체 메모리소자의 제조방법을 설명하기 위한 단면도들이다.2A through 2E are cross-sectional views illustrating a method of manufacturing an MFL semiconductor memory device according to an embodiment of the present invention.
본 발명에 따른 MFL 반도체 메모리소자의 제조방법은, 도2a에 도시된 바와 같이 패드산화막(도시되지 않음)이 형성된 반도체기판(40) 상에 서로 이격된 폴리실리콘 재질의 제 1 부유게이트(42) 및 제 2 부유게이트(44)를 형성하고, 상기 제 1 부유게이트(42) 및 제 2 부유게이트(44) 상에 산화막 계열의 제 1 스페이서(46) 및 제 2 스페이서(48)를 각각 형성한다.In the method of manufacturing an MFL semiconductor memory device according to the present invention, as shown in FIG. 2A, a first floating gate 42 made of polysilicon is spaced apart from each other on a semiconductor substrate 40 on which a pad oxide film (not shown) is formed. And a second floating gate 44, and an oxide film-based first spacer 46 and a second spacer 48 are formed on the first floating gate 42 and the second floating gate 44, respectively. .
이때, 상기 각 스페이서(46, 48)는 반도체기판(40) 상에 폴리실리콘막 및 개구부가 형성된 더미(Dummy)용 질화규소막을 순차적으로 형성하고, 상기 더미용 질화규소막 상에 스페이서(46, 48) 형성용 산화막을 형성한 후, 에치백공정을 수행함으로써 상기 개구부 측부에 스페이서(46, 48)를 형성할 수 있다.In this case, each of the spacers 46 and 48 sequentially forms a dummy silicon nitride film having a polysilicon film and an opening formed on the semiconductor substrate 40, and the spacers 46 and 48 on the dummy silicon nitride film. After the formation oxide film is formed, spacers 46 and 48 may be formed on the side of the opening by performing an etch back process.
그리고, 상기 더미용 질화규소막을 습식 식각 제거한 후, 상기 스페이서(46, 48)를 마스크로 사용하여 폴리실리콘막을 식각함으로써 스페이서(46, 48) 하부에 각각 부유게이트(42, 44)를 형성할 수 있다.After the wet silicon oxide film is removed by the dummy silicon nitride layer, the floating gates 42 and 44 may be formed under the spacers 46 and 48 by etching the polysilicon layer using the spacers 46 and 48 as masks. .
또한, 상기 제 1 부유게이트(42) 및 제 2 부유게이트(44) 사이의부유게이트(42, 44) 각 측벽에 산화막 계열의 제 3 스페이서(50) 및 제 4 스페이서(52)를 형성한다.In addition, an oxide film-based third spacer 50 and a fourth spacer 52 are formed on each sidewall of the floating gates 42 and 44 between the first floating gate 42 and the second floating gate 44.
이때, 상기 제 3 스페이서(50) 및 제 4 스페이서(52)는 제 1 스페이서(46) 및 제 2 스페이서(48)가 형성된 반도체기판(40) 전면에 산화막을 형성한 후, 에치백공정을 수행함으로써 형성할 수 있다.In this case, the third spacer 50 and the fourth spacer 52 are formed on the entire surface of the semiconductor substrate 40 on which the first spacer 46 and the second spacer 48 are formed, followed by an etch back process. It can form by doing.
그리고, 상기 제 1 부유게이트(46) 및 제 2 부유게이트(48) 사이에 불순물이 도핑된 폴리실리콘 재질의 공통소오스(54)를 형성하고, 상기 공통소오스(54) 상에 제 1 산화막(56)을 형성한다.A common source 54 made of polysilicon doped with impurities is formed between the first floating gate 46 and the second floating gate 48, and the first oxide layer 56 is formed on the common source 54. ).
다음으로, 제 1 산화막(56)이 형성된 반도체기판(40) 상에 소정두께로 폴리실리콘막(58)를 형성하고, 상기 폴리실리콘막(58) 상에 종래의 약 1,500Å보다 두껍게 4,000Å 내지 6,000Å, 바람직하게는 약 5,000Å의 두께로 실리콘나이트라이드막(60)을 형성한다.Next, a polysilicon film 58 is formed on the semiconductor substrate 40 on which the first oxide film 56 is formed to a predetermined thickness, and on the polysilicon film 58, the thickness is about 4,000 kPa to about 1,500 kPa. The silicon nitride film 60 is formed to a thickness of 6,000 kPa, preferably about 5,000 kPa.
계속해서, 도2b에 도시된 바와 같이 상기 실리콘나이트라이드막(60)을 약 3,000Å 내지 4,000Å, 바람직하게는 약 3,500Å정도 에치백(Etchback)하여 약 1,000Å 내지 2,000Å, 바람직하게는 약 1,500Å로 형성한다.Subsequently, as shown in FIG. 2B, the silicon nitride film 60 is etched back to about 3,000 kPa to 4,000 kPa, preferably about 3,500 kPa, and about 1,000 kPa to 2,000 kPa, preferably about It is formed to 1,500Å.
이어서, 도2c에 도시된 바와 같이 에치백된 반도체기판(40)의 실리콘나이트라이드막(60) 및 폴리실리콘막(58)을 CMP하여 제 1 산화막(56)을 노출시킨다.Next, as shown in FIG. 2C, the silicon nitride film 60 and the polysilicon film 58 of the etched back semiconductor substrate 40 are CMP to expose the first oxide film 56.
이때, 본 발명에 따라 약 5,000Å의 두께로 실리콘나이트라이드막(60)을 형성한 후, 에치백에 의해서 표면이 평탄화됨으로써 CMP 후, 제 2 스페이서(48) 측부의 실리콘나이트라이드막(60)에는 종래와 달리 함몰부가 형성되지 않고, 실리콘나이트라이드막(60)이 종래보다 두껍게 잔존하게 됨으로써 폴리실리콘막(58)이 외부로 노출되지 않는다.At this time, after forming the silicon nitride film 60 to a thickness of about 5,000 kPa in accordance with the present invention, the surface is planarized by etch back, so that after the CMP, the silicon nitride film 60 on the side of the second spacer 48 Unlike in the prior art, no depression is formed, and since the silicon nitride film 60 remains thicker than before, the polysilicon film 58 is not exposed to the outside.
다음으로, 도2d에 도시된 바와 같이 상기 CMP에 의해서 노출된 폴리실리콘막(58) 상에 열산화법 등의 방법으로 제 2 산화막(62)을 형성한다.Next, as shown in FIG. 2D, the second oxide film 62 is formed on the polysilicon film 58 exposed by the CMP by a thermal oxidation method or the like.
이때, 실리콘나이트라이드막(60) 상에는 실리콘나이트라이드막(60)의 재질특성에 의해서 제 2 산화막(62)이 형성된다.At this time, the second oxide film 62 is formed on the silicon nitride film 60 by the material characteristics of the silicon nitride film 60.
마지막으로, 도2e에 도시된 바와 같이 제 1 산화막(56) 및 제 2 산화막(62)을 식각 마스크로 사용하여 실리콘나이트라이드막(60) 및 폴리실리콘막(58)을 식각함으로써 채널층(64)을 형성한다.Finally, as shown in FIG. 2E, the silicon nitride film 60 and the polysilicon film 58 are etched using the first oxide film 56 and the second oxide film 62 as an etching mask. ).
본 발명에 의하면, CMP 후, 제 2 스페이서 측부의 폴리실리콘막 상에 형성된 실리콘나이트라이드막의 여유 마진이 작아 CMP 과정에 실리콘나이트라이드막이 완전히 식각된 후, 폴리실리콘막이 외부로 노출되는 것을 방지할 수 있다.According to the present invention, after the CMP, the margin of the silicon nitride film formed on the polysilicon film on the side of the second spacer is small so that the polysilicon film is prevented from being exposed to the outside after the silicon nitride film is completely etched during the CMP process. have.
따라서, 상기 노출된 폴리실리콘막 상에 제 2 산화막이 형성되어 식각 마스크로 기능함으로써 제 2 산화막 하부의 폴리실리콘막이 반도체기판 상에 잔류하는 것을 방지할 수 있는 효과가 있다.Therefore, the second oxide film is formed on the exposed polysilicon film and functions as an etching mask, thereby preventing the polysilicon film under the second oxide film from remaining on the semiconductor substrate.
이상에서는 본 발명은 기재된 구체예에 대해서만 상세히 설명되었지만 본 발명의 기술 사상 범위 내에서 다양한 변형 및 수정이 가능함은 당업자에게 있어서 명백한 것이며, 이러한 변형 및 수정이 첨부된 특허청구범위에 속함은 당연한 것이다.Although the present invention has been described in detail only with respect to the described embodiments, it will be apparent to those skilled in the art that various modifications and variations are possible within the technical spirit of the present invention, and such modifications and modifications belong to the appended claims.
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