KR20030058585A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to make a bitline and an upper electrode contact different metal interconnections and maintain uniform contact resistance regardless of a recessed degree of a tungsten plug, by forming a contact hole for the metal interconnection in contact with the bitline in a peripheral area and forming a contact hole for the metal interconnection in contact with the upper electrode while a metal interconnection contact is formed. CONSTITUTION: A plug is filled in a step between a bitline and a bitline formed in a cell area. A capacitor is electrically connected to the plug. The first interlayer dielectric(73) is formed on a lower structure(51) including the plug and the capacitor. The first interlayer dielectric is etched. The lower structure is selectively etched to form the first contact hole for the metal interconnection in contact with the bitline. The second plug is formed as a filling layer of the first contact hole for the metal interconnection. The first metal layer is formed and etched to form the first metal interconnection. The second interlayer dielectric(83) is formed on the resultant structure. The first and second interlayer dielectrics are etched to form the second contact hole(85) for the metal interconnection in contact with the upper electrode through a photolithography process using a mask for the second metal interconnection contact. The second interlayer dielectric is etched to form the third contact hole(87) for the metal interconnection in contact with the first metal interconnection.

Description

Method for manufacturing semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to forming a metal wiring contact hole in contact with a bit line in a peripheral region, and for metal wiring contacting an upper electrode of a capacitor together with forming a metal wiring contact in a subsequent process. The present invention relates to a method for manufacturing a semiconductor device that forms a contact, thereby improving the yield and reliability of the device.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art, in which “A” shows a cell region, and “B” shows a first region where a metal wiring contacting the upper electrode is to be formed. The peripheral region is shown, and "C" shows the second peripheral region, which is the region where the metal wiring in contact with the bit line is to be formed.

FIG. 2 is a photograph showing a metal wiring contact hole contacting a conventional over-etched upper electrode, and FIG. 3 is a metal wiring contact hole contacting a conventional upper electrode over-etched to short a gate electrode and a metal wiring. Figure 4 is a photograph showing the phenomenon, Figure 4 is a graph showing the contact resistance value according to the degree of recess of the conventional tungsten plug.

Referring to FIG. 1A, a bit line 13 having a hard mask layer 15 on an upper side thereof and an insulating layer spacer 17 on both sides thereof and a bit line formed in the cell region A may be formed. The first oxide film 21 is formed on the lower structure 11 including the plug 19 to fill the step between the 13 and the hard mask layer 15 by the chemical mechanical polishing method. 1 The oxide film 21 is etched flat.

After the nitride film 23 and the second oxide film 25 are sequentially formed on the entire surface including the first oxide film 21, the planarization process is performed.

Subsequently, the second oxide layer 25 and the nitride layer 23 are etched by a photolithography process using a lower electrode contact mask to form a lower electrode contact hole.

A liner TiN layer is formed on the plug layer 19 and the second oxide layer 25 exposed by the lower electrode contact hole.

Thereafter, the TiN layer is flat-etched by a chemical mechanical polishing method using the second oxide film 25 as an etching end point, and a lower portion separated from each other by the second oxide film 25 and electrically connected to the plug layer 19. The electrode 27 is formed.

The dielectric layer 29 is formed on the entire surface including the lower electrode 27, and the dielectric layers 29 of the first and second peripheral regions B and C are selectively etched.

Thereafter, the upper electrode 31 of the capacitor is formed on the entire surface including the dielectric layer 29, and the upper electrode 31 of the second peripheral region C is selectively etched.

Referring to FIG. 1B, an interlayer insulating layer 33 is formed on the upper electrode 31.

The interlayer insulating layer 33 is etched by a photolithography process using a metal wiring contact mask to form a first contact hole 35 for metal wiring contacting the upper electrode 31, and the interlayer insulating layer 33 ), The second oxide film 25, the nitride film 23, and the hard mask layer 15 are etched to form a second contact hole 37 for metal wiring contacting the bit line 13. In this case, as shown in FIG. 2, since the etching process is performed using a step that is contacted with the bit line 13 as a target during the first and second contact hole 35 and 37 forming processes, the first contact The hole 35 is subjected to transient etching (A).

Referring to FIG. 1C, a barrier metal layer 39 and a tungsten (W) layer 41 are sequentially formed on the entire surface including the first and second contact holes 35 and 37.

The tungsten layer 41 and the barrier metal layer 39 are etched flat by a chemical mechanical polishing process using the interlayer insulating layer 33 as an etch stop layer to form a tungsten plug. At this time, since the first contact hole 35 is formed by excessive etching, the upper portion of the upper electrode 31 has a recess value of the tungsten plug as shown in FIG. The contact resistance between the upper electrode 31 and the tungsten plug changes according to the degree of settling.

Thereafter, an aluminum (Al) layer 43 of metal wiring is formed on the interlayer insulating film 33 including the tungsten layer 41. In this case, as shown in FIG. 3, a short B is generated between the gate electrode G and the metal wire 43 by the excessively etched first contact hole 35.

However, in the conventional semiconductor device capacitor and its manufacturing method, the upper electrode contact is formed with the contact of the bit line of the peripheral circuit so that the bit line and the upper electrode are in contact with the same metal wiring, so that the upper electrode contact is punched to the lower structure. There is a problem in that throw-through occurs and contact resistance changes according to the degree of recess of tungsten, which is a wiring layer, thereby degrading yield and reliability of the device.

The present invention has been made to solve the above problems to form a metal wiring contact hole that is in contact with the bit line of the peripheral area, and to form a metal wiring contact in contact with the upper electrode of the capacitor as well as forming a metal wiring contact in a subsequent process The bit line and the upper electrode are in contact with different metal wires, and the punch-through is prevented from occurring to the lower structure during the upper electrode contact forming process, and the contact resistance is kept constant regardless of the degree of recess of the tungsten plug. Its purpose is to provide a method for manufacturing a semiconductor device.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2 is a photograph showing a contact hole for a metal wiring contacted with a conventional over-etched upper electrode.

3 is a photograph showing a phenomenon in which a contact hole for a metal wiring in contact with the conventional upper electrode is excessively etched and the gate electrode and the metal wiring are shorted.

Figure 4 is a graph showing the contact resistance value according to the degree of recess of the conventional tungsten plug.

5A through 5F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

11, 51: substructure 13, 53: bit line

15, 55: hard mask layer 17, 57: insulating film spacer

19: plug 21, 61: first oxide film

23, 63: nitride film 25, 65: second oxide film

27, 67: lower electrode 29, 69: dielectric film

31, 71: upper electrode 33: interlayer insulating film

35, 75: first contact hole for metal wiring 37, 85: second contact hole for metal wiring

39: barrier metal layer 41: tungsten layer

43: aluminum layer 59: first plug

73: first interlayer insulating film 77: first barrier metal layer

79: first tungsten 83: second interlayer insulating film

87: third contact hole for metal wiring 89: second barrier metal layer

91: second tungsten 93: second aluminum layer

The present invention for achieving the above object is a step of forming a first interlayer insulating film on a lower structure including a plug and a plug to fill the step between the bit line and the bit line formed in the cell region and the capacitor electrically connected to the plug, the first Etching the first interlayer insulating film and selectively etching the lower structure by a photolithography process using a metal wiring contact mask to form a first metal wiring contact hole in contact with the bit line, wherein the first metal wiring contact Forming a second plug that is a buried layer of holes, forming a first metal layer on the entire surface, and etching the first metal layer by a photolithography process using a metal wiring mask to form a first metal wire; Forming a second interlayer insulating film on the entire surface including the wiring and the second metal wiring contact The first and second interlayer insulating layers are etched by using a photolithography process to form a second metal wiring contact hole contacting the upper electrode of the capacitor, and the second interlayer insulating layer is etched to etch the first metal wiring. Providing a method for manufacturing a semiconductor device, the method including forming a contact hole for a third metal wiring contacted with

Forming the upper electrode in a TiN layer or a TiN / tungsten laminated structure having a thickness of 1000 to 2000 占 퐉;

Forming the first interlayer insulating film at a thickness of 2000 to 4000 kPa;

The second interlayer insulating film is formed to a thickness of 8000 to 10000 kPa.

The principle of the present invention is to form a metal wiring contact hole that is in contact with the bit line of the peripheral region and to form a metal wiring contact in contact with the upper electrode of the capacitor in a subsequent process, so that the bit line and the upper electrode Since the etching process targets the upper electrode contact step and contacts the different metal wires, the punch-through is prevented from occurring to the lower structure during the upper electrode contact forming process, and the upper electrode and the lower portion of the contact are in contact with each other. The invention maintains a constant contact resistance regardless of the degree of recess of the tungsten plug.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

5A to 5F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, where “A” shows a cell region, and “B” shows a region where a metal wiring contacting the upper electrode is to be formed. Is a first peripheral region, and “C” shows a second peripheral region, which is a region where a metal wiring in contact with a bit line is to be formed.

Referring to FIG. 5A, the gap between the bit line 53 having the hard mask layer 55 on the upper side and the insulating layer spacer 57 on the both sides and the bit line 53 formed on the cell region A is buried. The first oxide layer 61 is formed on the lower structure 51 including the first plug 59, and the hard mask layer 59 is etched to the end point by the chemical mechanical polishing method. Etch a flat surface.

After the nitride film 63 and the second oxide film 65 are sequentially formed on the entire surface including the first oxide film 61, the planarization process is performed.

Subsequently, the second oxide layer 65 and the nitride layer 63 are etched by a photolithography process using a mask for lower electrode contact to form a lower electrode contact hole.

A liner TiN layer is formed on the plug layer 59 and the second oxide layer 65 exposed by the lower electrode contact hole.

Thereafter, the TiN layer is flat-etched by the chemical mechanical polishing method using the second oxide film 65 as an etching end point, and the lower portion separated from each other by the second oxide film 65 and electrically connected to the plug layer 59. Electrode 67 is formed.

In addition, a dielectric film 69 is formed on the entire surface including the lower electrode 67, and the dielectric film 69 of the peripheral region B is selectively etched.

Thereafter, an upper electrode 71 having a thickness of 1000 to 2000 Å of a capacitor is formed on the entire surface including the dielectric film 69. In this case, the upper electrode 71 is formed of a TiN layer or a stacked structure of TiN / tungsten.

As shown in FIG. 5B, a first interlayer insulating film 73 having a thickness of 2000 to 4000 Å is formed on the upper electrode 71.

The first interlayer insulating film 73, the second oxide film 65, the nitride film 63, and the hard mask layer 55 are etched by a photolithography process using a metal wiring contact mask to form the bit line 53. A first contact hole 75 for first metal wiring contacting the first metal wiring is formed.

As shown in FIG. 5C, the first barrier metal layer 77 and the first tungsten layer 79 are sequentially formed on the entire surface including the first contact hole 75.

Subsequently, the first tungsten layer 79 and the first barrier metal layer 77 are etched by a chemical mechanical polishing process using the first interlayer insulating layer 73 as an etch stop layer to form a second plug. In this case, the first tungsten layer 79 and the first barrier metal layer 77 may be flat-etched by using an etch back process instead of the chemical mechanical polishing process.

As shown in FIG. 5D, a first aluminum layer is formed on the first interlayer insulating layer 73 including the second plug.

The first aluminum layer is etched by a photolithography process using a metal wiring mask to form a metal wiring 81 in contact with the bit line 53.

As shown in FIG. 5E, a second interlayer insulating film 83 having a thickness of 8000 to 10000 kPa is formed on the first interlayer insulating film 73 including the metal wiring 81 in contact with the bit line 53.

In addition, the first and second interlayer insulating layers 73 and 83 are etched by a photolithography process using a metal wiring contact mask contacting the upper electrode 71 for metal wiring contacting the upper electrode 71. A second contact hole 85 is formed, and the second interlayer insulating layer 83 is etched to form a third contact hole 87 for metal wiring, which is in contact with the metal wiring 81 that is in contact with the bit line 53. do.

As shown in FIG. 5F, the second barrier metal layer 89 and the second tungsten layer 91 are sequentially formed on the entire surface.

Then, the second tungsten layer 91 and the second barrier metal layer 89 are etched flat by a chemical mechanical polishing process using the second interlayer insulating layer 83 as an etch stop layer to form a third plug. In this case, the second tungsten layer 91 and the second barrier metal layer 89 may be flat-etched by using an etch back process instead of the chemical mechanical polishing process.

Subsequently, a second aluminum layer 93 having a wiring contacting the upper electrode 71 is formed on the second interlayer insulating layer 83 including the third plug.

The method of manufacturing a semiconductor device of the present invention forms a metal wiring contact hole in contact with a bit line in a peripheral region, and subsequently forms a metal wiring contact and a metal wiring contact in contact with an upper electrode of a capacitor. Since the upper electrode and the upper electrode are in contact with different metal wires, and the etching process is performed to target the upper electrode contact step, the punch throw is prevented from occurring to the lower structure during the upper electrode contact forming process. Since the parts are in contact, the contact resistance is kept constant regardless of the degree of recess of the tungsten plug, thereby improving the yield and reliability of the device.

Claims (4)

Forming a first interlayer insulating film on a lower structure including a plug filling a step between the bit line and the bit line formed in the cell region and a capacitor electrically connected to the plug; Etching the first interlayer insulating layer and selectively etching the lower structure by a photolithography process using a first metal wiring contact mask to form a first metal wiring contact hole in contact with the bit line; Forming a second plug that is a buried layer of the first metal wiring contact hole; Forming a first metal layer by forming a first metal layer on the entire surface and etching the first metal layer by a photolithography process using a mask for metal wiring; Forming a second interlayer insulating film on the entire surface including the first metal wiring; The first and second interlayer insulating layers are etched by a photolithography process using a mask for forming a second metal wiring contact to form a second metal wiring contact hole contacting the upper electrode of the capacitor, and the second interlayer insulating layer is etched. Forming a third metal wiring contact hole in contact with the first metal wiring. The method of claim 1, The upper electrode is formed of a TiN layer having a thickness of 1000 to 2000 GPa or a stacked structure of TiN / tungsten. The method of claim 1, A method for manufacturing a semiconductor device, wherein the first interlayer insulating film is formed to a thickness of 2000 to 4000 kPa. The method of claim 1, A method for manufacturing a semiconductor device, wherein the second interlayer insulating film is formed to a thickness of 8000 to 10000 kPa.