KR20030058508A - Method for forming pattern of semiconductor device - Google Patents
Method for forming pattern of semiconductor device Download PDFInfo
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- KR20030058508A KR20030058508A KR1020010088964A KR20010088964A KR20030058508A KR 20030058508 A KR20030058508 A KR 20030058508A KR 1020010088964 A KR1020010088964 A KR 1020010088964A KR 20010088964 A KR20010088964 A KR 20010088964A KR 20030058508 A KR20030058508 A KR 20030058508A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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Abstract
Description
본 발명은 반도체소자의 패턴 형성방법에 관한 것으로서, 보다 상세하게는 패턴 형성을 위한 리소그래피공정시에 스윙(swing) 또는 나칭(notching) 최소화를 통해 최적의 CD 정의를 위해 사용하는 무기(inorganic) 반사방지막(ARL; anti reflective layer) 형성시에 적용하는 반도체소자의 패턴 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a pattern of a semiconductor device, and more particularly, to an inorganic reflection used for optimal CD definition through minimizing swinging or notching during a lithography process for forming a pattern. The present invention relates to a method of forming a pattern of a semiconductor device to be applied when forming an anti reflective layer (ARL).
반도체 제조공정중 폴리 또는 금속의 높은 반사로 인해 정확한 CD 구현이 어렵기 때문에 이를 방지하기 위해 반사방지막이 사용되고 있으며, 단가가 비싼 유기 ARC (anti reflection coating)보다는 비용이 적게 들고 원하는 상수 (n 및 k)값 조절이 가능한 무기 ARC 산화질화막을 CVD 방법에 의해 증착하여 사용하고 있다.Due to the high reflection of poly or metal during the semiconductor manufacturing process, it is difficult to achieve accurate CD.An anti-reflective film is used to prevent this, and it is less expensive than the expensive organic anti-reflection coating (ARC) and has a desired constant (n and k). The inorganic ARC oxynitride film whose value can be adjusted is deposited and used by the CVD method.
이러한 ARC 산화막을 이용한 종래기술에 따른 반도체소자의 패턴 형성방법을 설명하면 다음과 같다.Referring to the method of forming a pattern of a semiconductor device according to the prior art using the ARC oxide film as follows.
도 1은 종래기술에 따른 반도체소자의 패턴 형성방법에 있어서, 감광막패턴 측면에 발생하는 프팅(footing) 현상을 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a phenomenon in which a footing occurs on a side surface of a photoresist pattern in a method of forming a pattern of a semiconductor device according to the related art.
종래기술에 따른 반도체소자의 패턴 형성방법은, 도 1에 도시된 바와같이, 폴리실리콘 또는 금속을 이용하여 배선층(11)을 증착한다.In the method of forming a pattern of a semiconductor device according to the prior art, as shown in FIG. 1, the wiring layer 11 is deposited using polysilicon or metal.
그다음, 상기 배선층(11)상에 무기 반사방지막(ARL; anti reflective layer)(13)을 CVD법으로 증착하고, 상기 반사방지막(13)상에 질소가 도핑된 산화막(15)을 증착한다.Next, an inorganic antireflective layer (ARL) 13 is deposited on the wiring layer 11 by CVD, and an oxide film 15 doped with nitrogen is deposited on the antireflective layer 13.
이어서, 상기 질소가 도핑된 산화막(15)상에 감광물질을 도포하고, 이를 포토 및 식각공정을 통해 선택적으로 제거하여 감광막패턴(17)을 형성한다.Subsequently, a photosensitive material is coated on the nitrogen doped oxide film 15 and selectively removed through a photo and etching process to form the photosensitive film pattern 17.
그러나, 종래기술에 의하면, 산화질화막의 경우 질소성분이 감광물질(photo resist)과 반응하여 도1의 "A"에서와 같은 프팅(flooting) 현상이 발생하는 문제가 있다.However, according to the related art, in the case of the oxynitride film, a nitrogen component reacts with a photoresist to cause a floating phenomenon such as "A" of FIG. 1.
따라서, 이러한 문제를 개선하기 위해 현재 산화질화막을 증착한후 N2O 플라즈마 처리를 수행하기도 하였으나 최근에는 강산의 PR이 사용되는 추세에 있기 때문에 산화질화막의 표면을 N2O 플라즈마 처리를 한다 하더라도 스컴(scum) 발생확률이 높아지게 되는 문제가 있다. 즉, 고집적화된 소자로 갈수록 N2O 플라즈마 처리에 의한 산화시에 막 표면에 미량의 질소 성분이 포함되어 있으며, 이러한 질소성분이 감광물질과 반응하여 스컴 현상을 발생시킨다.Thus, depositing a current oxynitride film in order to improve these problems, N 2 O, but also perform the plasma treatment Recently, even if the N 2 O plasma treatment to the surface of the oxynitride film, because the tendency of strong PR used scum (scum) There is a problem that the probability of occurrence increases. In other words, the more highly integrated device, a small amount of nitrogen contained on the surface of the film during oxidation by N 2 O plasma treatment, the nitrogen component reacts with the photosensitive material to generate a scum phenomenon.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 패턴을 형성하기 위한 리소그라피공정중에 스컴(scum) 등의 현상을 배제하여 패턴의 정확한 CD 구현이 가능하여 반도체수율 및 품질을 향상시킬 수 있는 반도체소자의 패턴 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, it is possible to implement the accurate CD of the pattern by eliminating the phenomenon such as scum during the lithography process for forming the pattern to improve the semiconductor yield and quality It is an object of the present invention to provide a method for forming a pattern of a semiconductor device.
도 1은 종래기술에 따른 반도체소자의 패턴 형성방법에 있어서, 감광막패턴 측면에 발생하는 프팅(footing) 현상을 설명하기 위한 단면도.1 is a cross-sectional view illustrating a phenomenon in which a footing occurs on a side surface of a photoresist pattern in a method of forming a pattern of a semiconductor device according to the prior art.
도 2는 본 발명에 따른 반도체소자의 패턴 형성방법에 있어서, 질소가 포함되지 않은 산화막을 이용하여 감광막패턴의 측면에 프팅(footing) 현상이 발생되지 않음을 설명하기 위한 단면도.FIG. 2 is a cross-sectional view for explaining that in the method of forming a pattern of a semiconductor device according to the present invention, a phenomenon in which a footing does not occur on the side surface of the photosensitive film pattern using an oxide film not including nitrogen is shown.
도 3은 본 발명에 따른 반도체소자의 패턴 형성방법에 있어서, 금속 다마신 공정에 적용한 경우에 질소가 포함되지 않은 산화막을 산소플라즈마 처리에 의해 형성한 경우에 나타나는 현상을 설명하기 위한 단면도.3 is a cross-sectional view for explaining a phenomenon that occurs when an oxide film containing no nitrogen is formed by oxygen plasma treatment in the method of forming a pattern of a semiconductor device according to the present invention.
[도면부호의설명][Description of Drawing Reference]
21, 31 : 하부층 23 : 무기반사방지층21, 31: lower layer 23: inorganic antireflection layer
25 : 산화막 33 : 제1저유전상수 절연층25 oxide film 33 first low dielectric constant insulating layer
35 : 질화막 또는 SiCN37 : 제2저유전상수 절연층35 nitride film or SiCN37 second low dielectric constant insulating layer
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 미세패턴 형성방법은, 하부층상에 무기 반사방지층을 형성하는 단계; 상기 하부층상에 무기 반사방지층을 형성하는 단계; 상기 무기 반사방지층상에 질소가 함유되지 않은 산화막을 형성하는 단계; 상기 질소가 함유되지 않은 산화막상에 감광막패턴을 형성하는 단계; 및 상기 감광막패턴을 마스크로 패터닝공정을 수행하는 단계를 포함하여 구성되는것을 특징으로한다.Method for forming a fine pattern of a semiconductor device according to the present invention for achieving the above object, the step of forming an inorganic antireflection layer on the lower layer; Forming an inorganic antireflection layer on the lower layer; Forming an oxide film containing no nitrogen on the inorganic antireflection layer; Forming a photoresist pattern on the oxide film not containing nitrogen; And performing a patterning process using the photoresist pattern as a mask.
또한, 본 발명에 따른 반도체소자의 패턴 형성방법은, 하부층상에 제1 저유전 상수 절연막을 형성하는 단계; 상기 제1 저유전 상수 절연막상에 질소를 함유한 절연막을 형성하는 단계; 상기 질소를 함유한 절연막을 산소(O2) 플라즈마 처리하는 단계; 산소플라즈마 처리된 절연막상에 제2 유전상수 절연막을 형성하는 단계; 및 다마신공정을 진행하여 상기 제2유전상수 절연막과 질소를 함유한 절연막 및 제1저유전상수 절연막을 선택적으로 제거하여 배선콘택을 형성하는 단계;를 포함하여 구성되는 것을 특징으로한다.In addition, the method of forming a pattern of a semiconductor device according to the present invention comprises the steps of: forming a first low dielectric constant insulating film on the lower layer; Forming an insulating film containing nitrogen on the first low dielectric constant insulating film; Oxygen (O 2 ) plasma treatment of the insulating film containing nitrogen; Forming a second dielectric constant insulating film on the oxygen plasma treated insulating film; And performing a damascene process to selectively remove the second dielectric constant insulating film, the insulating film containing nitrogen, and the first low dielectric constant insulating film to form a wiring contact.
(실시예)(Example)
이하, 본 발명에 따른 반도체소자의 패턴 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a pattern of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따른 반도체소자의 패턴 형성방법에 있어서, 질소가 포함되지 않은 산화막을 이용하여 감광막패턴의 측면에 프팅(footing) 현상이 발생되지 않음을 설명하기 위한 단면도이다.FIG. 2 is a cross-sectional view illustrating a phenomenon in which a footing phenomenon is not generated on a side surface of a photoresist pattern using an oxide film not including nitrogen in the method of forming a pattern of a semiconductor device according to the present invention.
도 3은 본 발명에 따른 반도체소자의 패턴 형성방법에 있어서, 금속 다마신 공정에 적용한 경우에 질소가 포함되지 않은 산화막을 산소플라즈마 처리에 의해 형성한 경우에 나타나는 현상을 설명하기 위한 단면도이다.3 is a cross-sectional view for explaining a phenomenon which occurs when an oxide film containing no nitrogen is formed by oxygen plasma treatment in the method of forming a pattern of a semiconductor device according to the present invention.
본 발명에 따른 반도체소자의 패턴 형성방법은, 도 2에 도시된 바와같이, 먼저 폴리실리콘 또는 금속을 이용하여 배선층(21)을 증착한다.In the method for forming a pattern of a semiconductor device according to the present invention, as shown in FIG. 2, first, the wiring layer 21 is deposited using polysilicon or metal.
그다음, 상기 배선층(12)상에 무기(inorganic) 반사방지막(ARL; antireflective layer)(23)을 증착한후 하고, 상기 무기반사방지막(23)을 O2플라즈마처리를 실시하여 상기 무기반사방지막(23)표면에 질소가 포함되지 않은 산화막(25)을 형성한다. 이때, 상기 O2플라즈마 처리공정은, 사용장비에 따라 약간 다르기는 하지만 30 내지 2000 W 의 파워와, 10 내지 50000 sccm의 O2및, 1 내지 5000 sccm 의 He하에서 실시하는 것이 바람직하다.Next, an inorganic antireflective layer (ARL) 23 is deposited on the wiring layer 12, and the inorganic antireflective layer 23 is subjected to O 2 plasma treatment to perform the inorganic antireflective layer ( 23) An oxide film 25 containing no nitrogen is formed on the surface. At this time, the O 2 plasma treatment process, although slightly different depending on the equipment used, is preferably carried out under a power of 30 to 2000 W, 10 to 50000 sccm O 2 and 1 to 5000 sccm He.
또는, 상기 무기반사방지막(23)을 O2플라즈마처리하는 대신에 상기 무기반사방지막(23)표면에 TEOS(미도시)을 증착할 수도 있다.Alternatively, TEOS (not shown) may be deposited on the surface of the inorganic antireflection film 23 instead of performing O 2 plasma treatment on the inorganic antireflection film 23.
이어서, 상기 질소가 포함되지 않은 산화막(25)상에 감광물질을 도포하고, 이를 포토 및 식각공정을 통해 선택적으로 제거하여 감광막패턴(미도시)을 형성한다. 이때, 상기 감광막패턴(미도시)의 측벽에는 종래기술에서와 같은 프팅(footing) 현상이 나타나지 않게 되어 원하는 패턴의 정확한 CD 구현이 가능해진다.Subsequently, a photosensitive material is coated on the oxide film 25 that does not contain nitrogen, and is selectively removed through a photo and etching process to form a photoresist pattern (not shown). At this time, the sidewall of the photoresist pattern (not shown) does not appear a footing phenomenon as in the prior art, it is possible to implement a precise CD of the desired pattern.
한편, 본 발명의 다른 실시예로서, 도 3에 도시된 바와같이, 하부층(31)상에 저유전상수값을 갖는 제1절연층(33)을 증착한 후 상기 제1절연층(33)상에 SiCN 또는 질화막(35)을 증착한다.Meanwhile, as another embodiment of the present invention, as shown in FIG. 3, the first insulating layer 33 having the low dielectric constant value is deposited on the lower layer 31 and then on the first insulating layer 33. SiCN or nitride film 35 is deposited.
그다음, 상기 질화막(35)을 O2플라즈마처리를 실시한다. 이때, 상기 O2플라즈마 처리공정은, 사용장비에 따라 약간 다르기는 하지만 30 내지 2000 W 의 파워와, 10 내지 50000 sccm의 O2및, 1 내지 5000 sccm 의 He하에서 실시하는 것이 바람직하다. 또는, 상기 질화막(35)을 O2플라즈마처리하는 대신에 상기 무기반사방지막 (23)표면에 TEOS(미도시)을 증착할 수도 있다.Then, the nitride film 35 is subjected to O 2 plasma treatment. At this time, the O 2 plasma treatment process, although slightly different depending on the equipment used, is preferably carried out under a power of 30 to 2000 W, 10 to 50000 sccm O 2 and 1 to 5000 sccm He. Alternatively, instead of performing O 2 plasma treatment on the nitride film 35, TEOS (not shown) may be deposited on the surface of the inorganic antireflection film 23.
이어서, 도 4에 도시된 바와같이, 상기 산소플라즈마 처리된 질화막(35)상에 저유전 상수값을 갖는 제2절연층(37)을 증착한 후, 도면에는 도시하지 않았지만, 포토 및 식각을 통한 금속다마신 공정을 진행하여 금속다마신을 이용한 배선콘택을 형성한다. 이때, 상기 포토 및 식각공정전에 상기 제2절연층(37)상에 하드마스크용으로 산화막을 형성할 수도 있다.Subsequently, as shown in FIG. 4, after depositing the second insulating layer 37 having the low dielectric constant value on the oxygen plasma treated nitride film 35, although not shown in the drawing, the photo and etching process may be performed. The metal damascene process is performed to form a wiring contact using the metal damascene. In this case, an oxide film may be formed on the second insulating layer 37 for the hard mask before the photolithography and etching processes.
상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 패턴 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the pattern forming method of the semiconductor device according to the present invention has the following effects.
본 발명에 따른 반도체소자의 패턴 형성방법에 의하면, 반사방지막용 산화질화막표면에 질소가 포함되지 않은 산화막을 형성하므로써 패턴 형성을 위한 포토리소그라피 공정시에 강산의 감광물질과 전혀 반응하지 않게 되어 스컴 현상이 전혀 나타나지 않게 된다.According to the method for forming a pattern of a semiconductor device according to the present invention, by forming an oxide film containing no nitrogen on the surface of the oxynitride film for the antireflection film, it does not react at all with the photosensitive material of the strong acid during the photolithography process for pattern formation and thus the scum Will not appear at all.
또한, 금속, 예를들면 Cu 다마신 공정에서 질소와 카바이드(carbide)막의 질소성분에 의한 비어 포이지닝(poisoning) 현상이 발생하는 것을 억제시킬 수가 있다.In addition, in the metal, for example, Cu damascene process, it is possible to suppress the occurrence of the poisoning phenomenon caused by nitrogen and the nitrogen component of the carbide film.
따라서, 질소성분이 감광물질과 반응하여 발생하는 스컴현상을 억제시킬 수 있어 최적의 CD 구현을 가능하므로 반도체 수율 및 제품의 품질을 향상시킬 수 있다.Therefore, the scum phenomena generated by the reaction of the nitrogen component with the photosensitive material can be suppressed, so that the optimum CD can be realized, thereby improving semiconductor yield and product quality.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
Claims (7)
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