KR20030058070A - Apparatus for a signal search in Mobile Communication System and Method thereof - Google Patents

Abstract

PURPOSE: An apparatus and a method for searching signals in a mobile communication system are provided to quickly search pilot signals by processing input signals in parallel by a plurality of PN(Pseudo Noise) code despreaders. CONSTITUTION: The second PN shift register(46) receives and stores a plurality of PN codes outputted from the first PN shift register(42) in parallel. The first shift register(45) stores a plurality of I and Q component input signals outputted from an input buffer memory unit(44). The second shift register(46) receives and stores the I and Q component input signals outputted from the first shift register(45) in parallel, and receives and stores the I and Q component input signals outputted from the input buffer memory unit(44). A plurality of depreading devices(47) despread a plurality of the I and Q component input signals outputted from the second shift register(46) in parallel, using a plurality of the PN codes outputted from the second PN shift register(46). A coherent accumulator(48) accumulates a plurality of the despreaded I and Q component despreading signals. An energy adder(51) squares and adds the accumulated I and Q component accumulation signals, and calculates an energy value.

Description

Apparatus for a signal search in Mobile Communication System and Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mobile communication system, and more particularly, to a signal search apparatus and method for a mobile communication system for finding a PN offset of a multipath within a fast time by configuring a despreader in parallel.

A code-division multiple access (CDMA) mobile communication system basically consists of a mobile station (MS), a base station, a base station controller, and a mobile switching center.

The mobile communication signal modulated and transmitted from the mobile station is received by the base station, demodulated by the base station, and restored to the original signal.

The mobile communication signal includes a pilot signal for time synchronization and power control. The pilot signal is a signal transmitted to the base station by spreading with a unique PN code for each terminal user. The base station can demodulate the received signal by finding the respective time delays, ie, PN offsets, of the multipath components of the pilot signal to search for the pilot signal. In order to find the PN offset, all the offsets of the received signal may be despread using the PN signal, the energy of the despread signal is calculated, an average value is calculated, and a specific threshold value among the plurality of energy values is obtained. Select the PN offset of the path signal with a larger energy value. The device that performs this operation is called a "searcher."

1 is a block diagram of a conventional pilot signal searcher.

Referring to FIG. 1, the searcher includes a pseudo noise (PN) code generator 1, a despreader 2, a coherent accumulator 3, an energy calculator 5, and a noncoherent accumulator. (noncoherent accumulator) (6), sorter (sortor) (8).

Although not shown in the drawing, the input signal received through the antenna is separated into an I (in-phase) component and a Q (quadrature) component and input to the despreader 2. When the I and Q component input signals are input to the despreader 2, the PN code generator 1 generates a PN code and inputs it to the despreader 2. The PN code generator 1 generates PN codes corresponding to one PN offset.

Here, the PN code generates a code corresponding to each component since the input signal is separated into I and Q components. The I and Q component input signals are input to the despreader 2 by the number determined by the coherent accumulator 3. The despreader 2 despreads the input signal using the input PN codes, and inputs the output signal to the coherent accumulator 3. Here, the output signal is a signal output from the despreader (2) is output as a complex I component and Q component. That is, the despreader 2 despreads the first input signal using the PN code and despreads the next input signal using the PN code. This operation is repeated for the number of input signals determined by the coherent accumulator 3. The coherent accumulator 3 performs cumulative calculation for each of the input components I and Q. The accumulated and calculated respective components are squared and added to each component by the energy calculator 5 to calculate an energy value. Here, the energy value means an energy value for one PN offset. If the energy value for another PN offset is calculated, another PN codes are generated from the PN code generator 1 and another energy value is obtained by despreading and accumulating the input signals using the PN codes. This can be calculated. The energy value thus calculated is calculated by the noncoherent accumulator 6 as an average value of energy for a predetermined time. The noncoherent accumulator 6 may calculate an energy average value for each of a plurality of energy values. If this process is expressed by a formula, the energy value for one offset can be expressed as follows.

Where I (.) And Q (.) Are the input signals of I and Q components, respectively, and PN _i and PN _q are the PN codes of I and Q, respectively. An example of coherent accumulation N times is illustrated.

The sorter 8 sorts the calculated plurality of energy averages in descending order. When sorted based on the energy averages calculated for all possible PN offsets, a finger manager (not shown) assigns a finger to a PN offset corresponding to an energy average greater than this based on a specific energy average. do. The base station may control the finger to demodulate the corresponding data based on the assigned PN offset.

FIG. 2 shows a case where a coherent operation is 32 PN chips and a noncoherent operation is 4 for one offset. Referring to FIG. 2, 32 input signals are despread for each of the first 32 PN codes, and the output values are accumulated. Then, one energy value is output by calculating an energy value. The next 32 PN codes are despread with the next 32 input signals, respectively, and an energy value is output. The same procedure can be repeated two more times to calculate the respective energy values and calculate the average of these energies to calculate the energy values for one offset.

However, under the CDMA mobile communication system environment, the searcher of the base station needs to find the signals of various terminal users and all the time delays for each multipath, so that the time for finding the PN offset needs to be improved. There was a limit to searching the pilot signal.

Disclosure of Invention The present invention has been made to solve the above-mentioned problems of the prior art, and a signal search apparatus and method of a mobile communication system that enables fast pilot signal search by processing input signals in parallel using a plurality of PN code despreaders. It is to provide.

The signal search apparatus of the mobile communication system according to the present invention includes a plurality of second PN sequential storage means for receiving and storing in parallel a plurality of PN codes output from the first PN sequential storage means for sequentially storing a plurality of PN codes. First sequential storage means for storing a plurality of I and Q component input signals output from an input buffer memory section for outputting I and Q component input signals, and parallel I and Q component input signals output from the first sequential storage means A second sequential memory means for receiving and storing the I and Q component input signals outputted from the input buffer memory unit and a plurality of PN codes outputted from the second PN sequential memory means. A plurality of despreading means for despreading a plurality of I and Q component input signals output from the two sequential storage means in parallel, and the despreading of the plurality of despread I and Q components Square and addition to the coherent accumulator, and accumulating each of the accumulation of I and Q component signal for accumulating a signal comprises the energy calculating means for calculating an energy value.

The signal searching method of the present invention provides a first step of sequentially storing a plurality of PN codes in a first PN shift register, and a plurality of I and Q component input signals output from an input buffer memory unit. In the second step of sequentially storing in the first step, the plurality of PN codes are loaded in parallel from the first PN shift register into a second PN shift register according to a pilot search command signal, and a plurality of I and Q in the first shift register. A third step of loading component input signals in parallel to despread the plurality of I and Q component input signals in parallel using the plurality of PN codes for one PN offset; the plurality of despread I and Q A fourth step of accumulating component despread signals; and a fifth step of calculating an energy value by squaring and adding each of the accumulated I and Q component accumulated signals; And shifting the plurality of I and Q component input signals one by one from the input buffer memory unit to the second shift register, and then repeatedly performing the steps 3 to 5 to calculate energy values corresponding to the plurality of PN offsets. It comprises a step.

1 is a block diagram of a conventional pilot signal searcher.

2 is a diagram for explaining energy calculation timing for one conventional offset.

3 is a block diagram of a pilot signal searcher according to the first embodiment of the present invention;

4 is a detailed block diagram of the periphery of the despreading means shown in FIG. 3;

5 is a diagram for explaining energy calculation timing according to the first embodiment of the present invention;

6 is a block diagram of a pilot signal searcher according to a second embodiment of the present invention.

7 is a view for explaining a slot for time allocation according to the second embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

41: PN code generator 42,43; PN shift register

44: input buffer memory 45, 46: shift register

47: despreading means 48: coherent accumulator

49, 53: buffer 50: coherent accumulator gain control unit

51: Energy Adder 52: Noncoherent Accumulator

54: sorter

3 is a block diagram of a pilot signal search apparatus according to the prior art.

Referring to FIG. 3, the pilot signal search apparatus, that is, the searcher, includes a first shift register 32 for storing a plurality of PN codes and a second shift register 33 for storing a plurality of input signals. Despreading means 38 for despreading a plurality of input signals in parallel using a PN code, a coherent accumulator 34 for accumulating a plurality of output signals despread in parallel from the despreading means 38, and If the accumulated length from the coherent accumulator 34 exceeds a certain length, a buffer 35 for temporarily storing the predetermined length is included.

The searcher further includes a PN code generator 31, an energy calculator 36, a noncoherent accumulator 37 and an aligner 39. The PN code generator 31 arbitrarily generates a plurality of PN codes and provides them to the first shift register 32. The energy calculator 36 calculates an energy value by squaring and adding each component based on the respective components (I and Q components) accumulated and calculated from the coherent accumulator 34. Here, the energy value means an energy value for one PN offset. The noncoherent accumulator 37 calculates an energy average value for a predetermined time based on the energy value to calculate an energy average value. The sorter 39 sorts the calculated plurality of energy averages in descending order.

The first shift register 32, the second shift register 33, the despreading means 38 and the coherent accumulator 34 will be described in more detail with reference to FIG. 4.

4 shows a detailed block diagram of the peripheral devices of the despreading means 38 shown in FIG.

Referring to FIG. 4, the first shift register 32 and the second shift register 33 may store 32 pieces of data, respectively. That is, the first shift register 32 may store 32 two-bit PN codes while shifting the two-bit PN codes generated and input from the PN code generator 31 to the right in the order of input. The second shift register 33 may store 32 16-bit input signals while shifting the input signals inputted in 16 bits to the right in the order of input. Here, the two-bit PN code occupies one bit each for the I component and the Q component. In addition, the 16-bit input signal may occupy 8 bits each of the even path and the odd path, and each of the 8 bits may occupy 4 bits of the I component and the Q component. The even path and the odd path are signals sampled in half chip units before being input to the despreading means 38. It should be noted that the first shift register 32 and the second shift register 33 are not input to the despreading means 38 until 32 PN codes and 32 input signals are stored, respectively.

The despreading means 38 comprises a first despreader 62 for despreading an even path input signal and a second despreader 63 for despreading an odd path input signal. Here, the despreading means 38 includes the first despreader 62 and the second despreader 63, but the third despreader, the fourth despreader, It may further include more despreader. The first despreader 62 and the second despreader 63 may each include 32 despreaders. That is, as described above, 32 PN codes and 32 input signals are stored in the first shift register 32 and the second shift register 33. Therefore, since one despreader is required to despread one PN code and one input signal, 32 despreaders may be provided to despread an entire PN code and an input signal of 32 in total. The first despreader 62 and the second despreader 63 output 32 despread I and Q component despread signals, respectively, to be input to the coherent accumulator 34.

The coherent accumulator 34 receives 32 I and Q component despread signals which are despread in parallel at the same time, and accumulates them, respectively, and outputs I and Q component accumulated signals. Here, the coherent accumulator 34 is preferably an adder or means for adding. The adder means first adders 55a, 55b, 55c, and 55d. The I and Q component accumulating signals may be input to the energy calculator 36 to add a square of each component and output the energy value. In the case where there are more than 32 I and Q component despread signals output from the first despreader 62 or the second despreader 63, that is, multiples of 32, first 32 I and Q component inverses are applied. A spread signal is accumulated by the first adders 55a, 55b, 55c, 55d and then temporarily stored in the buffer 35 (first accumulated signal). The excess 32 I and Q component despread signals are then accumulated by the first adders 55a, 55b, 55c, 55d (second accumulate signal), and the second accumulate signal and the buffer 35 The first accumulation signal stored at may be accumulated and input to the energy calculator 36. Here, the first accumulated signal and the second accumulated signal are accumulated based on an I or Q component. Accordingly, when more than 32 I and Q component despread signals are output from the first despreader 62 or the second despreader 63, the coherent accumulator 34 may generate the first accumulated signal. And second adders 55e, 55f, 55g, and 55h for accumulating the second accumulated signals. Here, the first adders 55a, 55b, 55c, 55d and the second adders 55e, 55f, 55g, 55h may be configured in plural to accumulate even paths, odd paths, and I and Q components, respectively. Can be. In the first embodiment of the present invention, the first adders 55a, 55b, 55c, and 55d and the second adders 55e, 55f, 55g, and 55h are respectively configured to facilitate the understanding of the description. Four or more first and second adders may be included by various modifications.

Hereinafter, an operation of finding an optimal PN offset using the searcher configured as described above will be described.

Two pairs of sampled I and Q component input signals are input to the second shift register 33 in half-chip units, and a pair of I and Q PN codes output from the PN code generator 31 are connected to the first shift register ( 32). Here, the I and Q component input signals are two pairs of even path 8 bits and odd path 8 bits, and the I and Q PN codes are a pair of 2 bits. At this time, the input signal and the PN code are not operated until 32 are stored in each of the shift registers 32 and 33, and the input signal and the PN code are stored in each of the shift registers 32 and 33. In this case, each of the input signal and the PN code is input to the despreading means 38 to start the despreading operation. As described above, the despreading means 38 may include a first despreader 62 for despreading even paths and a second despreader 63 for despreading odd paths.

First, an 8-bit input signal of an even path preceded by a half chip is input to the first despreader 62. The 8-bit input signal of the odd path, which is after the half chip PN offset, is input to the second despreader 63. In addition, I and Q PN codes are input from the first shift register 32 to the first despreader 62 and the second despreader 63, respectively. In this case, the 8-bit input signal of the even path and the 8-bit input signal of the odd path are separated into 4-bit I and Q component input signals, respectively, so that the first despreader 62 and the second despreader 63 are respectively. Note that) is entered. As already mentioned, the first despreader 62 and the second despreader 63 may each include 32 despreaders. Accordingly, 32 PN codes and input signals stored in the first shift register 32 and the second shift register 33 are simultaneously input to the first despreader 62 and the second despreader 63 at one time. do.

The first despreader 62 and the second despreader 63 despread 32 I and Q component input signals using 32 PN codes.

For example, the PN code stored in the first shift register 32 is represented by a first PN code and a second PN code, and the I and Q input signals stored in the second shift register 33 are firstly displayed. Let it be expressed as an input signal, a second input signal. In addition, the first despreader 62 includes 32 despreaders, and denotes the first even path despreader and the second even path despreader. Then, the first despreader 62 may display the first even path despreader as the 32nd even path despreader. A 32nd code may be stored in the first shift register 32 from a first PN code, while a 32nd input signal may be stored in the second shift register 33 from a first input signal. Referring to the first despreader 62 for despreading the first even path, the first PN code and the first input signal are despread in the first even path despreader, and the second PN code and the second The input signal is despread in the second even path despreader, and finally, the 32nd PN code and the 32nd input signal may be despread in the 32nd even path despreader. The second despreader 63 may also despread the input signal of the odd path in the same process as the first despreader 62, and the detailed description thereof will be omitted below to avoid ambiguity or redundancy. 32 I and Q component despread signals, respectively, are output from the first even path despreader to the coherent accumulator 34 by the first despreader 62 including the 32nd even path despreader. do.

The 32 I and Q component despread signals are input to the plurality of first adders 55a, 55b, 55c, 55d and accumulated, respectively, and the accumulated two I and Q component accumulate signals are input to the energy calculator 36. The energy value is calculated. In this case, when the I and Q component despread signals are multiples of 32, the second adders 55e, 55f, 55g, and 55h and the buffer 35 may be used. For example, if the I and Q component despread signals are 64, denote them as a first despread signal and a second despread signal. The first despread signal and the second despread signal may include 32 I and Q component despread signals, respectively. Then, the first despread signal output from the first despreader 62 is first accumulated by the first adders 55a, 55b, 55c, and 55d, and the output first accumulated signal is stored in the buffer 35. Is temporarily stored in. Next, the second despread signal output from the first despreader 62 is accumulated by the first adders 55a, 55b, 55c, and 55d, and the output second accumulator signal is stored in the second adder ( 55e, 55f, 55g, 55h are added to the first accumulated signal stored in the buffer 35 and output. Referring to Figure 5 will be able to more easily understand this operation process. Accordingly, the searcher can coherent arithmetic operations on 32 or more I and Q component despread signals, thereby increasing the coherent computation length.

5 is a view for explaining the energy calculation timing according to the first embodiment of the present invention.

Referring to FIG. 5, there are a total of 64 PN codes, which can be separated into two. First, 32 PN codes (①) are coherent and stored in the buffer 35. Subsequently, the next 32 PN codes (2) can be coherently computed and added to this value and the value stored in the buffer 35 to be output. The output value is an energy value calculated by the energy calculator 36. As shown in FIG. 5, the energy calculation timing shows that the above operation is repeated for a plurality of PN offsets.

On the other hand, the I and Q component accumulation signals output from the coherent accumulator 34 are input to the energy calculator 36, and each of the I and Q component accumulation signals is squared and then summed to calculate an energy value. The calculated energy value is input to the noncoherent accumulator 37 and converted into an energy average value for a predetermined time.

Here, in order to find the optimal PN offset, various PN offsets must be tracked by changing the positions of received input signals and despreading using a PN code.

In order to implement this, the searcher maintains the first shift register 32 as it is and shifts the second shift register 33 to calculate an energy average value for all PN offsets that the input signals may have. Can be. That is, in order to calculate an energy average value for the next PN offset, the second shift register 33 is shifted one by one to the right, and then the second shift register 33 is obtained using the PN code of the first shift register 32. Based on the shifted input signal of), the energy value can be calculated through despreading and accumulation. Then, the average energy value for the PN offset may be calculated by shifting the second shift register 33 one by one to the right again. As a result, according to the searcher, an energy average value of all 32 PN offsets may be calculated. Here, the calculation of the energy average value for the 32 PN offsets is the same as the operation described above except that the second shift register 33 is shifted to the right one by one. Is omitted.

Meanwhile, the energy average values calculated for the 32 PN offsets may be aligned by the sorter 39. The finger may be allocated to a PN offset corresponding to an energy average value that is equal to or greater than a specific energy average value by a finger manager (not shown) based on the alignment of the energy average values.

6 is a block diagram of a pilot signal searcher according to a second embodiment of the present invention.

The pilot signal searcher according to the second embodiment of the present invention can perform 32 coherent operations for 64 offsets in units of 1/2 PN during 32 clocks. The PNs used as inputs of the despreading means 38 of the pilot signal searcher according to the embodiment and the shifter registers 32 and 33 for storing the input data are first and second PN shift registers in the second embodiment of the present invention. (42,43) and the first and second shift registers 45,46 are double buffered, and the input buffer memory 44 is used as the input data.

That is, by adding a pipeline operation of the PN and the input data to the pilot signal searcher according to the first embodiment of the present invention illustrated in FIG. 3, the amount of offsets searched per unit clock can be doubled.

49 denotes a buffer (coherent accumulator buffer), and stores the result of the calculation in the despreading means 47.

53 is a non-coherent accumulator buffer that stores previously calculated coherent accumulator results until the current coherent accumulator results.

FIG. 7 is a view for explaining a slot for time allocation according to the second embodiment of the present invention. Each slot includes 32 clocks.

In the second embodiment of the present invention, the PN code generator 41 receives a PN code to be used in slot 1 (actually despreading starts to occur) in advance in slot 0 by receiving a command to start searching before slot 0 shown in FIG. ) Is stored in the first PN shift register 42, and the first 32 data to be used in the slot 1 are read from the input buffer memory unit 44 and stored in the first shift register 45.

When the time of slot 1 is reached, the PN code stored in the first PN shift register 42 is loaded into the second PN shift register 43, and the data stored in the first shift register 45 is loaded into the second shift register. It loads to 46, and the despreading means 47 starts despreading.

Subsequently, data is read from the input buffer memory unit 44 and shifted in the second shift register 46 to search for another offset. At this time, the PN code stored in the second PN shift register 43 is maintained as it is.

The PN code generator 41 generates the PN code to be used for the slot 2 and stores it in the first PN shift register 42 while the despreading means 47 despreads the slot 1 time. ) Is read from the 16-bit data and stored in the first shift register 45.

In slot 2, the operation is the same as in slot 1.

For reference, in slot 1, the process of reading 32 data from the input buffer memory unit 44 should occur twice. That is, the first 32 data are despread by the despreading means 47 at the current slot 1 time, and the second 32 data are data to be despread at the slot 2 time.

To this end, the input buffer memory section 44 uses a memory having two read ports, or arranges memory so that two data can be read in one clock, and another buffer (not shown) for data for the current slot. Put it.

Next, by repeating the above similar process in successive slots, a pipeline structure in which the despreading means 47 of the searcher can be operated continuously without interruption can be made, and thus the number of PN offsets searched per unit clock is determined. It can be doubled than in the embodiment.

Such a signal search apparatus and method of the present invention has the following effects.

First, by processing the input signals in parallel using a plurality of PN despreaders, the pilot signals can be searched at high speed.

Second, the PN offset and the coherent operation length can be increased by performing more than 32 coherent operations using the adder and the buffer.

Third, the performance of the searcher can be improved by allowing the despreading means to operate continuously.

Claims (2)

Second PN sequential storage means for receiving and storing in parallel a plurality of PN codes output from the first PN sequential storage means for sequentially storing a plurality of PN codes; First sequential storage means for storing a plurality of I and Q component input signals output from an input buffer memory section for outputting a plurality of I and Q component input signals; Second sequential storage means for receiving and storing the I and Q component input signals output from the first sequential storage means in parallel, and for receiving and storing the I and Q component input signals output from the input buffer memory section; A plurality of despreading means for despreading in parallel a plurality of I and Q component input signals outputted from said second sequential storage means using a plurality of PN codes outputted from said second PN sequential storage means; A coherent accumulator for accumulating the plurality of despread I and Q component despread signals; And And energy calculation means for calculating an energy value by squaring and adding each of the accumulated I and Q component accumulated signals. A first step of sequentially storing a plurality of PN codes in a first PN shift register; A second step of sequentially storing a plurality of I and Q component input signals output from the input buffer memory unit in a first shift register; Load the plurality of PN codes in parallel from the first PN shift register into a second PN shift register according to a pilot search command signal, and load a plurality of I and Q component input signals in parallel from the first shift register; Despreading the plurality of I and Q component input signals in parallel using the plurality of PN codes for a PN offset of; Accumulating the plurality of despread I and Q component despread signals; A fifth step of calculating an energy value by squaring and adding each of the accumulated I and Q component accumulation signals; And Shifting the plurality of I and Q component input signals one by one from the input buffer memory unit to the second shift register, and then repeatedly performing the steps 3 to 5 to calculate energy values corresponding to the plurality of PN offsets. Pilot signal search method of a wireless communication system characterized in that it comprises a step.