KR100380770B1 - Spread spectrum receiver - Google Patents

Abstract

A spread spectrum receiver having a spread code generator with reduced hardware and memory capacity is disclosed. Delay values for each path of a predetermined number of multipath channels are detected. The ring buffer is provided to sequentially store spreading codes by a predetermined length with sequential write addresses. This ring buffer is controlled such that a spreading code is read from the ring buffer with a sequential read address determined by subtracting the delay value for each path from the sequential write address.

Description

Spread Spectrum Receiver {SPREAD SPECTRUM RECEIVER}

FIELD OF THE INVENTION The present invention relates to receivers for use in spread spectrum communication systems, and more particularly to spread code generation techniques for spread spectrum receivers under multipath conditions.

Several spreading code generation techniques have been proposed that are designed to generate spreading codes for each of the multiple transmission paths.

In Japanese Patent Application No. 9-55715 (first publication), a plurality of demodulators having a pseudo noise (PN) code generator, each spread spectrum receiver including a read-only memory (ROM) storing PN code data. Is provided. The read address of the ROM (hereinafter referred to as ROM address) is latched and monitored by the controller. This controller generates a relative PN address from the latched ROM address. This correlated PN address is added to the base address generated by the address counter and the result is used as the ROM address to read the PN sequence from the ROM.

In Japanese Patent Publication No. 2803661 (second publication), the spreading code for each channel is precomputed and written to the short code memory provided for each channel. The spreading code for a channel is read from the corresponding short code memory and used to spread the input signal of that channel.

In Japanese Patent Application No. 9-36778 (third publication), a spread spectrum receiver is provided with a spreading code generator comprising an address generator, an address counter and a memory. The address generator generates a synchronization address by adding correlation path information and a base index received from the synchronization acquisition unit. The address counter is an N scale counter for counting from 0 to N-1 in accordance with the chip clock. The memory stores a spreading code that will be used to despread the input signal with a capacity for a predetermined length. Only upon receiving a path switch request from the address generator, the address counter loads the sync address from the address generator and outputs it as a read address in memory. This allows the spreading code to start from a sync address to be read from memory. Since the correlation path information provides a correlation phase shift from the base index, a spreading code with the correct phase can be obtained.

However, since the conventional spreading code generators disclosed in the first and second publications require a plurality of PN code memories, the amount of hardware is increased.

The remaining conventional spreading code generator disclosed in the third publication can generate a phase adjusted spreading code using only one memory that stores a spreading code of a predetermined length. However, there is a need to increase the length of the periodic spreading code to identify multiple base stations in a spread spectrum communication system. As a result, the capacity of the PN code memory is increased. Moreover, when used to receive a plurality of transmission paths, a plurality of memory blocks corresponding to each of the transmission paths are required, thereby increasing the amount of hardware.

It is an object of the present invention to provide a spread spectrum receiver having a spread code generator with a reduced amount of hardware and memory capacity.

According to a feature of the invention, a spread spectrum receiver comprises: a detector for detecting a delay value for each of a predetermined number of paths in a multipath channel; A spreading code generator for generating a spreading code; A ring buffer for sequentially storing the spreading code by a predetermined length; And a read controller for reading the spreading code from the ring buffer at a position determined according to the delay value for each of the paths.

According to another feature of the present invention, a spread spectrum receiver for receiving N (N is an integer) multipath signals in a multipath channel includes: a detector for detecting N delay values for N paths; A spreading code generator for generating a spreading code used to despread the received spread spectrum signal; A memory for storing the spreading code by a predetermined length; And a controller for controlling the memory such that the spreading code is written to a sequential write address and read into a sequential read address resulting from the sequential write address in accordance with a delay value for each of the N paths.

The N delay values can be selected sequentially while spreading codes are written to the sequential write addresses. The controller may include a subtractor for generating a sequential read address by subtracting the selected delay value from the sequential write address. The memory may have a data write port and a data read port separately.

The N delay values may be sequentially selected after the spreading code is written to the sequential write addresses. The memory may have a single data port shared between read and write operations. The controller preferably controls the read and write operations of the memory in a time division manner.

The controller may be configured to write the spreading code to a sequential write address in N time slots, wherein the N time slots are sequential read addresses generated from the sequential write addresses according to delay values for each of the N paths. It may be a time division controller which controls to be divided into-sequentially used to read the spreading code from the memory.

The controller writes the spreading code into the memory with N + 1 time slots in which a sequential write address is maintained, wherein the N + 1 time slots have a sequential write address, and delay values for each of the N paths. May be divided into a sequential read address generated from the sequential write address, which is sequentially used to read the spreading code from the memory.

As described above, according to the present invention, a spreading code having a corresponding path delay is read from the memory while writing to the memory. Thus, a spreading code with any delay time can be generated even in the case of a spreading code with a long duration without a quantitative increase in hardware.

Moreover, since spreading codes with corresponding path delays are read from the memory in a time division manner, only one memory is needed to generate a plurality of path delayed spreading codes, thereby reducing the amount of hardware.

1 is a block diagram illustrating a baseband processor of a spread spectrum receiver according to the present invention.

2 is a block diagram illustrating a path delayed spread code generator of a spread spectrum receiver according to a first embodiment of the present invention;

3A to 3D are timing diagrams for explaining the operation of the path delayed spread code generator in the first embodiment.

4 is a block diagram illustrating a path delayed spread code generator of a spread spectrum receiver according to a second embodiment of the present invention.

5A to 5E are timing diagrams for explaining the operation of the path delayed spreading code generator in the second embodiment.

Description of the main parts of the drawing

10: correlator

11: route finder

12: spreading code generator

13: Path Delayed Spread Code Generator

16: combiner

17: demodulator

Referring to FIG. 1, a spread spectrum receiver according to the present invention includes a baseband having a despreading and demodulation function for generating demodulated data from a wireless system (not shown) and spread spectrum data received from and received from the wireless system. It includes a processing unit. The wireless system receives the radio spread spectrum signal and converts it from radio frequency to baseband frequency. This baseband frequency signal is output to the baseband processor as received data.

The baseband processor includes a correlator 10, a path finder 11, a spread code generator 12, a path delayed spread code generator 13, and a correlation of N correlators 14.0 to 14. (N-1). A base 15, a synthesizer 16 and a demodulator 17.

The correlator 10 inputs the data received from the wireless system and the spreading code SC from the spreading code generator 12 and multiplies the received data by the spreading code SC to generate a correlation. By shifting the spreading code in time on the received data, the correlation value for each delay time is obtained and output to the path finder 11.

The path searcher 11 detects a delay time at which a strong correlation occurs from the correlation value received from the correlator 10 and uses the N delay values D ₀ -D _N-1 as delay information to the path delayed spreading code generator 13. Output The delay information of each path indicates the delay time that the corresponding radio signal path arrives.

The path delayed spreading code generator 13 generates _N path delayed spreading codes SC ₀ -SC _N-1 by delaying the spreading code SC according to the delay information. Correlators 14.0 to 14. (N-1) multiply the received data by the N path delayed spreading codes SC ₀ -SC _N-1 to generate N correlations. The N correlations are combined by synthesizer 16 to produce despread data. The despread data is demodulated by demodulator 17 into demodulated data.

Spread code generation

2, the path delayed spread code generator 13 according to the first embodiment of the present invention includes a selector 21, a subtractor 22, an M bit counter 23, a memory (ring buffer) 24, Converter 25 and memory controller 26.

The selector 21 inputs delay values D ₀ to D _N-1 for the _N multipaths # 0 to # (N-1) from the path delayed spreading code generator 13 and according to the selection timing signal, delays D _{0. -Select one} of D _N-1 . D _SEL selecting the delay time is output to the subtractor 22 for subtracting the selected delay value D _SEL from the counter value C of the M-bit counter 23. The output C-D _SEL of the subtractor 22 is used as the read address of the memory 24 which functions as a ring buffer.

The M bit counter 23 is an address counter that counts according to a predetermined clock and generates a counter value C as a write address of the ring buffer 24. The spreading code generated by the spreading code generator 12 is written at the position indicated by the counter value C in the ring buffer 24. In addition, the counter value C is used to generate the read address described above. The number of bits M is determined according to the maximum allowable delay difference among the multipaths # 0 to # (N-1). For example, to allow path delays of up to 256 chips, 256 (= 2 ⁸ ) addresses are needed. Thus, in this case, the M bit counter 23 is an 8 bit counter.

The spreading code SC of the spreading code generator 12 is successively written onto the ring buffer 24 in accordance with the write address C. At the same time, the read address C-D _SEL is supplied to the ring buffer 24. Therefore, the write spreading code SC is read continuously according to the read address C-D _SEL . Since the read address is generated by subtracting the selected delay value D _SEL from the counter value C, the N path delayed spreading codes for the multipaths # 0 to # (N-1) are read sequentially from the ring buffer 24. In other words, the ring buffer 24 is controlled so that the spreading code SC is written while reading the delay which varies according to the selected delay value.

Converter 25 includes a set of N flip-flop circuits, each corresponding to multipath # 0 to # (N-1). Converter 25 latches the N path delayed spreading codes sequentially read from ring buffer 24 in accordance with the latch timing signal, and each of the multiple paths # 0 through # (N-1) according to the output timing signal. Output N path delayed spreading codes simultaneously.

The memory controller 26 controls the write and read timing of the ring buffer 24. In this embodiment, the write timing of the ring buffer 24 is synchronized with the predetermined clock and output timing signal of the M bit counter 23. The read timing of the ring buffer 24 is synchronized with the selection timing signal and the latch timing signal. The frequency of the read timing signal is N times as high as the frequency of the write timing signal. In other words, the time interval for the write operation is divided into N time slots, each of which is used for each read operation of the N path delayed spreading codes for multipath # 0 to # (N-1).

As shown in Figs. 3A to 3B, the M bit counters 23 increase, that is, the counter value C changes: 0, 1, 2, 3, 4, 5, 6, 7, 8, It is assumed that it changes to ... and each delay value D ₀ -D _N-1 is set to 2, 3, ..., 1.

Referring to Fig. 3C, when the write address C = 5, the spreading code SC is written to the address 5 of the ring buffer 24. At the same time, the delay value D ₀ = 2 is selected by the selector 21 in accordance with the selection timing signal and the delay value D ₀ = 2 is subtracted from the write address C = 5 by the subtractor 22. Therefore, the output value 3 (= 5-2) of the subtractor 22 is output to the ring buffer 24 as a read address. Thus, a spreading code having a delay corresponding to the selected delay value is read from the ring buffer 24. Similarly, when the delay value D ₁ = 3 is selected by the selector 21 according to the selection timing signal, the delay value D ₁ = 3 is subtracted by the subtractor 22 from the write address C = 5 and the subtractor 22 is reduced. An output value of 2 (= 5-3) is output to the ring buffer 24 as a read address. Same as other delay values D ₂ -D _N-1 .

In this manner, spreading codes SC ₀ -SC _N-1 for N paths # 0 through # (N-1) are sequentially from ring buffer 24 with read addresses 3, 2, 1, ... 4 Although read, the spreading code SC is written to the ring buffer 24 at address 5.

Referring to FIG. 3D, the spreading codes SC ₀ -SC _N-1 are sequentially read out to read addresses 3, 2, 1, ... 4 and the flip-flop circuit of the converter 25 in accordance with the latch timing signal. When latched in, the latched spreading codes SC ₀ -SC _N-1 are simultaneously output to the correlator section 15 in accordance with an output timing signal delayed by one clock of the M-bit counter 23.

In the manner described above, spreading codes SC ₀ -SC _N-1 for N paths # 0-# (N-1) are sequentially read from the ring buffer 24 with a read address corresponding to delay information while spreading. Code SC is written to the ring buffer 24 at each write address. As described above, the ring buffer 24 is controlled by the memory controller 26 so that the N spreading codes are read for the time required to write data to the ring buffer 24 at one address. When spreading codes SC ₀ -SC _N-1 are sequentially read to the read address and latched in converter 25 according to the latch timing signal, the latched spreading codes SC ₀ -SC _N-1 correlate according to the output timing signal. It is output simultaneously to the base 15.

Since data is read from the ring buffer 24 while data is written to the ring buffer 24, the maximum allowable path delay time is determined according to the size of the ring buffer 24. Thus, when a multipath signal with a larger delay difference is received, it is necessary to create a ring buffer 24 with a larger capacity to overcome the multipath signal. However, since the spreading code is written to the ring buffer 24 while the generated spreading code is read from the ring buffer 24, the spreading code having a random delay time can be used for spreading code having a long duration without quantitative increase in hardware. Even if it can be easily generated.

Referring to FIG. 4, the path delayed spreading code generator 13 according to the second embodiment of the present invention has a first type as shown in FIG. 2 except for the number of ports of the ring buffer 24 and the memory controller 31. It has the same circuit configuration as in the embodiment. Here, circuit blocks similar to those already described with reference to FIG. 2 are denoted by the same reference numerals and detailed description thereof will be omitted.

In the second embodiment, the ring buffer 24 is a memory having a single address port and a single data port. The memory controller 31 controls the ring buffer 24 so that write and read operations are performed in accordance with the time division structure.

Since (A), (B) and (E) of FIG. 5 are the same as (A), (B) and (D) of FIG. 3, respectively, description thereof will be omitted. The control operation of the memory controller 31 is performed as shown in Figs. 5C and 5D. Details of this will be described below.

Referring to Fig. 5D, when the write address C = 5, the memory controller 31 switches the ring buffer to the address 5 during the write period in which the spread code SC is 1 / (N + 1) period of the write timing. The strobe signal is controlled to be written to (24). The strobe signal is then changed to read only. The delay value D ₀ = 2 is selected by the selector 21 according to the selection timing signal and the delay value D ₀ = 2 is subtracted from the write address C = 5 by the subtractor 22. Therefore, the output value 3 (= 5-2) of the subtractor 22 is output to the ring buffer 24 as a read address. Thus, a spreading code having a delay corresponding to the selected delay value is read from the ring buffer 24. Similarly, when the delay value D ₁ = 3 is selected by the selector 21 according to the selection timing signal, the delay value D ₁ = 3 is subtracted by the subtractor 22 from the write address C = 5 and the subtractor 22 is reduced. An output value of 2 (= 5-2) is output to the ring buffer 24 as a read address. This is equal to the remaining delay values D ₂ -D _N-1 .

In this way, spreading codes SC ₀ -SC _N-1 for N paths # 0 through # (N-1) are read sequentially from the ring buffer 24 with read addresses 3, 2, 1, ... 4 do. The spreading codes SC ₀ -SC _N-1 are sequentially latched as described above and output simultaneously by the converter 25. In other words, the time interval during which the write address is maintained is divided into N + 1 time slots, and the writing operation of spreading code SC for multipath # 0 to # (N-1) and the reading of N path delayed spreading codes Each is used for operation.

According to the present invention, it is possible to provide a spread spectrum receiver having a spread code generator with reduced hardware and memory capacity.

Claims (16)

In a spread spectrum receiver, A detector for detecting a delay value for each of a predetermined number of paths of the multipath channel; A spreading code generator for generating a spreading code; A ring buffer for sequentially storing the spreading code by a predetermined length; And A read controller for reading the spreading code from the ring buffer at a position determined according to the delay value for each of the paths Spread spectrum receiver comprising a. A spread spectrum receiver for receiving N (N is an integer) multipath signals of a multipath channel, A detector for detecting N delay values for the N paths; A spreading code generator for generating a spreading code used to despread the received spread spectrum signal; A memory for storing the spreading code by a predetermined length; And A controller for controlling the memory such that the spreading code is written to a sequential write address and read from a sequential read address resulting from the sequential write address according to a delay value for each of the N paths A spread spectrum receiver comprising a. 3. The spread spectrum receiver of claim 2, wherein the controller sequentially selects the N delay values while the spreading code is written to the sequential write addresses. 4. The spread spectrum receiver of claim 3, wherein the controller comprises a subtractor for generating the sequential read address by subtracting a selected delay value from the sequential write address. 4. The apparatus of claim 3, wherein the controller sequentially writes the spreading code according to a first timing signal and sequentially reads the written spreading code according to a second timing signal, wherein the frequency of the second timing signal is determined by the first timing signal. A spread spectrum receiver, characterized in that it is N times higher than the frequency of one timing signal. 6. The spread spectrum receiver of claim 5, wherein the memory includes a data write port and a data read port separately. 3. The spread spectrum receiver of claim 2, wherein the controller sequentially selects the N delay values after the spread code is written to the sequential write addresses. 8. The spread spectrum receiver of claim 7, wherein the controller comprises a subtractor for generating the sequential read address by subtracting the selected delay value from the sequential write address. 8. The spread spectrum receiver of claim 7, wherein the memory has a single data port shared between read and write operations. 10. The spread spectrum receiver of claim 9, wherein the controller controls the read and write operations of the memory in a time division manner. 3. The memory device of claim 2, further comprising a storage unit configured to store the N path delayed spreading codes sequentially read from the memory according to the N delay values, and to generate the N path delayed spreading codes in parallel. Spread spectrum receivers. 12. The spread spectrum receiver of claim 11, further comprising N correlators for receiving the N path delayed spreading codes from the storage unit in parallel to generate N correlation values for the N paths. . 3. The apparatus of claim 2, wherein the controller is a time division controller for controlling a period in which the spreading code is written to a sequential write address is divided into N time slots, wherein the N time slots are delayed for each of the N paths. A sequential read address generated from said sequential write address in accordance with a value, said spread spectrum receiver being used sequentially to read said spread code from said memory. 3. The apparatus of claim 2, wherein the controller is a time division controller that controls a period in which sequential write addresses are maintained is divided into N + 1 time slots, wherein the N + 1 time slots are stored in the memory at sequential write addresses. A spread spectrum receiver characterized by writing a spreading code and sequentially reading the spreading code from the memory at sequential read addresses resulting from the sequential write addresses according to delay values for each of the N paths . A method for generating a spreading code in a spread spectrum receiver, the method comprising: Detecting a delay value for each of a predetermined number of paths of the multipath channel; Generating a spreading code; Sequentially storing the spreading code in a ring buffer by a predetermined length; And Reading the spreading code from the ring buffer at a location determined according to the delay value for each of the paths Spreading code generation method comprising a. A spread spectrum receiver for receiving N (N is an integer) multipath signals of a multipath channel, the method for generating N spread codes for the multipath signal, Detecting N delay values for the N paths; Generating a spreading code used to despread the received spread spectrum signal; Storing the spreading code in a memory for a predetermined length; Writing the spreading code to the memory at a sequential write address; And Reading a path delayed spreading code from the memory at a sequential read address generated from the sequential write address according to a delay value for each of the N paths Spreading code generation method comprising a.