KR20030057228A - A Liquid crystal display device method for fabricating the same - Google Patents

Abstract

PURPOSE: A method for manufacturing an array panel for an LCD(Liquid Crystal Display) device is provided to reduce the process time by defining a second domain in a single pixel through one exposure process and to produce an LCD device of a wide viewing angle and high quality of an image by preventing the occurrence of disclination. CONSTITUTION: An alignment film(163) is formed by coating an alignment material of which alignment characteristic is changed by the ultraviolet rays on the front face of a substrate(100) having a transparent pixel electrode. The substrate with the alignment film is defined as A regions and B regions. The regions is the half of a pixel. A mask(170) having a transmission part(C) and a cut-off part(D) is placed below the array panel. Ultraviolet rays(L1) are irradiated from the upper portion of the array panel to determine the alignment characteristic of the alignment film. The region corresponding to the transmission part of the mask is defined as a first domain having first alignment characteristic, while the region corresponding to the cut-off part of the mask is defined as a second domain having second alignment characteristic.

Description

A liquid crystal display device method for fabricating the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a liquid crystal display device that realizes a wide viewing angle.

Hereinafter, a configuration of an array substrate for a liquid crystal display device will be described with reference to FIG. 1.

1 is an enlarged plan view schematically showing one pixel included in an array substrate for a liquid crystal display device.

As illustrated, the thin film transistor T, which is a switching element, is positioned in a matrix type on the substrate 10, and the gate wiring 25 and the data wiring 45 intersecting the thin film transistor T are formed. do.

The thin film transistor T includes a gate electrode 23, a source electrode 41, a drain electrode 43, and a semiconductor layer 36 formed on the gate electrode.

An area defined by the intersection of the gate line 25 and the data line 45 is defined as a pixel area P. FIG.

Hereinafter, the cross-sectional structure of the above-described planar structure will be described with reference to FIG. 2.

FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1.

As shown in the drawing, the gate electrode 23 and the gate wiring 25 are formed on the substrate 10.

The gate insulating film 29 serving as the first insulating film is formed on the entire surface of the substrate 21 on which the gate wiring 25 and the like are formed.

An active layer 36 and an ohmic contact layer 37 are formed in an island form on the gate insulating layer 29 on the gate electrode 23.

A source electrode 41 and a drain electrode 43 and a data line 45 connected to the source electrode 41 are formed on the active layer 36.

A passivation layer 51, which is a second insulating layer, is formed on the data line 45 and the source and drain electrodes 41 and 43, and is exposed through the drain contact hole 53 formed by patterning the passivation layer 51. The transparent pixel electrode 61 in contact with the drain electrode 45 is formed in contact with each other.

An alignment layer 63 is formed on the entire surface of the substrate 10 on which the transparent pixel electrode 61 is formed.

When the liquid crystal panel including the array substrate as described above is used as a desktop monitor, the viewing angle should be wide.

In the method of widening the viewing angle, the field of view is written using a multi-domain technique or a phase difference film in which the ring pixels are divided into various regions so that the orientation of liquid crystal molecules is changed in each region so that the characteristics of the pixels become the average of the characteristics of the various regions contained therein. Phase compensation technology to reduce the phase difference to the change of direction, the horizontal electric field by applying the horizontal electric field so that the director of the liquid crystal is twisted in a plane parallel to the alignment layer, the vertical alignment mode using the vertical alignment film and liquid crystal with negative dielectric anisotropy, etc. There is this.

Hereinafter, a method for realizing a wide viewing angle by dividing the pixel area into various areas will be described with reference to FIGS. 3 and 4.

3 and 4 illustrate an exposure method for implementing two domains on a single pixel of an array substrate.

As shown in FIG. 3, in order to define a plurality of pixels P formed in the array substrate 10 as two domains, an exposure method using ultraviolet rays is used.

That is, the mask 70 including the transmission part C and the shielding part D is positioned on the array substrate 10 having the cross-sectional structure described above.

In this case, the transmission part C is positioned to correspond to the area A of the array substrate 10, and the shielding part D of the mask 70 is positioned to correspond to the area B of the array substrate 10.

When the ultraviolet ray is irradiated to the mask 70, the alignment characteristic of the alignment layer 63 corresponding to the A region of the pixel is changed.

Subsequently, as shown in FIG. 4, the transmissive portion C of the mask 70 is positioned to correspond to the B region of the pixel, and the shielding portion D corresponds to the A region of the pixel so that the alignment characteristic is already obtained. This changed part is shielded.

When the second ultraviolet rays are irradiated on the mask 70, the alignment characteristics of the alignment layer may be changed by the influence of the ultraviolet rays on the A region and the B region.

Through the sequential irradiation process as described above, two domains may be defined in one pixel.

However, the sequential irradiation method as described above has a disadvantage in that it takes a long process time because different regions are defined in one pixel through two ultraviolet irradiation processes.

In addition, a region having an undesired third alignment characteristic may occur due to misalignment of the substrate and the mask during a plurality of exposure processes, and the light leakage may occur because the liquid crystal is abnormally aligned in the region.

SUMMARY OF THE INVENTION The present invention has been made for the purpose of solving the above problems, and proposes a method of forming a single pixel into two domains in one UV irradiation process.

1 is a plan view schematically showing one pixel of a typical array substrate for a liquid crystal display device;

FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1;

3 and 4 are plan views showing a domain forming process according to a conventional exposure method,

5 is a view showing a domain forming process according to the exposure method of the present invention,

6A through 6E are cross-sectional views taken along the line II-II ′ of FIG. 1 and shown in the process sequence of the present invention.

<Description of the symbols for the main parts of the drawings>

100: substrate 123: gate electrode

125: gate wiring 129: gate insulating film

136: active layer 137: ohmic contact layer

141: source electrode 143: drain electrode

145: data wiring 151: protective film

161 transparent pixel electrode 163 alignment layer

170: mask

A method of forming a two domain according to the present invention for achieving the above object comprises the steps of forming an alignment film on a substrate; Defining the alignment layer as an A region and a B region; Placing a mask comprising a transmissive portion and a reflecting portion under the substrate; Making the transmissive part of the mask correspond to the area A and the reflecting part to correspond to the area B; Irradiating ultraviolet rays from the upper portion of the substrate, wherein the region A has a first alignment characteristic, and the alignment layer corresponding to the region B has a second alignment characteristic.

The alignment layer has different alignment characteristics due to ultraviolet rays.

According to an aspect of the present invention, there is provided a method of manufacturing a multi-domain array substrate, the method including forming a gate electrode and a gate wiring on a substrate; Forming a gate insulating film as a first insulating film on an entire surface of the substrate on which the gate electrode and the gate wiring are formed; Forming an active layer and an ohmic contact layer on the gate insulating layer on the gate electrode; Forming a source electrode and a drain electrode in contact with the ohmic contact layer, and a data line connected to the source electrode; Forming a protective film, which is a second insulating film, on the entire surface of the substrate on which the source and drain electrodes are formed; Patterning the second passivation layer to form a drain contact hole exposing a portion of the drain electrode; Forming a transparent pixel electrode in contact with the drain electrode; Forming an alignment layer by coating an alignment material on the entire surface of the substrate on which the transparent pixel electrode is formed; Defining a plurality of pixels formed on the substrate and having an alignment layer formed in regions A and B; Placing a mask comprising a transmissive portion and a reflective portion under the substrate on which the alignment layer is formed; Making the transmissive part of the mask correspond to the area A and the reflecting part of the mask corresponding to the area B; Irradiating ultraviolet rays from the upper portion of the substrate to define a single pixel as two domains having different orientation characteristics.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

The present invention is characterized by forming two domains in a single pixel in one exposure process.

5 is a plan view illustrating a domain forming process according to an exposure method of the present invention.

As illustrated, the data line 145 defining the pixel region P intersecting the gate line 125, the gate line 125, and the thin film transistor T positioned at the intersection of the two lines 125 and 145. ), A pixel electrode 161 formed in the pixel region P, and a mask 170 is positioned below the array substrate 100 coated with an alignment layer (not shown).

The mask 170 includes a transmissive portion C and a shielding portion D, and the transmissive portion C is positioned to correspond to an area A of the substrate 100, and the shielding portion D is disposed on the B portion of the substrate 100. Position it to correspond to the area.

When the ultraviolet light L1 is irradiated to the upper portion of the array substrate 100 on which the mask 170 is located, the characteristics of the alignment layer 163 corresponding to the region A and the region B of the array substrate are changed.

The light irradiated to the area A passes through the transmission portion C of the mask 170 as it is, but the light incident to the area B of the substrate 100 is reflected by the lower shielding portion D of the lower portion and is returned to the area B again. Is investigated.

Since the light is irradiated twice in the alignment layer 163 corresponding to the region B, the characteristic of the alignment layer is changed first, and the alignment characteristic of the alignment layer is changed again.

Therefore, since the alignment characteristics of the alignment layers corresponding to the region A and the region B are different, the result of defining two domains in a single pixel can be obtained.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to the present invention including the above-described multi-domain forming method will be described with reference to FIGS. 6A and 6D.

6A to 6E are cross-sectional views illustrating the process sequence of the present invention cut along the line II-II ′ of FIG. 1 (the same configuration is indicated by adding 100 since the top views are the same).

First, as shown in FIG. 6A, a gate electrode 123 and a gate wiring 125 are formed on the substrate 100.

In this case, the gate electrode 123 and the gate wiring 125 may be a single layer using one selected from aluminum (Al), aluminum alloy (mainly AlNd), molybdenum (Mo), chromium (Cr), and tungsten (W). Two metals are laminated to form a double film.

Usually, when the gate electrode, the gate wiring, etc. are formed as a double film, aluminum is used. That is, the first layer is made of aluminum and the second layer is formed using molybdenum (Mo) or chromium (Cr).

The reason why the gate wirings are formed of a double metal layer is that molybdenum having high corrosion resistance because the aluminum has a small resistance but chemically corrosion resistance and causes a wiring defect problem due to hillock formation in a subsequent high temperature process. Mo) or chromium (Cr) is laminated.

Subsequently, a gate insulating film 129 is formed on the entire surface of the substrate on which the gate electrode and the gate wiring are formed.

The gate blocking film 129 forms an inorganic insulating material including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) selected from the group.

An active layer 136 and an ohmic contact layer 137 are formed on the gate insulating layer on the gate electrode.

As shown in FIG. 6B, a source electrode 141 and a drain electrode 143 contacting the ohmic contact layer 137 and a data line 145 connected to the source electrode 141 are formed.

The source electrode 141 and the drain electrode 143 are spaced apart from each other, and the active layer 136 is exposed by removing the ohmic contact layer 137 exposed between the spaced apart portions.

The source electrode and the drain electrode may be patterned by depositing one selected from a group of conductive metals including aluminum (Al), aluminum alloy (mainly AlNd), molybdenum (Mo), chromium (Cr), and tungsten (W). Form.

Next, as shown in FIG. 6C, a group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 100 on which the source and drain electrodes 141 and 143 are formed. The protective layer 151 is formed by depositing the selected one, or in some cases applying one selected from the group of organic insulating materials including benzocyclobutene (BCB) and acrylic resin.

Subsequently, the passivation layer 151 is patterned to form a drain contact hole 153 exposing a part of the drain electrode 143.

As shown in FIG. 6D, one selected from the group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZO) is formed on the entire surface of the substrate 100 on which the passivation layer 151 is formed. Deposition is performed to form the transparent pixel electrode 161 in contact with the drain electrode 143.

Next, as shown in FIG. 6E, the alignment layer 163 is formed by coating an alignment material whose alignment characteristics are changed by ultraviolet rays, such as polyimides, on the entire surface of the substrate 100 on which the transparent pixel electrode is formed. do.

The substrate 100 on which the alignment layer 163 is formed is defined as a plurality of A regions and B regions.

The area A and the area B correspond to half of each single pixel.

The mask 170 including the transmission part C and the shielding part D is positioned below the array substrate 100 having the above-described configuration.

The transmission part C of the mask 170 is positioned to correspond to the area A, and the shielding part D is positioned to correspond to the area B.

Next, ultraviolet (L1) is irradiated from the upper portion of the array substrate 100 to determine the alignment characteristic of the alignment layer 163.

In this case, the alignment characteristic of the alignment layer of the region B is changed by the incident light L1, and the alignment characteristic is changed once again by the light L2 reflected by the shielding part D.

Therefore, a region corresponding to the transmission portion C of the mask 170 is defined as a first domain having a first alignment characteristic, and a region corresponding to the shielding portion D is a second domain having a second alignment characteristic. Is defined.

Through the process as described above it can be produced an array substrate for a liquid crystal display device according to the present invention.

Therefore, the substrate is manufactured by the multi-domain implementation method according to the present invention. Since two domains can be defined in a single pixel by one exposure process, the process time can be shortened.

In addition, since there is no movement of the mask on the substrate, the region having the third alignment characteristic does not occur due to misalignment of the substrate and the mask, so that no disclination phenomenon, which is a light leakage phenomenon, does not occur, and thus a liquid crystal display having a wide viewing angle and a high image quality. It is effective to manufacture the device.

Claims (7)

Forming an alignment film on the substrate; Defining the alignment layer as an A region and a B region; Placing a mask comprising a transmissive portion and a reflecting portion under the substrate; Making the transmissive part of the mask correspond to the area A and the reflecting part to correspond to the area B; Irradiating ultraviolet rays from the upper portion of the substrate, wherein the region A has a first alignment characteristic, and the alignment layer corresponding to the region B has a second alignment characteristic. 2 domain formation method comprising. The method of claim 1, The alignment layer is a two-domain formation method of the photocurable material, the alignment characteristic is changed by ultraviolet light. Forming a gate electrode and a gate wiring on the substrate; Forming a gate insulating film as a first insulating film on an entire surface of the substrate on which the gate electrode and the gate wiring are formed; Forming an active layer and an ohmic contact layer on the gate insulating layer on the gate electrode; Forming a source electrode and a drain electrode in contact with the ohmic contact layer, and a data line connected to the source electrode; Forming a protective film, which is a second insulating film, on the entire surface of the substrate on which the source and drain electrodes are formed; Patterning the second passivation layer to form a drain contact hole exposing a portion of the drain electrode; Forming a transparent pixel electrode in contact with the drain electrode; Forming an alignment layer by coating an alignment material on the entire surface of the substrate on which the transparent pixel electrode is formed; Defining a plurality of pixels formed on the substrate and having an alignment layer formed in regions A and B; Placing a mask comprising a transmissive portion and a reflective portion under the substrate on which the alignment layer is formed; Making the transmissive part of the mask correspond to the area A and the reflecting part of the mask corresponding to the area B; Irradiating ultraviolet rays from the top of the substrate to define a single pixel as two domains having different orientation characteristics Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 3, wherein And wherein the alignment material is a photocurable material whose alignment characteristics are changed by ultraviolet rays. The method of claim 3, wherein The first silicon nitride film is formed by reacting a siren (SiH ₄ ) gas and an ammonia (NH ₃ ) gas in a ratio of 1: 5. The method of claim 3, wherein And wherein the active layer is formed of pure amorphous silicon (a-Si: H), and the ohmic contact layer is formed of impurity amorphous silicon (n + a-Si: H). The method of claim 3, wherein And the transparent pixel electrode is formed of one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZO).