KR20030057124A - Monitoring method for TFT fabrication process - Google Patents

Abstract

PURPOSE: A method for monitoring TFT(Thin Film Transistor) manufacturing process is provided to easily monitor the thickness of a photoresist film remaining in a channel area due to diffractive exposure by forming plural test patterns with the photoresist on a substrate except the area of a TFT. CONSTITUTION: An insulating film, a semiconductor layer, an extrinsic semiconductor layer and a source/drain layer are formed on a gate by using 4-mask process(301). A photoresist film is layered on the source/drain layer, and a photoresist film having plural test patterns is formed in the black area on a substrate(302). Exposure is performed by using a patterned mask to generate a fully exposed area, a diffractively exposed area and a non-exposed area(303). Development is performed in the exposed photoresist film(304). The propriety of exposure in the photoresist area is examined by detecting the exposure degree of the test patterns(305).

Description

Monitoring method for TFT fabrication process

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to TFT manufacturing, and in particular, in manufacturing a TFT using a four-mask process, a TFT capable of easily monitoring the adequacy of a photoresist film thickness left by diffraction exposure in a region where a channel is formed. It relates to a manufacturing process monitoring method.

Today, video display devices have been changed from CRTs to liquid crystal displays, plasma display panels, and the like. In particular, LCDs have lower power consumption, lighter weight, and emit no harmful electromagnetic waves than CRTs. Due to its advantages, it is being spotlighted as a next generation advanced image display device.

1 is a diagram schematically illustrating a configuration of a general liquid crystal display.

Referring briefly to FIG. 1, a general liquid crystal display device includes a TFT substrate on which a TFT array is formed, a color filter substrate on which a color filter is arranged, a TFT substrate, and a color filter substrate. It includes a liquid crystal (Liquid Crystal) injected between the back light (Back Light) for supplying light for displaying an image.

Here, the TFT array formed on the TFT substrate serves to transmit and control an electrical signal, and the liquid crystal controls the degree of light transmission by changing the molecular structure according to the applied voltage. The light controlled through the above process passes through the color filter substrate and is displayed in a desired color and image.

Various methods of manufacturing a TFT substrate having such a TFT array have been developed, and FIG. 2 is a view showing a process of manufacturing a TFT by a general four-mask process as one known manufacturing method.

A brief description of the four-mask process includes the following steps. In the state where the gate is first formed, an insulating film such as SiNx, a semiconductor layer such as a-Si, an impurity semiconductor layer such as n ⁺ a-Si, a source / drain layer such as Mo, and a photoresist film are sequentially stacked. In exposing the photoresist film, exposure is performed using a mask patterned to generate a complete exposure part, a diffraction exposure part, and a non-exposed area.

In the selectively exposed state as described above, the source / drain layer is etched through the wet etching as the first etching process with respect to the complete exposure area where the source / drain layer is exposed. The impurity semiconductor layer and the semiconductor layer exposed in the first etching process may be etched through dry etching as the second etching process.

The source / drain layer is then exposed through an ashing process on the photoresist film remaining in the diffraction exposure area as a third etching process. As a fourth and fifth etching process, etching is performed on the source / drain layer and the impurity semiconductor layer through dry etching.

By the way, when manufacturing a TFT through such a 4-mask process, the thickness of the photoresist film left by the said diffraction exposure will have a large influence on the performance of the TFT completed by the etching process which advances sequentially in the future. .

At this time, when the exposure to the diffraction exposure area is excessively performed through the exposure to the photoresist film, the photoresist film remaining in the diffraction exposure area is formed thinner than the design reference value. In addition, when exposure to the diffraction exposure area is insufficient, the photoresist film remaining in the diffraction exposure area is formed thicker than the design reference value.

This may be affected by the slit pattern of the mask for performing the diffraction exposure, and may be affected as the intensity of the exposure amount changes even when using the slit pattern of the same mask.

As such, when the exposure amount control for the photoresist film is out of the design reference range, the thickness of the photoresist film that is desired to remain through the diffraction exposure is out of the reference range. Accordingly, as the thickness of the photoresist film is formed thicker or thinner, insufficient etching or overetching occurs in an etch process which is sequentially performed in the future, and as a result, a problem may occur in that a defective TFT can be manufactured.

However, in the related art, by measuring the remaining thickness of the photoresist film through the Macro / Micro inspection program, the thickness detection process is complicated and time-consuming. In addition, it is possible to estimate the remaining thickness of the photoresist film from the measurement of the CD value by using a CD (Critical Dimension) measuring device, but there is a disadvantage that a lot of time passes after the process is completed.

Accordingly, when a problem is found in the process through the inspection process, a process error occurs in all the TFTs in which the process progresses from the corresponding TFT in which the problem is found to the time of the inspection result, and thus a large accident may occur. There is this.

The present invention has been made in view of the above-described conditions. In manufacturing a TFT using a 4-mask process, a channel is formed by forming a plurality of test patterns with photoresist on a substrate other than the region where the TFT is formed. It is an object of the present invention to provide a TFT manufacturing process monitoring method capable of easily monitoring the adequacy of a photoresist film thickness left by diffraction exposure in a region.

1 is a view schematically showing a configuration of a general liquid crystal display device.

2 is a view illustrating a process of manufacturing a TFT by a general 4-mask process.

3 is a flowchart illustrating a process of monitoring a TFT manufacturing process by the TFT manufacturing process monitoring method according to the present invention.

4 illustrates an example of a test pattern formed on a substrate in order to perform a TFT manufacturing process monitoring method according to the present invention.

In order to achieve the above object, in the TFT manufacturing process monitoring method according to the present invention, in manufacturing a TFT array using a 4-mask process,

Sequentially stacking an insulating film, a semiconductor layer, an impurity semiconductor layer, and a source / drain layer while the gate is formed;

Stacking a photoresist film on the source / drain layer and forming a photoresist film having a plurality of test patterns on a substrate in a region where a TFT array is not formed;

Performing exposure using a patterned mask so that a full exposure / diffraction exposure / non-exposure region is generated for the photoresist film formed on the source / drain layer in view of the channel formation region;

Performing development on the exposed photoresist film; And

Detecting a degree of exposure to the plurality of test patterns and examining whether the exposure to the photoresist film formed on the source / drain layer is appropriate; Its features are to include.

Here, in the step of exposing the photoresist film, the plurality of test patterns provided on the substrate in the region where the TFT array is not formed are characterized in that complete exposure is performed.

Further, in examining whether the exposure of the photoresist film formed on the source / drain layer is appropriate, the exposure data for each test pattern is referred to by referring to the type of the test pattern that is present without being lost by performing the exposure. Compared with that, it is characterized in determining whether the exposure to the photoresist film is appropriate.

In addition, one test pattern constituting the plurality of test patterns is characterized in that a plurality of lines and spaces are repeated to form a predetermined size.

In addition, the sum of the line width and the space width forming one test pattern is characterized in that it has a predetermined value.

According to the present invention, in manufacturing a TFT using a four-mask process, by forming a plurality of test patterns with photoresist on a substrate other than the region where the TFT is formed, it is left by diffraction exposure in the region where the channel is formed. Paper has the advantage of easily monitoring the appropriateness of the photoresist thickness.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a flowchart illustrating a process of monitoring a TFT manufacturing process by the TFT manufacturing process monitoring method according to the present invention.

Referring to FIG. 3, first, with a gate formed using a 4-mask process, an insulating film such as SiNx, a semiconductor layer such as a-Si, an impurity semiconductor layer such as n ⁺ a-Si, a source such as Mo The drain layers are sequentially stacked (step 301).

Then, a photoresist film is laminated on the source / drain layer, and a photoresist film having a plurality of test patterns is formed on the substrate (the margin part of the substrate) in the region where the TFT array is not formed, as shown in FIG. (Step 302). 4 is a view showing an example of a test pattern formed on a substrate in order to perform the TFT manufacturing process monitoring method according to the present invention.

The test patterns shown in FIG. 4 show one combination example, and each test pattern is formed with different diffraction patterns, and each rotation pattern is provided with a predetermined rule, thereby analyzing the appropriateness of the exposure dose in the subsequent exposure process. It becomes possible.

Looking at the combination of the test pattern shown in Figure 4, each pattern has the following differences.

First test pattern: line width 1.3mm, space width 1.5mm

Second test pattern: line width 1.4mm, space width 1.4mm

Third test pattern: line width 1.5mm, space width 1.3mm

Fourth test pattern: line width 1.6mm, space width 1.2mm

That is, the sum of the line width and the space width of the first to fourth test patterns are all formed in 2.8 mm, the line width increases by 0.1 mm, and the space width decreases by 0.1 mm. From the standpoint of the aperture ratio, the aperture ratio of the first test pattern is relatively large, and the aperture ratio of the fourth test pattern is relatively small. Here, the aperture ratio may be calculated as the space width for the entire area (line width + space width).

This is because the photoresist film has an exposure effect depending on the amount of energy absorbed per unit area, and thus the degree of the photoresist film removed is changed depending on the exposure amount in the subsequent exposure process. That is, even for the same exposure amount, since the energy required to remove the first test pattern and the energy degree required to remove the fourth test pattern are different, the range of the test pattern to be removed varies according to the aperture ratio. This will be described in detail at the stage of examining the appropriateness of the exposure dose.

On the other hand, after the step 302, the exposure is performed using a patterned mask so that a complete exposure / diffraction exposure / non-exposure area is generated for the photoresist film formed on the source / drain layer in consideration of the channel formation area ( Step 303).

Accordingly, when the intensity of exposure is constant, the exposure amount irradiated to the photoresist film is controlled by the patterned mask, so that the photoresist film is sufficiently exposed so that the photoresist film is completely disappeared, and the diffraction exposure area The silver channel is exposed so that a photoresist film having a predetermined thickness can be left as a portion to be formed, and the non-exposed region is left as it is not exposed.

In this case, the photoresist provided as the test pattern may be selectively exposed among full exposure or diffraction exposure. However, in the case of using diffraction exposure, a slit must be separately formed in the mask, so that it is easier to perform exposure to the test pattern through full exposure.

After the exposure process is performed in step 303, development is performed on the exposed photoresist film (step 304). Accordingly, the thickness of the photoresist film remaining in each exposure area is different depending on the exposure amount performed in step 303.

That is, the photoresist film of the full exposure region does not remain, the photoresist film of the diffraction exposure region remains a photoresist film of a predetermined thickness, and all of the photoresist film of the non-exposed region remains.

Here, the thickness of the photoresist film remaining in the diffraction exposure area has a great influence on the process in the future. It can be detected. That is, the degree of exposure to the plurality of test patterns is detected, and whether or not the exposure is appropriate for the photoresist film formed on the source / drain layer is examined (step 305).

If the actual exposure is performed so as to satisfy the design reference value for the predetermined thickness that should remain in the diffraction exposure area, the first test pattern, which is described by way of example in FIG. And all of the second test patterns are removed, and the third test pattern and the fourth test pattern remain. By referring to data acquired through an existing M / M inspection program or a CD measuring device, it is possible to determine the exposure state of each test pattern when proper exposure is performed.

In this case, when the overexposure is performed in step 303, since the exposure energy is increased, all of the third test patterns may be removed, and only the fourth test patterns may remain. Of course, when the exposure degree is severe, the fourth test pattern may also be removed.

When the underexposure is performed in step 303, since the exposure energy is reduced, not only the third and fourth test patterns but also the second test pattern or the first test pattern may remain. .

In this way, it is possible to determine whether the exposure dose is appropriate for the diffraction exposure portion through macro inspection (visual inspection) on the test pattern. In addition, through the visual inspection process in the developing step, it is possible to determine whether or not the step abnormality, it is possible to quickly detect the process abnormality. As a result, even when a process abnormality occurs, it is possible to cope quickly so that a large accident due to time delay can be prevented in advance.

According to the TFT manufacturing process monitoring method according to the present invention as described above, in manufacturing a TFT using a 4-mask process, by forming a plurality of test patterns with a photoresist film on a substrate outside the region where the TFT is formed, There is an advantage that it is easy to monitor the appropriateness of the thickness of the photoresist left by the diffraction exposure in the region where the channel is formed.

Further, according to the TFT manufacturing process monitoring method according to the present invention, when a process abnormality occurs for exposure, detection of a process abnormality can be made faster, thereby preventing a large accident due to processing delay in advance. There is an advantage.

Claims (5)

In manufacturing a TFT array using a 4-mask process, Sequentially stacking an insulating film, a semiconductor layer, an impurity semiconductor layer, and a source / drain layer while the gate is formed; Stacking a photoresist film on the source / drain layer and forming a photoresist film having a plurality of test patterns on a substrate in a region where a TFT array is not formed; Performing exposure using a patterned mask so that a full exposure / diffraction exposure / non-exposure region is generated for the photoresist film formed on the source / drain layer in view of the channel formation region; Performing development on the exposed photoresist film; And Detecting a degree of exposure to the plurality of test patterns and examining whether the exposure to the photoresist film formed on the source / drain layer is appropriate; TFT manufacturing process monitoring method comprising a. The method of claim 1, And performing exposure to the photoresist film, wherein a plurality of test patterns provided on a substrate in a region where the TFT array is not formed are subjected to complete exposure. The method of claim 1, In the step of examining the appropriateness of the exposure to the photoresist film formed on the source / drain layer, the comparison with the exposure data for each test pattern with reference to the type of the test pattern that does not disappear with the performance of the exposure And determining whether or not the exposure to the photoresist film is appropriate. The method of claim 1, And a plurality of lines and spaces are repeated to form a predetermined size in one test pattern constituting the plurality of test patterns. The method of claim 4, wherein And a line width and a space width forming the one test pattern have a predetermined value.