KR20030056849A - Circuit for Buffering Output - Google Patents

Abstract

PURPOSE: An output buffer circuit is provided to reduce noise of a buffer by increase the number of drive transistors which are used the buffer as an operation range is shifted to a low voltage region. CONSTITUTION: An output buffer circuit includes a first delay block(11), a second delay block(12), a first sensing block(13), a second sensing block(14), a pair of first control blocks(28,29), a plurality of second control blocks(25,26,27), a plurality of third control blocks(22,23,24) and a plurality of driving transistors(30,31,32,33,34,35). In the output buffer circuit, the first and the second delay blocks(11,12) delay the data input signal by a predetermined time and outputs the delayed data input signal and the sensing blocks(13,14) sense the voltage level of the operational voltage and outputs the sensed signal. The plurality of driving transistors(30,31,32,33,34,35) output the data output signals by receiving the control signals.

Description

Circuit for Buffering Output

The present invention relates to a buffer circuit, in particular, by dividing the size of the drive transistor and the operating voltage region of the device, by using a predetermined drive transistor in the high voltage region, increasing the drive transistor to be used toward the low voltage region to minimize the noise generated It relates to an output buffer circuit.

Hereinafter, a conventional output buffer circuit will be described with reference to the accompanying drawings.

1 is a circuit diagram showing a conventional output buffer circuit.

As shown in FIG. 1, a conventional output buffer circuit includes an inverter 1 that receives an enable signal OE and inverts the enable signal OE, and a NAND gate that negatively multiplies the enable signal OE and the data input signal Din ( 2), a NOR gate 3 that negatively combines the output value s1 of the inverter 1 with the data input signal Din, and an output value s2 of the NAND gate 2 are applied to the gate. The PMOS transistor 4 connected between the power supply voltage terminal Vcc and the data output terminal and the output value of the NOR gate 3 are applied to the gate, and the data output terminal and the ground voltage terminal ( And an MOS transistor 5 connected between Vss).

The conventional output buffer circuit operates while the enable signal OE is high. If the enable signal OE is low, since the PMOS and NMOS transistors 4 and 5 are turned off, the data input signal Din does not affect the data output signal Dout.

If the enable signal OE is high, the data output signal Dout is determined according to the state of the data input signal Din.

That is, when the data input signal Din is high, the output s2 of the NAND gate 2 has a low value, and the output s3 of the noah gate 3 has a low value. The MOS transistor 4 is turned on and the NMOS transistor 5 is turned off. Therefore, the data output Dout shows a high state.

On the contrary, when the data input signal Din is low, the output s2 of the NAND gate 2 has a high value, and the output s3 of the noah gate 3 has a high value. The MOS transistor 4 is turned off, and the NMOS transistor 5 is turned on. Thus, the data output Dout represents a low state.

However, the conventional output buffer circuit as described above has the following problems.

In the output buffer circuit, the PMOS transistor 4 and the NMOS transistor 5, which are the later drive transistors, are simultaneously turned on and off, and noise is generated in the power terminal by the current flowing momentarily.

In particular, in a device using a battery or the like, such a power noise may become larger in the high voltage region, which may cause a malfunction of the device. In the low voltage region, the capacity of the drive transistor may be reduced, resulting in deterioration of device characteristics.

The present invention has been made to solve the above problems, and by dividing the size of the drive transistor and the operating voltage region of the device, a predetermined drive transistor is used in the high voltage region, and more drive transistors are used to increase the noise toward the low voltage region. It is an object to provide the minimum output buffer circuit that has occurred.

1 is a circuit diagram showing a conventional output buffer circuit

2 is a circuit diagram showing an output buffer circuit of the present invention.

Explanation of symbols for the main parts of drawings

11: first delay unit 12: second delay unit

13 high voltage detection unit 14 low voltage detection unit

21, 22, 25: inverter 23, 26, 28: NAND gate

24, 27, 29: Noah gate 30, 32, 34: PMOS transistor

31, 33, 35: NMOS transistor

The output buffer circuit of the present invention for achieving the above object includes a delay unit for outputting a data input signal delayed by a predetermined time, a detection unit for detecting a voltage level of the operating voltage and outputting a detection signal, an enable signal and A control unit configured to receive a data input signal, a data input signal delayed by a predetermined time and the detection signal, and sequentially output a control signal according to a time when the data input signal is applied; and to receive the control signal and output a data output signal. And a driving transistor unit.

Hereinafter, an output buffer circuit of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram showing an output buffer circuit of the present invention.

The output circuit of the present invention is divided into a delay unit, a control unit, and a driving transistor unit. In the embodiment shown in FIG. 2, the operating voltage region is divided into three regions.

In order to detect such an operation region, a high voltage detector 13 for detecting a first voltage or more and a low voltage detector 14 for detecting a second voltage or less are separately configured.

In addition, the delay units 11 and 12 are each composed of two delay elements for operating the driving transistor unit for each of the operation regions, and each of the first and second delay units 11 and 12 has a predetermined time? Time. The input signal is delayed and output.

As shown in FIG. 2, the output buffer circuit of the present invention includes a first delay unit 11 for delaying a data input signal Din by a predetermined time σ and outputting data through the first delay unit 11. When the second delay unit 12 outputs the data input signal 2σ time delayed din by delaying the input signal σ time delayed Din again by the same predetermined time σ, and when the operating voltage is equal to or greater than the first voltage V1. A first detector 13 outputting a high voltage detection signal s7, a second detector 14 outputting a low voltage detection signal s8 when the operating voltage is less than or equal to the second voltage V2, and an enable signal. (OE) and the first control unit (28, 29) for receiving the data input signal (Din) and outputs the first control signal (s11, s12), the enable signal (OE), the first delay unit ( 11) a second time outputting the second control signals s13 and s14 by receiving the t time delayed data input signal σ time delayed Din and the low voltage detection signal s8 through 11). 2 t time delayed data input signal (2σ time delayed Din) and high voltage detection signal s7 are received through the control unit 25, 26, 27, the enable signal OE, and the second delay unit 12. According to the third control units 22, 23, and 24 which output the third control signals s15 and s16, and the first, second and third control signals s11, s12, s13, s14, s15 and s16. And first, second, and third driving transistors 30, 31, 32, 33, 34, and 35 that operate to output data output signals Dout, respectively.

The first, second, third driving transistors 30, 31, 32, 33, 34, and 35 may be connected to the PMOS transistors 30, 32, and 34 between the power supply voltage Vcc and the ground voltage Vss, respectively. NMOS transistors 31, 33, and 35 are connected in series, and the contacts of the PMOS transistors 30, 32, 34 and NMOS transistors 31, 33, 35, that is, of each transistor The data output signal Dout is output to the drain terminal.

Each of the first, second, and third controllers controls control signals s11, s12, s13, s14, s15, and s16 for turning on / off PMOS and NMOS transistors of the first, second, and third driving transistors. And NAND gates 29, 27, and 24 and NAND gates 28, 26, and 23 for outputting the same.

That is, the first control unit receives the enable signal OE and the data input signal Din, and inverts and outputs the enable signal OE by inverting the first NAND gate 28 and the enable signal OE. The first inverter 21, the output s5 of the first inverter 21, and the first NOR gate 29 are applied to the data input signal Din and are negatively logically coupled thereto.

The first control signals s12 and s11 which are outputs of the first control unit refer to the outputs of the first NAND gate 28 and the first NOR gate 29 in pairs.

In addition, the first control signals s11 and s12 are applied to the gate of the NMOS transistor 31 and the gate of the PMOS transistor 30 of the first driving transistor, respectively, to determine the data output signal value.

The operation of the first control unit and the first driving transistors 30 and 31 will be described as follows.

The enable signal OE determines whether the output buffer circuit operates. In the low state, the output buffer circuit does not operate. The output buffer circuit operates only in the high state. Therefore, the following description will proceed on the assumption that the enable signal OE is in a high state.

In the first controller, when the enable signal OE is in a high state, the output signals s11 and s12 of the first controller are determined by the data input signal Din.

When the data input signal Din is high, the output s12 of the first NAND gate is low and the output of the first NOR gate s11 is low. Accordingly, in the first driving transistor, the PMOS transistor 30 is in an on state and the NMOS transistor 31 is in an off state, so that the data output signal Dout is output in a high state.

The second control unit operates by three input signals, unlike the first NAND gate 28 and the first Noah gate 29 of the first control unit operating with two input signals. In this case, the added signal is a low voltage detection signal s8 that outputs a high signal when the operating voltage is lower than the second voltage V2 (low voltage level) and a low signal when the operating voltage is high. The low voltage detection signal s8 is a signal output from the second detection unit 13.

The second control unit has a low voltage detection signal s8 output from the second detection unit 14, a sigma time delayed data input signal sigma time delayed Din output from the first delay unit 11, and enable. A second NAND gate 26 that negatively multiplies the signal OE, a second inverter 25 that inverts the low voltage detection signal s8 output from the second detection unit 14, and the second inverter ( The output s10 of the signal 25, the sigma time delayed data input signal sigma time delayed Din output from the first delay unit 11, and the signal s5 inverted and output the enable signal OE. The second NOR gate 27 is applied to the negative logic logic unit.

In addition, the output s14 of the second NAND gate 26 is a gate of the PMOS transistor 32 of the second driving transistor, and the output s13 of the second NOR gate 27 is of the second driving transistor. It is applied to the gate of the NMOS transistor 33.

Considering the above operation considering the relationship with the driving transistor of the subsequent stage, the operation is as follows.

If the operating voltage is higher than the second voltage V2, the low voltage detection signal s8 has a low signal. Therefore, the output s14 of the second NAND gate 26 is in a high state, and the second The output s13 of the NOR gate 27 has a low state, and both PMOS and NMOS transistors 32 and 33 of the second driving transistor are turned off. In this case, the second control unit and the second driving transistors 32 and 33 do not affect the data output signal Dout regardless of other signal states other than the low voltage detection signal.

If the operating voltage is lower than the second voltage V2, the low voltage detection signal s8 is a high signal and the second inverter 25 is a low signal. In this case, the data output signal Dout is determined by the data input signal sigma time delayed Din applied.

That is, when the sigma time delayed data input signal (sigma time delayed Din) is a high signal, the second NAND gate 26 outputs a low signal (s14), and the second noah gate 27 outputs a high signal. Output (s13). Thus, the PMOS transistor 32 of the second driving transistor is turned on, and the NMOS transistor 33 maintains an off state. Thus, in this case, the data output signal Dout represents a high state.

Next, the configuration of the third controller will be described.

The third controller 22 includes a third inverter 22 for inverting the high voltage detection signal s7 output from the first detector 13, an output s9 of the third inverter 22, and a second Output from the 2nd time delayed data input signal (2σ time delayed Din) output from the delay part 12, the 3rd NAND gate 23 which carries out the negative logic of the enable signal OE, and the 1st sensing part 13, The high voltage detection signal s7, the 2σ time delayed Din output from the second delay unit 12, and the signal s5 inverted and output the enable signal OE. The third NOR gate 24 is applied to the negative logic unit.

The third controller may include a high voltage detection signal s7 indicating a high level when the operating voltage is greater than or equal to the first voltage V1 (high voltage level) and a low level when the operating voltage is less than or equal to the first voltage V1. Shape.

An operation of the third controller and the third driving transistor is as follows.

The high voltage detection signal s7 is output as a high signal when the operating voltage is greater than or equal to the first voltage V1, and the output s9 of the third inverter 22 becomes a low signal. Therefore, at this time, the output s16 of the third NAND gate 23 becomes a high signal, and the PMOS transistor 34 of the third driving transistor is turned off. In addition, since the output s16 of the third NAND gate 23 becomes a low signal when the high voltage detection signal s7 is a high signal, the NMOS transistor 35 of the third driving transistor also indicates an off state. As a result, when the high voltage detection signal s7 is greater than or equal to the first voltage V1, the third driving transistors 34 and 35 do not drive.

The high voltage detection signal s7 is output as a low signal when the operating voltage is less than or equal to the first voltage V1. In this case, the data input signal is delayed by 2 sigma by the first and second delay units 11 and 12. The values of the outputs s16 and s15 of the third NAND gate 23 and the third NOR gate 24 are determined according to the state of (2σ time delayed Din).

The enable signal OE is a high signal, the high voltage detection signal s7 is a low signal (the output s9 of the third inverter 22 is a high signal), and the data input signal 2σ time delayed by 2σ time. When the state of the delayed Din is a high signal, the third NAND gate 23 outputs a low signal to turn on the PMOS transistor 34 of the third driving transistor. At this time, the third NOR gate 24 is By outputting the high signal and turning off the NMOS transistor 35, the high signal is output as the data output signal Dout.

On the other hand, the enable signal OE is a high signal, the high voltage detection signal s7 is a low signal (the output s9 of the third inverter 22 is a high signal), and the data input signal delayed by 2 sigma time ( When the state of 2σ time delayed Din is a low signal, the third NAND gate 23 outputs a high signal (s16) to turn off the PMOS transistor 34 of the third driving transistor, and at this time, the third NOR The gate 24 outputs the high signal s15 to turn on the NMOS transistor 35 to output the low signal as the data output signal Dout.

The first and second detectors 13 and 14 respectively detect whether the operating voltage is greater than or equal to the first voltage V1 and sense whether or not the second voltage V2 << V1 is less than or equal to the operating voltage. If it is between V1 and V2, the second and third driving transistors do not operate, and only the first driving transistors 30 and 31 operate.

When the power supplied to the device is in the high voltage region (V> V1), the high voltage detection signal s7 indicates a high signal and the inverted output s9 of the third inverter 22 indicates a low signal, thereby driving the third drive. Both PMOS and NMOS transistors 34 and 35 of the transistor are turned off.

At this time, the low voltage detection signal s8 indicates a low signal, and the output s10 of the second inverter 25 inverted indicates a high signal. Therefore, both PMOS and NMOS transistors 32 and 33 of the second driving transistor are also turned off.

Therefore, the driving transistor operating in this case is only the first driving transistors 30 and 31, which reduces the capacitor of the output drive in such a high voltage region, thereby reducing the power noise.

When the power supplied to the device is in the region (V2 <V <V1) between the high voltage and the low voltage, the high voltage detection signal s7 converts the low signal and the inverted output s9 of the third inverter 22 becomes the high signal. PMOS and NMOS transistors 34 and 35 of the third driving transistor selectively operate.

At this time, the low voltage detection signal s8 indicates a low signal, and the output s10 of the second inverter 25 inverted indicates a high signal. Therefore, both PMOS and NMOS transistors 32 and 33 of the second driving transistor are turned off.

Accordingly, the driving transistors that operate in this case are the first and second driving transistors 30, 31, 34, and 35, and the first and second driving transistors are sequentially termed at a predetermined voltage. ), And power noise is reduced.

When the power supplied to the device is in the low voltage region V <V2, the high voltage detection signal s7 indicates a low signal and the inverted output s9 of the third inverter 22 indicates a high signal, thereby driving the third drive. The PMOS and NMOS transistors 34 and 35 of the transistor operate selectively.

At this time, the low voltage detection signal s8 indicates a high signal, and the output s10 of the second inverter 25 inverted indicates a low signal. Therefore, the PMOS and NMOS transistors 32 and 33 of the second driving transistor also selectively operate.

Therefore, the driving transistors operating in this case are the first, second, and third driving transistors, and the driving transistors are sequentially operated with a predetermined time term, so that the capacitor of the output drive increases compared to the high voltage or the intermediate voltage level. And instantaneous current increases, improving the output drive characteristics of the device.

At this time, by sequentially driving the first, second, and third driving transistors, the current flowing momentarily decreases, thereby reducing power noise.

The output buffer circuit of the present invention as described above has the following effects.

In the output buffer circuit, noise is generated in the power terminal due to the instantaneous current flowing when the drive transistor is turned on / off. In particular, in a high voltage region, such a power noise becomes larger in a device using a battery, causing a device malfunction. In the low voltage region, the capacitor of the drive transistor may be reduced, resulting in deterioration of device characteristics.

In order to improve this, the present invention divides the size of the drive transistor and the operating voltage region of the device, and uses only the appropriate drive transistor size in the high voltage region, and gradually increases the size of the drive transistor to be used in the low voltage region. An output buffer circuit with noise can be implemented.

Claims (9)

A delay unit for outputting a data input signal by delaying a predetermined time; A sensing unit for sensing a voltage level of an operating voltage and outputting a sensing signal; A controller which receives an enable signal, a data input signal, a data input signal delayed by a predetermined time, and the sensing signal and sequentially outputs a control signal according to the time when the data input signal is applied; And a driving transistor unit receiving the control signal and outputting a data output signal. The output buffer circuit according to claim 1, wherein the delay unit comprises a plurality of delay elements having a predetermined delay value corresponding to the number of regions to be sensed by the operating voltage. The method of claim 1, wherein the control unit A NAND gate receiving the enable signal, the data input signal or the data input signal delayed by a predetermined time, and the sensing signal and outputting a negative logic product as a control signal, respectively; And an output buffer circuit for outputting an inversion signal of the enable signal, a data input signal or a data input signal delayed by a predetermined time, and a signal for negatively inverting the inversion signal of the sensing signal as a control signal. . The method of claim 1, wherein the driving transistor unit An output buffer circuit comprising a PMOS transistor configured in series between a power supply voltage and a ground voltage, and an NMOS transistor. A delay unit for outputting a data input signal by delaying a predetermined time; A first detector configured to output a high voltage detection signal when the operating voltage is greater than or equal to the first voltage; A second sensing unit outputting a low voltage sensing signal when the operating voltage is less than or equal to the second voltage; A first controller configured to receive an enable signal and the data input signal and output a first control signal; A second control unit receiving the enable signal, a data input signal delayed t time through the delay unit, and a low voltage detection signal to output a second control signal; A third control unit receiving the enable signal, a data input signal delayed by 2t time through the delay unit, and a high voltage detection signal to output a third control signal; And first, second, and third driving transistors which operate according to the first, second, and third control signals to output data output signals, respectively. The method of claim 5, wherein the first control unit comprises: a first NAND gate receiving the enable signal and the data input signal and performing a negative logic to output a first control signal; And an inverted signal of the enable signal and a first NOR gate receiving the data input signal and outputting a first control signal. The display device of claim 5, wherein the second controller comprises: a second NAND gate receiving the enable signal, the data input signal delayed in time t, and a low voltage detection signal and performing a negative logic to output a second control signal; And a second NOR gate configured to receive the inverted signal of the enable signal, the t-time delayed data input signal, and the inverted signal of the low voltage detection signal to output a second control signal. 6. The PMOS transistor and the NMOS transistor of claim 5, wherein the PMOS transistor and the NMOS transistor are configured in series between a power supply voltage and a ground voltage, respectively, and the gate and NMOS transistors of the PMOS transistors are respectively configured. The gate of the output buffer circuit, characterized in that the first, second, third control signal is applied, and outputs a data output signal to the contacts of the respective PMOS and NMOS transistor. The third NAND gate of claim 5, wherein the third control unit receives the enable signal, the 2t time-delayed data input signal, and an inverted signal of a high voltage sensing signal, and outputs a third control signal by performing a negative logic multiplication. , And a third NOR gate configured to receive the inverted signal of the enable signal, the 2t time-delayed data input signal, and a high voltage sensing signal to output a third control signal.