KR20030056460A - Circuit for compensating ras time in semiconductor memory device - Google Patents

Circuit for compensating ras time in semiconductor memory device Download PDF

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KR20030056460A
KR20030056460A KR1020010086675A KR20010086675A KR20030056460A KR 20030056460 A KR20030056460 A KR 20030056460A KR 1020010086675 A KR1020010086675 A KR 1020010086675A KR 20010086675 A KR20010086675 A KR 20010086675A KR 20030056460 A KR20030056460 A KR 20030056460A
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voltage
block
ras
time
node
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KR1020010086675A
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Korean (ko)
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조주환
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주식회사 하이닉스반도체
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)

Abstract

PURPOSE: A circuit for compensating a row address strobe time of a semiconductor memory device is provided to finish the row address strobe(RAS) time by monitoring the voltage of RTO node commonly connected to the bit line, thereby securing the RAS time without depending on the change of PVT(process, voltage and temperature). CONSTITUTION: A circuit for compensating a row address strobe time of a semiconductor memory device includes a sensing start block(100), an initializing block(200) for implementing the initialization of each block based on the output of the sensing start block(100), a voltage comparison block(300), a latch block(400) and an output block(500). In the circuit, the sensing start block(100) latches the start signal and outputs the latched signal when the corresponding memory cell block is selected and the start signal is activated. The latch block(400) is initialized by the initializing block(200) and latches the comparison result of the voltage comparison block(300). And, the output block(500) outputs the RAS time finish signal based on the latched comparison result.

Description

반도체 메모리장치의 ＲＡＳ 시간 보상회로{CIRCUIT FOR COMPENSATING RAS TIME IN SEMICONDUCTOR MEMORY DEVICE}RAS time compensation circuit of semiconductor memory device {CIRCUIT FOR COMPENSATING RAS TIME IN SEMICONDUCTOR MEMORY DEVICE}

본 발명은 반도체 메모리장치의 RAS 시간 보상회로에 관한 것으로서, 특히 PVT 변화에 대한 RAS 시간의 변화를 보상시킬 수 있는 반도체 메모리장치의 RAS 시간 보상회로에 관한 것이다.The present invention relates to a RAS time compensation circuit of a semiconductor memory device, and more particularly, to a RAS time compensation circuit of a semiconductor memory device capable of compensating a change in RAS time with respect to a PVT change.

DRAM(Dynamic Random Access Memory)에 있어서, 리프레쉬(refresh) 동작은 필수적이다. 이러한 리프레쉬 동작이 일어나는 시간은 RAS 시간과 RP 시간으로 나눌 수 있다.In a DRAM (Dynamic Random Access Memory), a refresh operation is essential. The time at which such a refresh operation occurs can be divided into RAS time and RP time.

리프레쉬 동작은 /RAS 신호를 하이 레벨에서 로우 레벨로 천이시켜 행 어드레스에 해당하는 워드라인을 활성화시킨 뒤, 센스앰프를 동작시켜 메모리 셀에 저장된 데이터를 다시 써넣는 동작과, 비트라인(BIT, /BIT)을 1/2 VDD(비트라인 최대 상승전압)로 프리차지 시키는 동작을 포함한다.In the refresh operation, the word line corresponding to the row address is activated by transitioning the / RAS signal from the high level to the low level, and the sense amplifier is operated to rewrite the data stored in the memory cell, and the bit line (BIT, / BIT) to 1/2 VDD (bit line maximum rise voltage).

RAS(Row Address Strobe) 시간은 리프레쉬 명령이 입력되었을 경우, 충분히 리프레쉬 동작이 일어나도록 행 어드레스 스트로브(/RAS) 신호를 활성화시키는 시간이다.The low address strobe (RAS) time is a time for activating the row address strobe (/ RAS) signal so that a refresh operation sufficiently occurs when a refresh command is input.

RP(Refresh Precharge) 시간은 RAS 시간동안 충분히 리프레쉬 시킨 후, 비트라인의 전압을 1/2 VDD(비트라인 최대 전압차의 1/2)로 프리차지 시키는 시간이다.The RP (Refresh Precharge) time is a time for sufficiently refreshing during the RAS time and then precharging the voltage of the bit line to 1/2 VDD (1/2 of the maximum bit line difference).

따라서, RAS 시간이 정확하게 보장되지 않으면, 리프레쉬 동작과 프리차지 동작이 제대로 일어나지 않아 전체 메모리의 기입 및 독출 동작시 오동작을 일으킬 수 있다.Therefore, if the RAS time is not accurately guaranteed, the refresh operation and the precharge operation may not be performed properly, which may cause a malfunction in the write and read operations of the entire memory.

종래에는 이러한 RAS 시간을 인버터, 또는 커패시터와 저항 등의 지연소자를 사용하여 유지되도록 하였다. 알려진 바와 같이, 이러한 수동소자들은 PVT(Process, Voltage, Temperature)의 변화에 민감하게 변화하기 때문에, RAS 시간이 PVT 의 변화에 따라 변동되어, 지나치게 짧아지거나 지나치게 길어질 수 있었다.Conventionally, such RAS time is maintained by using an inverter or a delay device such as a capacitor and a resistor. As is known, since these passive devices are sensitive to changes in PVT (Process, Voltage, Temperature), the RAS time may be changed according to the change of PVT, which may be too short or too long.

RAS 시간이 짧은 경우에는 리프레쉬 동작이 충분하게 일어나지 않아, 독출동작시 오동작을 일으킬 수 있으며, RAS 시간이 긴 경우에는 뒤에 일어나는 프리차지 동작이 제대로 일어나지 않는 문제점이 있었다.If the RAS time is short, the refresh operation does not occur sufficiently, which may cause a malfunction during the read operation. If the RAS time is long, the precharge operation that occurs later does not occur properly.

본 발명의 목적은 비트라인에 공통으로 접속되는 RTO 노드의 전압을 이용하여 RAS 시간을 종료시킴으로써 PVT 의 변화에 무관하게 RAS 시간을 보장하는 것이다.An object of the present invention is to ensure the RAS time regardless of the change of PVT by terminating the RAS time using the voltage of the RTO node commonly connected to the bit line.

도 1 은 본 발명의 일실시예에 따른 RAS 시간 보상회로를 나타낸 회로도.1 is a circuit diagram showing a RAS time compensation circuit according to an embodiment of the present invention.

도 2 는 본 발명의 일실시예에 따른 RAS 시간 보상회로의 동작을 나타낸 파형도.Figure 2 is a waveform diagram showing the operation of the RAS time compensation circuit according to an embodiment of the present invention.

본 발명에 따른 반도체 메모리장치의 RAS 시간 보상회로는, 해당 메모리 셀 블록이 선택되고, 동작의 개시를 나타내는 개시신호가 활성화되었을 경우, 개시신호를 래치시켜 출력하는 센싱 개시수단; 출력되는 개시신호에 기초하여 RAS 시간 종료신호를 초기화시키는 초기화 수단; 초기화 수단에 의해 초기화되며, RTO 노드의 전압과 미리 결정되는 기준전압을 비교하는 전압 비교수단; 초기화 수단에 의해 초기화되며, 상기 전압 비교수단의 비교 결과를 래치시키는 비교결과 래치수단; 및 래치된 비교결과에 기초하여 RAS 시간 종료신호를 출력하는 출력수단을 포함한다.The RAS time compensation circuit of the semiconductor memory device according to the present invention comprises: sensing start means for latching and outputting a start signal when a corresponding memory cell block is selected and a start signal indicating the start of an operation is activated; Initialization means for initializing the RAS timeout signal based on the output start signal; Voltage comparing means initialized by the initialization means and comparing the voltage of the RTO node with a predetermined reference voltage; Comparison result latch means initialized by an initialization means and latches a comparison result of the voltage comparison means; And output means for outputting a RAS timeout signal based on the latched comparison result.

또한, 전압 비교수단은 전류미러형 차동증폭기일 수 있다.In addition, the voltage comparing means may be a current mirror type differential amplifier.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 1 은 본 발명의 일실시예에 따른 RAS 시간 보상회로를 나타낸 회로도이다.1 is a circuit diagram illustrating a RAS time compensation circuit according to an embodiment of the present invention.

본 발명에 따른 RAS 시간 보상회로는, 외부에서 입력되는 센싱 개시신호(START)에 기초하여 센싱 동작의 개시을 알리는 센싱 개시부(100), 센싱 개시부(100)의 출력에 기초하여, 각 부의 초기화를 수행하는 초기화부(200), 비트라인(BIT, /BIT)에 공통으로 접속되는 RTO 노드의 전압을 기준전압(REF)과 비교하는 전압 비교부(300), 전압 비교부의 비교 결과를 래치시키는 비교결과 래치부(400), 비교 결과에 따라 RAS 시간 종료를 알리는 RAS 시간종료신호(OUT)를출력하는 출력부(500)를 포함한다.The RAS time compensation circuit according to the present invention is based on the output of the sensing start unit 100 and the sensing start unit 100 to notify the start of the sensing operation based on the sensing start signal START input from the outside, the initialization of each unit Latching a comparison result of the voltage comparator 300 for comparing the voltage of the RTO node commonly connected to the bit line BIT, / BIT with the reference voltage REF. The comparison result includes a latch unit 400 and an output unit 500 for outputting a RAS timeout signal OUT indicating the end of the RAS time according to the comparison result.

센싱 개시부(100)는 해당 블록이 선택되었음을 알리는 블록선택신호(/BSEL)가 입력되는 NMOS 트랜지스터(N7), 센싱의 시작을 알리는 개시신호(START)가 입력되는 CMOS 인버터(P7, N6), 및 CMOS 인버터(P7, N6)의 출력을 래치시키는 래치(I2, I3)를 포함한다.The sensing initiation unit 100 may include an NMOS transistor N7 to which a block selection signal / BSEL is input to indicate that the corresponding block is selected, CMOS inverters P7 and N6 to which a start signal START to be sensed is input, And latches I2 and I3 for latching the outputs of the CMOS inverters P7 and N6.

블록 선택신호(/BSEL)가 인버터(I1)를 거쳐 NMOS 트랜지스터(N7)의 게이트로 인가된다. NMOS 트랜지스터(N7)의 드레인에는 로우 레벨(low level, 이하 L) 전압인 접지전압이 접속된다. 외부에서 입력되는 센싱 개시신호(START)가 PMOS 트랜지스터(P7)와 NMOS 트랜지스터(N6)의 게이트로 입력된다. PMOS 트랜지스터(P7)의 소오스 단에는 하이레벨(high level, 이하 H) 전압인 바이어스 전압(Vdd)이 인가된다.The block select signal / BSEL is applied to the gate of the NMOS transistor N7 via the inverter I1. A ground voltage, which is a low level (hereinafter L) voltage, is connected to the drain of the NMOS transistor N7. The sensing start signal START input from the outside is input to the gates of the PMOS transistor P7 and the NMOS transistor N6. A bias voltage Vdd, which is a high level (hereinafter, H) voltage, is applied to the source terminal of the PMOS transistor P7.

따라서, 해당 블록이 선택되었을 때 블록선택신호(/BSEL)가 H 레벨에서 L 레벨로 천이하여 접지전압을 노드(ND8)로 전달하며, 이후 개시신호(START)에 따라 CMOS 인버터(P7, N6)가 H 또는 L 레벨 전압을 출력한다. CMOS 인버터(P7, N6)로부터 출력된 H 또는 L 레벨전압은 래치(I2, I3)에 래치된 후 출력된다.Therefore, when the corresponding block is selected, the block selection signal / BSEL transitions from the H level to the L level to transfer the ground voltage to the node ND8, and then the CMOS inverters P7 and N6 according to the start signal START. Outputs an H or L level voltage. The H or L level voltage output from the CMOS inverters P7 and N6 is output after being latched to the latches I2 and I3.

초기화부(200)는, 래치(I2, I3)에 래치된 전압신호를 소정의 시간동안 지연시키는 복수의 인버터(I4, I5, I6, I7, I8, I9), 복수의 인버터(I4, I5, I6, I7, I8, I9)를 통과한 신호와 래치(I2, I3)로부터 지연되지 않는 신호를 AND 연산하는 NAND 연산부(NAND1)와 인버터(I10), 래치(I2, I3)에 래치된 신호에 따라 노드(ND1)의 전위를 접지전압으로 초기화시키는 NMOS 트랜지스터(N5), 및 래치부(I2, I3)에래치된 전압신호에 기초하여 비교결과 래치부(400)로 접지전압을 전달하는 NMOS 트랜지스터(N8 및 N9)를 포함한다.The initialization unit 200 includes a plurality of inverters I4, I5, I6, I7, I8, I9, and a plurality of inverters I4, I5, which delay the voltage signals latched by the latches I2, I3 for a predetermined time. To the signals latched by the NAND calculation unit NAND1 and the inverter I10 and the latches I2 and I3 that AND the signals passing through I6, I7, I8, and I9 and signals that are not delayed from the latches I2 and I3. Therefore, the NMOS transistor N5 for initializing the potential of the node ND1 to the ground voltage, and the NMOS transistor for transferring the ground voltage to the latch unit 400 based on the comparison of the voltage signals latched by the latch units I2 and I3. (N8 and N9).

래치(I2, I3)에 래치된 신호는 홀수개의 인버터 통과후 NMOS 트랜지스터(N8)의 게이트로 인가됨과 동시에, 인버터(I9)를 거쳐 NAND 게이트(NAND1)의 제 1 입력으로 인가된다. 또한, 래치(I2, I3)에 래치된 신호는 NMOS 트랜지스터(N9)의 게이트로 인가됨과 동시에 NAND 게이트(NAND1)의 제 2 입력으로 인가된다. NMOS 트랜지스터(N5)의 게이트로 인버터(I4)로 부터의 신호가 인가되고, 드레인에는 접지전압이 인가되고, 소오스는 노드(ND1)에 접속된다.The signals latched in the latches I2 and I3 are applied to the gate of the NMOS transistor N8 after passing through an odd number of inverters, and are also applied to the first input of the NAND gate NAND1 via the inverter I9. The signals latched to the latches I2 and I3 are applied to the gate of the NMOS transistor N9 and to the second input of the NAND gate NAND1. The signal from the inverter I4 is applied to the gate of the NMOS transistor N5, the ground voltage is applied to the drain, and the source is connected to the node ND1.

따라서, 해당 셀 블록이 선택되고(/BSEL=L), 센싱 개시신호가 활성화되지 않은 상태(START=L)에서, 래치부(I2, I3)는 L 레벨 전압을 출력하고, NMOS 트랜지스터(N5)가 턴온되어, L 레벨 전압(접지전압)이 노드(ND1)로 전달되고, 노드(ND2)의 전위는 L 레벨이 된다.Accordingly, when the corresponding cell block is selected (/ BSEL = L) and the sensing start signal is not activated (START = L), the latch units I2 and I3 output the L level voltage and the NMOS transistor N5. Is turned on, the L level voltage (ground voltage) is transmitted to the node ND1, and the potential of the node ND2 becomes L level.

해당 셀 블록이 선택되고(/BSEL=L), 센싱 개시신호가 인가되면(START=H), 래치부(I2, I3)는 H 레벨 전압을 출력하고, NMOS 트랜지스터(N5)가 닫히게 되어 노드(ND1)로부터 단절되며, 노드(ND2)의 전위는 H 레벨이 되므로, 노드(ND1)의 전위는 비교결과 래치부(400)의 출력에 따라 달라지게 된다.When the corresponding cell block is selected (/ BSEL = L) and the sensing start signal is applied (START = H), the latches I2 and I3 output the H level voltage, and the NMOS transistor N5 is closed so that the node ( Disconnected from ND1 and the potential of the node ND2 becomes H level, so that the potential of the node ND1 varies depending on the output of the latch unit 400 as a result of the comparison.

전압 비교부(300)는 비트라인(BIT, /BIT)에 공통으로 접속되는 RTO 노드의 전압을 감지하는 NMOS 트랜지스터(N1), 소정의 기준전압(REF)을 감지하는 NMOS 트랜지스터(N2), 안정적인 외부 바이어스 전압(Vext) 전달을 위한 PMOS 트랜지스터(P1, P2, P3, P4), 및 접지전압 전달을 제어하는 NMOS 트랜지스터(N3)로이루어지는 전류미러형 차동증폭기를 포함한다.The voltage comparator 300 includes an NMOS transistor N1 that senses a voltage of an RTO node commonly connected to the bit lines BIT and / BIT, an NMOS transistor N2 that senses a predetermined reference voltage REF, and is stable. PMOS transistors P1, P2, P3, and P4 for external bias voltage Vext, and NMOS transistor N3 for controlling ground voltage transfer.

RTO 노드의 전압(RTO)은 NMOS 트랜지스터(N1)의 게이트로 인가되며, 기준전압(REF)은 NMOS 트랜지스터(N2)의 게이트로 인가된다. NMOS 트랜지스터(N3)의 게이트에는 노드(ND1)가 접속되고, 소오스에는 NMOS 트랜지스터(N1, N2)의 드레인이 접속된다.The voltage RTO of the RTO node is applied to the gate of the NMOS transistor N1, and the reference voltage REF is applied to the gate of the NMOS transistor N2. The node ND1 is connected to the gate of the NMOS transistor N3, and the drains of the NMOS transistors N1 and N2 are connected to the source.

따라서, RTO 노드의 전압이 비교전압(REF) 보다 낮은 경우, 노드(ND3)로 L 레벨 전압을 전달하고, RTO 노드의 전압이 비교전압(REF) 보다 높은 경우 노드(ND3)로 H 레벨 전압을 전달한다.Therefore, when the voltage of the RTO node is lower than the comparison voltage REF, the L level voltage is transferred to the node ND3. When the voltage of the RTO node is higher than the comparison voltage REF, the H level voltage is transmitted to the node ND3. To pass.

비교결과 래치부(400)는 노드(ND3)의 전압을 인버터(P5, N4) 및 PMOS 트랜지스터(P6)로 이루어지는 래치에 래치시키며, 래치된 노드(ND4)의 전압 신호를 출력부(500)의 노드(ND1)로 출력한다.As a result of the comparison, the latch unit 400 latches the voltage of the node ND3 into a latch formed of the inverters P5 and N4 and the PMOS transistor P6, and the voltage signal of the latched node ND4 of the output unit 500. Output to node ND1.

따라서, RTO 노드의 전압이 비교전압(REF) 보다 낮은 경우, 노드(ND1)로 H 레벨 전압을 전달하고, RTO 노드의 전압이 비교전압(REF) 보다 높은 경우 노드(ND1)로 L 레벨 전압을 전달한다.Therefore, when the voltage of the RTO node is lower than the comparison voltage REF, the H level voltage is transmitted to the node ND1. When the voltage of the RTO node is higher than the comparison voltage REF, the L level voltage is transferred to the node ND1. To pass.

출력부(500)는 노드(ND1)의 전압을 반전시키는 인버터(I11), 인버터(I11)와 노드(ND2)의 전압을 NAND 연산하는 NAND 연산부(NAND2), 및 지연을 위한 인버터(I12, I13)를 포함한다.The output unit 500 includes an inverter I11 for inverting the voltage of the node ND1, a NAND calculator NAND2 for NAND-operating the voltages of the inverter I11 and the node ND2, and inverters I12 and I13 for delay. ).

따라서, 해당 셀 블록이 선택되고(/BSEL=L), 센싱 개시신호가 인가되면(START=H)에서는, 노드(ND2)의 전위는 H 레벨이 되어 출력(OUT)은 노드(ND1)의 전위에 의존하게 된다. 이때, RTO 노드의 전압(RTO)이기준전압(REF) 보다 높아 비교결과 래치부(400)에서 출력되는 비교결과가 L 레벨이면, 출력(OUT)은 L 레벨이 되며, RTO 노드의 전압(RTO)이 기준전압(REF) 보다 낮아 비교결과 래치부(400)에서 출력되는 비교결과가 H 레벨이면, 출력(OUT)은 H 레벨이 된다.Therefore, when the corresponding cell block is selected (/ BSEL = L) and the sensing start signal is applied (START = H), the potential of the node ND2 becomes H level and the output OUT becomes the potential of the node ND1. Will depend on. At this time, if the voltage RTO of the RTO node is higher than the reference voltage REF and the comparison result output from the comparison result latch unit 400 is L level, the output OUT becomes L level, and the voltage RTO of the RTO node If the comparison result output from the comparison result latch unit 400 is lower than the reference voltage REF at the H level, the output OUT is at the H level.

도 2 는 본 발명에 따른 RAS 시간 보상회로의 동작을 나타낸 파형도이다.2 is a waveform diagram showing the operation of the RAS time compensation circuit according to the present invention.

도시된 바와 같이, 먼저 블록 선택신호(/BSEL)가 L 레벨로 천이하여 당해 블록이 선택되었음을 알린다. 다음, /RAS 신호(도시생략)가 L 레벨로 되어 워드라인(WL)을 인에이블 시킨다. 다음, 센싱 개시신호(START)가 H 레벨로 인가되어 RTO 노드의 전압(RTO)을 센싱하여 기준전압(REF)과 비교한다. 리프레쉬 동작이 수행되어 비트라인 상의 전압이 증폭되면서 RTO 노드의 전압이 기준전압 레벨 이상이 되면(A), 내부의 지연시간 후 RAS 종료신호(OUT)가 L 레벨로 천이됨으로써 RAS 시간 종료를 나타낸다.As shown, first, the block select signal / BSEL transitions to the L level to indicate that the block is selected. Next, the / RAS signal (not shown) is brought to the L level to enable the word line WL. Next, the sensing start signal START is applied at the H level to sense the voltage RTO of the RTO node and compare it with the reference voltage REF. When the refresh operation is performed and the voltage on the bit line is amplified and the voltage of the RTO node is higher than the reference voltage level (A), after the internal delay time, the RAS end signal OUT transitions to the L level to indicate the end of the RAS time.

따라서, RTO 노드의 전압이 미리 정해진 기준 전압 이상이 되었을 때(A)를 센싱하여 RAS 시간을 종료시킴으로써 PVT 의 변화에 무관하게 RAS 시간을 보상시킬 수 있다.Therefore, when the voltage of the RTO node is greater than or equal to the predetermined reference voltage (A) by sensing the end of the RAS time, it is possible to compensate for the RAS time regardless of the change of the PVT.

본 발명에 따르면, RTO 노드의 전압을 감지하여 일정 비교전압 이상이 되었을 때를 감지하여 RAS 시간 종료를 알림으로써 PVT 변동으로 인한 RAS 시간의 변동없이 RAS 시간을 종료시킬 수 있다.According to the present invention, by detecting the voltage of the RTO node by detecting a certain comparison voltage or more, and notifies the end of the RAS time, it is possible to end the RAS time without a change in the RAS time due to the PVT change.

따라서, 전체 반도체 메모리장치의 동작을 안정화시키고 수율의 향상을 도모할 수 있다.Therefore, the operation of the entire semiconductor memory device can be stabilized and the yield can be improved.

Claims (3)

해당 메모리 셀 블록이 선택되고, 동작의 개시를 나타내는 개시신호가 활성화되었을 경우, 상기 개시신호를 래치시켜 출력하는 센싱 개시수단;Sensing start means for latching and outputting the start signal when a corresponding memory cell block is selected and a start signal indicating start of operation is activated; 상기 출력되는 개시신호에 기초하여 상기 RAS 시간 종료신호를 초기화시키는 초기화 수단;Initialization means for initializing the RAS timeout signal based on the output start signal; 상기 초기화 수단에 의해 초기화되며, RTO 노드의 전압과 미리 결정되는 기준전압을 비교하는 전압 비교수단;Voltage comparison means initialized by the initialization means and comparing a voltage of an RTO node with a predetermined reference voltage; 상기 초기화 수단에 의해 초기화되며, 상기 전압 비교수단의 비교 결과를 래치시키는 비교결과 래치수단; 및Comparison result latching means initialized by said initialization means and latching a comparison result of said voltage comparing means; And 상기 래치된 비교결과에 기초하여 상기 RAS 시간 종료신호를 출력하는 출력수단을 포함하는 것을 특징으로 하는 반도체 메모리장치의 RAS 시간 보상회로.And output means for outputting the RAS timeout signal based on the latched comparison result. 제 1 항에 있어서,The method of claim 1, 상기 전압 비교수단은 전류미러형 차동증폭기인 것을 특징으로 하는 반도체 메모리장치의 RAS 시간 보상회로.The voltage comparing means is a RAS time compensation circuit of a semiconductor memory device, characterized in that the current mirror type differential amplifier. 제 1 항에 있어서,The method of claim 1, 상기 비교전압은 상기 RTO 노드의 최대 전압 보다 낮은 것을 특징으로 하는 반도체 메모리장치의 RAS 시간 보상회로.The comparison voltage is a RAS time compensation circuit of the semiconductor memory device, characterized in that lower than the maximum voltage of the RTO node.
KR1020010086675A 2001-12-28 2001-12-28 Circuit for compensating ras time in semiconductor memory device KR20030056460A (en)

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