KR20030056397A - Apparatus for testing a memory - Google Patents

Abstract

PURPOSE: A memory test device is provided to effectively reduce the cost for the test by using a test logic circuit and repair analysis circuit. CONSTITUTION: A memory test device(304) for testing a memory(302) electrically connected to a test board includes a test logic circuit(306), a recovery analysis circuit(308), a de-multiplexor(312) and a multiplexor(314). In the memory test device(304), the test logic circuit(306) performs the functional test of the memory(302) and the recovery analysis circuit(308) stores the address occurring the failure after the test and performs the recovery analysis. The memory test device(304) is mounted on the test board.

Description

Memory test device {APPARATUS FOR TESTING A MEMORY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test apparatus, and more particularly, to a memory test apparatus of a BOST (Built-Out of Self-Test) type for reducing the test cost of a commercial memory.

As a way to reduce the cost of commercial memory test, a BIST (Built-In Self Test) method that applies test logic inside the memory is being attempted. 1 is a block diagram of a conventional semiconductor memory device to which the BIST method is applied for a memory test. As shown in FIG. 1, a memory unit 102 for storing data and a test unit 104 for performance test of the memory unit 102 are provided together in the memory 100. ) Provides a control signal Ctrl and a test clock signal Tck to the memory unit 102 for the test of the memory unit 102, and exchanges an address Addr and data DQ with each other. The test unit 104 receives the test input signal Tin, the test reset signal Trst, and the test clock signal Tck from the outside in series, and outputs the test output signal Tout to the outside.

The test unit 104 includes a test logic circuit 106, a repair analysis circuit 108, and a DFT (design for testability) 110. A tap controller 116, a demultiplexer 112, and a multiplexer 114 are further provided. The test logic circuit 106 performs a functional check of the memory unit 102. The recovery analysis circuit 108 stores the address where the failure occurred after the inspection by the test logic circuit 106 and performs a recovery analysis. The recovery analysis circuit 108 includes a register 109 for storing a defective address. The DFT 110 verifies the function of the test logic circuit 106 or the recovery analysis circuit 108 and outputs the result. The tap controller 116 serves as an apparatus for converting serial data into parallel data or converting parallel data into serial data to interface data input / output between the external unit and the test unit 104. That is, the test input signal Tin is provided from the outside into the memory 100 in the form of serial data in consideration of the pin overhead, which is converted into the parallel data form through the tap controller 116 to test logic circuit 106 or the DFT. Provided at 110. The demultiplexer 112 allows the test related signals generated by the tap controller 116 to be provided to the test logic circuit 106 in the memory test mode and to the DFT 110 in the TL test mode or the RA test mode. The test related signals provided to the DFT 110 are provided to the test logic circuit 106 in the TL test mode and to the recovery analysis circuit 108 in the RA test mode. The multiplexer 114 provides the output signal of the recovery analysis circuit 108 or the output signal of the DFT 110 to the tap controller 116 according to the mode, and the tap controller 116 converts these output signals into a serial signal. It outputs as a test output signal Tout.

However, when the BIST method is applied in this way, strictly speaking, there is a problem in that the number of dies per wafer is reduced since an area overhead necessarily exists. In particular, BIST, which can perform complex functional inspections with test equipment, can lead to more and more area overhead.Increasing memory performance increases the cost of testing without BIST and per-wafer with BIST. There may be a trade-off between reducing the number of dies. In addition, when BIST is applied to commercial memory, data input / output is performed through serial transmission considering pin overhead, which is not preferable in terms of reducing test cost by increasing test time.

The present invention has been proposed to solve this conventional problem, and an object thereof is to provide a memory test apparatus which is more effective in reducing test costs.

1 is a block diagram of a conventional semiconductor memory device to which the BIST method is applied for a memory test.

2 is a view for explaining how a memory test apparatus according to the present invention is used.

3 is a block diagram of a memory test apparatus according to an embodiment of the present invention.

In order to achieve the above object, the present invention provides a device for testing the performance of a memory electrically connected to a test board, comprising: a test logic circuit for performing a functional check of the memory; And a recovery analysis circuit for performing recovery analysis, wherein the recovery analysis circuit is mounted on the test board separately from the memory.

Preferably, the apparatus further includes means for verifying a function of the test logic circuit or the recovery analysis circuit according to a mode signal and outputting the result. Preferably, an address between the memory and the memory test device uses a bidirectional pad.

The BOST type memory test apparatus according to the present invention does not have to consider the area overhead which has always been a problem in the conventional BIST type, and solves the problem of reducing the number of dies when applying BIST to commercial memory. have. In addition, by controlling data input and output in parallel without considering pin overhead, the test time burden when applying BIST to commodity memory can be solved. In addition, when using an external low speed test apparatus, a clock multiplier may be applied inside or outside the BOST type test apparatus according to the present invention to overcome the speed limit problem of the external test apparatus, which may be generated by the high speed test apparatus. You can save money. You will also be able to perform test control and recovery analysis appropriate to the type of memory you are testing.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; In the drawings, the same reference numerals are used to refer to the same or similar components and signals for the sake of consistency of description.

2 is a view for explaining how the memory test apparatus according to the present invention is used. As shown in FIG. 2, the BOST (Built-Out of Self-Test) type test apparatus 206 according to the present invention is mounted on the test board 202 separately from the memory 204. The memory 204 is electrically connected to the test board 202 through a probe when in a chip state, and electrically connected to the test board 202 through a socket when in a packaged state. A test input signal Tin for the memory test is provided to the test apparatus 206, and the test result is output from the test apparatus 206 as the test output signal Tout.

3 is a block diagram of a memory test apparatus according to an embodiment of the present invention. As shown in FIG. 3, the memory 302 and the test apparatus 304 are divided separately, and as described with reference to FIG. 2, a signal for a test may be received via the test board 202 of FIG. 2. Give and take For testing the memory 302, the test apparatus 304 provides a control signal Ctrl and a clock signal Tck to the memory 302, and the test apparatus 304 and the memory 302 are address signals Addr. Send and receive data signal (DQ). Since the test device 304 is implemented outside the memory 302 and does not need to consider pin overhead, data is exchanged in parallel with the outside. Therefore, it does not need a tap controller that performs an interface for data input and output between the test device and the outside. The test device 304 receives a test reset signal Trst, a test clock signal Tck, a test input signal Tin, and a mode signal from the outside, and receives a test output signal Tout indicating a test result. Create and output to the outside.

As shown in FIG. 3, the test apparatus 304 includes a test logic circuit 306 and a recovery analysis circuit 308. Further, a DFT 310, a demultiplexer 312, and a multiplexer 314 are further provided. First, the test logic circuit 306 performs a functional check of the memory 302. The recovery analysis circuit 308 stores an address where a failure has occurred as a result of the test by the test logic circuit 306, and performs a recovery analysis. The recovery analysis circuit 308 includes a register 309 to store the defective address. The DFT 310 is responsible for verifying the function of the test logic circuit 306 or the recovery analysis circuit 308 and outputting the results. The address is then transferred between the memory 302 and the memory test device 306 using a bidirectional pad.

Next, the operation according to the mode will be described in detail. First, when the mode signal (00) is "00", the test apparatus 304 turns off all operations. When the mode signal is "11", the test logic circuit 306 verifies the function of the memory 302 according to the input condition of the test input signal Tin, and if the verified result is bad, corrects the corresponding address. Sent to recovery analysis circuit 308. The recovery analysis circuit 308 stores this address in the register 309, performs a recovery analysis, and then outputs it externally as a test output signal Tout. When the mode signal mode is "01", the DFT block 310 is enabled, and the function of the test logic circuit 306 is verified according to the input condition of the test input signal Tin later, and the result is checked. It outputs as a test output signal Tout. If the mode signal is "10", the DFT block 310 is also enabled, and the function of the recovery analysis circuit 308 is verified according to the input condition of the test input signal Tin. The result is output as a test output signal Tout.

The embodiments described herein are merely intended to enable those skilled in the art to easily understand and practice the present invention, and are not intended to limit the scope of the present invention. Therefore, those skilled in the art should note that various modifications or changes are possible within the scope of the present invention. The scope of the invention is defined in principle by the claims that follow.

The BOST type memory test apparatus according to the present invention does not have to consider the area overhead which has always been a problem in the conventional BIST type, and solves the problem of reducing the number of dies when applying BIST to commercial memory. have. In addition, by controlling data input and output in parallel without considering pin overhead, the test time burden when applying BIST to commodity memory can be solved. In addition, when using an external low speed test apparatus, a clock multiplier may be applied inside or outside the BOST type test apparatus according to the present invention to overcome the speed limit problem of the external test apparatus, which may be generated by the high speed test apparatus. You can save money. You will also be able to perform test control and recovery analysis appropriate to the type of memory you are testing.

Claims (3)

A device for testing the performance of a memory electrically connected to a test board, A test logic circuit for performing a functional check of the memory; A recovery analysis circuit for storing an address where a failure occurs after the inspection and performing recovery analysis; And a memory test apparatus mounted on the test board separately from the memory. The method of claim 1, And means for verifying a function of the test logic circuit or the recovery analysis circuit according to a mode signal, and outputting the result. The method of claim 1, And the address between the memory and the memory test device uses a bidirectional pad.