KR20030054199A - Method for spice simulation of compiled memory - Google Patents

Abstract

PURPOSE: A method for SPICE(Simulation Program with Integrated Circuit Emphasis) simulation of a compiled memory is provided to automate the SPICE simulation by classifying memory cells having identical operation patterns therewith and describing an SPICE input file of a corresponding memory. CONSTITUTION: Complied memories are classified according to memories having identical operation patterns(21). Stimulus signals being applied to each memory are described on a file being prepared by a high-level language(22). A source file is converted into a SPICE input file(23). The converted SPICE input file is used for automatically generating stimulus signals in a SPICE simulation(24). Thus, stimulus signals to be applied to each input pin in a SPICE simulation are automatically created.

Description

Method for SPICE simulation of compiled memory

TECHNICAL FIELD The present invention relates to integrated circuit design, and more particularly, to a method for automating the characterization of compiled memory cells by automatically describing an input file for SPICE simulation of an integrated circuit.

Integrated circuit design may include large and complex circuits with more than 500,000 transistors. The design of such a circuit is greatly simplified by the use of semi-custom design techniques in arranging the transistors to form blocks or cells and construct cell libraries. Each cell or block constructed by the above technique performs functions such as flip-flops, multiplexers, inverters, and the like. Each cell or logic function consists of a cell library in which cells selected from the cell library are interconnected to form an integrated circuit.

Memory having such a configuration is called compiled memory or parameterized memory, which was designed, automated and tested by K. Ogawa, M. Kohno and F. Kitamura in 1998. in Europe, 1998, Proceedings, pp. 15-20, "PASTEL: a parameterized memory characterization system."

Many integrated circuit manufacturers now use computer simulation programs to verify the performance of integrated circuits and their power dissipation to reduce manufacturing costs. In particular, integrated circuits divided into cells or blocks are characterized by using a simulation program such as Simulation Program with Integrated Circuit Emphasis (SPICE).

Such cell characterization is for building a cell library, and SPICE simulation for various timing paths defined in the cell library is essential.

The internal structure of a compiled memory cell is divided into a number of sub-blocks that differ in function depending on the design architecture. The overall operation of the compiled memory cell will form various patterns according to the successive combination of outputs of each sub-block. Since the initial condition of each sub-block constituting the inside of the memory cell varies according to the read, write, and standby modes of the memory, characterization of the cell is performed. The method of SPICE simulation becomes complicated. In addition, since a compiled memory cell is divided into hundreds according to its type and capacity, a problem of prolonging the library development period is caused if SPICE simulation is not automated.

Accordingly, an aspect of the present invention is to provide a method for automating SPICE simulation by classifying memory cells having the same operation pattern and describing the SPICE input file of the corresponding memory.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of the drawings is provided.

1 is a block diagram showing the structure of a compiled memory.

FIG. 2 is a timing diagram of signals related to an operation of the compiled memory illustrated in FIG. 1.

3 is a flowchart showing a simulation method according to a preferred embodiment of the present invention, which automatically generates the stimulus signals shown in FIG. 2 during SPICE simulation.

4 is a diagram illustrating an example of a source file for implementing the SPICE input file illustrated in FIG. 3.

<Description of Symbols for Main Parts of Drawings>

10: compiled memory device 11: controller

13: row decoder 14: column decoder

15: memory cell array 16: sense amplifier and I / O circuit

According to an aspect of the present invention, there is provided a SPICE simulation method of a compiled memory, including: (a) dividing the compiled memories into operation patterns; (b) describing respective stimulus signals applied to the respective memories on a file written in a predetermined language; (c) converting the file described in step (b) into a SPICE input file; And (d) automatically generating stimulus signals applied to each input pin through the file converted in the step (c) during the SPICE simulation of the memory.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a block diagram illustrating a structure of a compiled memory 10. Referring to FIG. 1, the compiled memory 10 includes a controller 11, a row decoder 13, a column decoder 14, a memory cell array 15, and a sense amplifier and an I / O circuit 16. do.

The control circuit 11 selects an operation mode according to control signals WEN and CSN applied from the outside to control the operation of the compiled memory 10 as a whole. Then, the row address signal and the column address signal are generated in accordance with the external address signals A [0], A [1], ..., A [i] and applied to the row and column decoders 13 and 14.

The memory cell array 15 includes a plurality of memory cells each storing one bit of data, each memory cell being arranged at a predetermined address determined by the row address and column address.

The row decoder 13 specifies the corresponding row address of the memory cell array 15 in response to the row address signal, and the column decoder 14 specifies the corresponding column address of the memory cell array 15 in response to the column address signal. do.

The sense amplifier and I / O circuit 16 receives data DIN input from the outside and writes them to the selected memory cell in accordance with control signals WEN and OEN applied from the outside. In addition, an operation of outputting read data DOUT read from the selected memory cell to the outside is performed.

FIG. 2 is a timing diagram of signals related to an operation of the compiled memory 10 shown in FIG. 1. In particular, FIG. 2 illustrates a clock signal CK when measuring propagation delays from an input of a clock signal CK to a data output DOUT among timing characteristics of a compiled memory cell. And stimulus signals that must be applied to the memory cell 10 to induce a switching operation of the data output DOUT (e.g., CK, WEN, CSN, OEN, DIN, A [0], A [1], ..., A [i]).

In order to measure the propagation delay from the input of the clock signal CK to the data output DOUT, as shown in FIG. 2, the first rising time of the clock signal CK input after the delay of 30n is determined as the trigger point ( The trigger point is used to simulate and measure up to the point when the data output (DOUT) first rises. In order to measure such a delay, in the memory write mode, the bit cell indicated by the address is initialized to a high or low level, and then the memory mode is changed to the write mode so that the clock signal CK and data output ( Switching must be considered.

3 is a flowchart showing a simulation method according to a preferred embodiment of the present invention, which automatically generates the stimulus signals shown in FIG. 2 during SPICE simulation. Referring to FIG. 3, first, the compiled memories are classified for each memory having the same operation pattern (step 21). Subsequently, the stimulus signals applied to each memory are each described on a file written in a high-level language such as the C programming language (step 22). The source file constructed in step 22 is converted into a SPICE input file (step 23), and the converted SPICE input file is used to automatically generate stimulus signals during the SPICE simulation (step 24). This automatically generates stimulus signals that must be applied to each input pin during SPICE simulation.

FIG. 4 is a diagram illustrating an example of a source file for implementing the SPICE input file illustrated in FIG. 3.

The source file shown in FIG. 4 has previously set up a method of defining and measuring input stimulus for a timing pattern constituting a library at the time of memory cell characterization. Setup is an external script. The script description content in the previously reserved format is composed of a high-level language such as a C language program, and the internal content is translated into a SPICE input file according to the intended purpose. .

In the script contents shown in FIG. 4, portions marked as 1 or 0 represent actual waveforms of the stimulus signal, and 1 and 0 represent high state (VDD) and low state (GROUND) values of the waveform, respectively. Ultimately, it refers to the voltage source applied to the input pin of each cell in the SPICE input file.

For example, when one bit of data denoted as 1 or 0 has a value of high state (VDD) or low state (GROUND) for 5n, "CK: 0 1 0 1 0 1 0 1" shown in FIG. Means that 4 pulse signals of 10n period are applied from 0n to 40n to the clock input pin of the cell.

According to the method of describing a stimulus signal such as Io, for example, the WEN signal of FIG. 2 is described as "WEN: 0 0 1 1 0 0 1 1 0" as shown in FIG. 4 to write and read the memory. Can be used for operation. According to the description of the stimulus signal (for example, the WEN signal), the memory performs a data write operation during the 0 to 10n and 20 to 30n sections, and performs a data read operation during the 10 to 20n and 30 to 40n sections. Will be performed.

According to the description of the SPICE input file according to the present invention, stimulus signals to be applied to each input pin for the operation of the memory intended by the designer are automatically generated in the SPICE simulation. As a result, the efficiency of the SPICE simulation is increased, which enables efficient cell characterization and significantly shortens the library development time for the compiled memory.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the method for automatically describing a simulation input file according to the present invention describes a SPICE input file by classifying memory cells having the same operation pattern, and using the SPICE input file as an input file for SPICE simulation. As a result, efficiency of SPICE simulation is increased, cell characterization is efficiently performed, and a library development period for compiled memory is greatly shortened.

Claims (4)

(a) dividing the compiled memories into operation patterns; (b) describing respective stimulus signals applied to the respective memories on a file written in a predetermined language; (c) converting the file described in step (b) into a SPICE input file; And and (d) automatically generating stimulus signals applied to each input pin through the file converted in the step (c) during the SPICE simulation of the memory. The method of claim 1, The file created in step (b) is an external script for setting up a method of defining and measuring input stimulus signals for timing patterns constituting the library of the compiled memory cell. The method of claim 1, And the stimulus signals described in step (b) are represented as binary data having a high or low value for a predetermined period. The method of claim 1, SPICE simulation method, characterized in that the file created in the step (b) is written in a high-level language including the C language.