KR20030054176A - A improvement method of ability packing for copper line - Google Patents
A improvement method of ability packing for copper line Download PDFInfo
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- KR20030054176A KR20030054176A KR1020010084300A KR20010084300A KR20030054176A KR 20030054176 A KR20030054176 A KR 20030054176A KR 1020010084300 A KR1020010084300 A KR 1020010084300A KR 20010084300 A KR20010084300 A KR 20010084300A KR 20030054176 A KR20030054176 A KR 20030054176A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
Abstract
Description
본 발명은 구리배선의 패키징 능력을 향상시키는 방법에 관한 것으로, 특히 듀얼 다마신 공정에 의해 형성된 구리배선의 패드 표면에만 니켈을 선택적으로 무전해도금함으로서 구리배선의 패키징 능력을 향상시키는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for improving the packaging capability of copper wiring, and more particularly, to a method for improving the packaging capability of copper wiring by selectively electroless nickel only on the pad surface of the copper wiring formed by the dual damascene process. .
구리배선은 기존의 알루미늄 합금(Al-0.5%Cu) 배선에 비하여 여러 가지 장점을 갖는데, 대표적으로 낮은 전기저항과 높은 신뢰성을 들 수 있다. 그러나 구리배선에서 대표적인 단점으로는 구리의 자연산화 현상과 유전체 내에서는 빠른 확산 현상이 나타난다는 것이다.Copper wiring has a number of advantages over conventional aluminum alloy (Al-0.5% Cu) wiring, typically low electrical resistance and high reliability. However, the main disadvantages of copper wiring are the natural oxidation of copper and the rapid diffusion in the dielectric.
특히. 구리 패드의 자연산화 현상은 구리배선 자체의 신뢰성을 저하시킬 뿐만 아니라, 패키징시에 본딩 능력(bonding ability) 특성을 열화시킨다. 그러므로 구리배선으로 제작된 소자를 상온 또는 고온에서 장시간 사용하는 경우에 대비하여 구리 패드의 자연산화를 피하기 위한 조치를 수행할 필요가 있다.Especially. The natural oxidation of the copper pads not only lowers the reliability of the copper wiring itself, but also degrades the bonding ability characteristics during packaging. Therefore, it is necessary to take measures to avoid the natural oxidation of the copper pad in case of using the device manufactured by the copper wiring for a long time at room temperature or high temperature.
종래에는 구리 패드의 자연산화 현상을 막기 위해 보호막을 증착한 후, 노광 및 현상공정을 이용하여 식각공정을 통해 패드부위만 오픈시킨다. 그리고 본딩 레이어 역할을 수행하는 알루미늄 합금층을 웨이퍼 전면에 스퍼터링 방법으로 증착한 후, 노광 및 현상공정을 이용하여 식각 공정을 진행한다.Conventionally, after the protective film is deposited to prevent natural oxidation of the copper pad, only the pad portion is opened through an etching process using an exposure and development process. The aluminum alloy layer, which serves as a bonding layer, is deposited on the entire surface of the wafer by a sputtering method, followed by an etching process using an exposure and development process.
이어, 최종적인 알루미늄 본딩 레이어를 구리 패드의 표면에만 형성하였다. 즉, 구리 패드만을 알루미늄 합금을 이용하여 덧씌우는 방법이다.The final aluminum bonding layer was then formed only on the surface of the copper pads. In other words, only the copper pad is overlaid using an aluminum alloy.
그러나 상기와 같은 종래의 구리 패드의 자연산화 현상을 막기 위한 방법은 종래에 널리 알려진 방법을 이용하므로 그리 어려운 작업은 아니지만 일련의 단위 공정이 복잡하고, 제조비용이 많이 소요되는 문제점이 있었다.However, the method for preventing the natural oxidation of the conventional copper pad as described above is not a difficult task because it uses a conventionally known method, but a series of unit processes are complicated, there is a problem that a lot of manufacturing cost.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 구리배선의 패드 표면에만 니켈을 선택적으로 무전해도금함으로서 패드 표면에서의 구리의 자연산화 현상을 방지하여 패드의 본딩 능력을 향상시킬 수 있는 구리배선의 패키징 능력을 향상시키는 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems by selectively electroless nickel plating only on the pad surface of the copper wiring to prevent the natural oxidation of the copper on the pad surface to improve the bonding ability of the pad It is an object of the present invention to provide a method for improving the packaging capability of wiring.
도 1a 내지 도 1d는 본 발명의 구리배선의 패키징 능력을 향상시키는 방법을 나타낸 공정 단면도1A to 1D are cross-sectional views illustrating a method of improving the packaging capability of the copper wiring of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 : 하부 구리배선 12 : 층간 절연막11 lower copper wiring 12 interlayer insulating film
13 : 트랜치 14 : 비아홀13: trench 14: via hole
15 : 상부 구리배선 16 : 캡핑층15: upper copper wiring 16: capping layer
17 : 보하막 18 : 니켈층17: bottom film 18: nickel layer
상기와 같은 목적을 달성하기 위한 본 발명의 구리배선의 패키징 능력을 향상시키는 방법은 하부 구리배선을 형성하고, 상기 하부 구리배선상에 층간 절연막을 형성하는 단계와, 상기 층간 절연막을 소정깊이로 소정부분 식각하여 트랜치를 형성하고, 상기 트랜치내의 상기 하부 구리배선 표면이 노출이 되도록 상기 층간 절연막을 선택적으로 식각하여 복수개의 비아홀을 형성하는 단계와, 상기 결과물 상부에 상부 구리배선을 증착하고 평탄화한 후, 캡핑층을 형성하는 단계와, 상기 상부 구리배선의 패드부위가 노출되도록 상기 캡핑층을 선택적으로 식각하여 보호막을 형성하는 단계와, 상기 노출된 상부 구리배선 패드 표면에만 무전해도금 방법에 의해 니켈을 형성하는 단계를 포함하는 것을 특징으로 한다.The method for improving the packaging capability of the copper wiring of the present invention for achieving the above object comprises the steps of forming a lower copper wiring, forming an interlayer insulating film on the lower copper wiring, the predetermined interlayer insulating film to a predetermined depth Forming a trench by partial etching, selectively etching the interlayer insulating layer to expose the lower copper wiring surface in the trench to form a plurality of via holes, and depositing and planarizing an upper copper wiring on the resultant Forming a capping layer, selectively etching the capping layer so that the pad portion of the upper copper wiring is exposed, and forming a protective film; and nickel by the electroless plating method only on the exposed upper copper wiring pad surface. It characterized in that it comprises a step of forming.
또한, 상기 트랜치와 비아홀을 형성한 후, 상기 하부 구리배선 표면에 생성된 구리 자연산화막을 환원시키는 단계를 더 포함하는 것이 바람직하다.In addition, after forming the trench and the via hole, it is preferable to further include the step of reducing the copper native oxide film formed on the surface of the lower copper wiring.
또한, 상기 구리 자연산화막을 환원시키는 방법은 질소/수소 혼합가스 분위기에서 급속열처리 및 플라즈마 처리하는 것이 바람직하다.In addition, the method of reducing the copper natural oxide film is preferably a rapid heat treatment and plasma treatment in a nitrogen / hydrogen mixed gas atmosphere.
또한, 상기 캡핑층은 SiN, 실리콘 질화막중 하나이고, PECVD 방법에 의해 형성되는 것이 바람직하다.In addition, the capping layer is one of SiN and silicon nitride film, it is preferably formed by a PECVD method.
또한, 상기 상부 구리배선은 상기 비아홀 및 하부 구리배선 표면을 세정한 후, 구리 배리어 및 씨드층을 이온화된 PVD 방법에 의해 증착하는 것이 바람직하다.In addition, the upper copper interconnection may be cleaned by cleaning the via holes and the lower copper interconnection surface, and then depositing a copper barrier and seed layer by ionized PVD.
또한, 상기 세정방법은 Ar RF 플라즈마, Ar/H RF 플라즈마 처리법중 하나이고, 상기 구리배리어는 Ta, TaN 중 하나인 것이 바람직하다.In addition, the cleaning method is one of the Ar RF plasma, Ar / H RF plasma treatment method, the copper barrier is preferably one of Ta, TaN.
또한, 상기 보호막의 두께는 3000∼10000Å인 것이 바람직하다.Moreover, it is preferable that the thickness of the said protective film is 3000-10000 kPa.
또한, 상기 니켈의 두께는 1000∼4000Å인 것이 바람직하다.Moreover, it is preferable that the thickness of the said nickel is 1000-4000 kPa.
이하, 첨부된 도면을 참조하여 본 발명의 구리배선의 패키징 능력을 향상시키는 방법에 대하여 보다 상세히 설명하기로 한다.Hereinafter, a method of improving the packaging capability of the copper wiring of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명의 구리배선의 패키징 능력을 향상시키는 방법을 나타낸 공정 단면도이다.1A to 1D are cross-sectional views illustrating a method of improving the packaging capability of the copper wiring of the present invention.
도 1a에 도시한 바와 같이 반도체 기판(도면에 도시하지 않았음)상에 하부 구리배선(11)을 형성한 후, 상기 하부 구리배선(11)상에 층간 절연막(12)을 형성한다.As shown in FIG. 1A, after forming the lower copper wiring 11 on the semiconductor substrate (not shown), the interlayer insulating film 12 is formed on the lower copper wiring 11.
이어, 상기 층간 절연막(12)을 소정깊이로 소정부분 식각하여 트랜치(13)를 형성한 후, 듀얼 다마신(dual damascene) 공정을 이용하여 상기 트랜치(13)내의 상기 하부 구리배선(11) 표면이 선택적으로 노출되도록 복수개의 비아홀(14)을 형성한다.Subsequently, the interlayer insulating layer 12 is etched to a predetermined depth to form a trench 13, and then a surface of the lower copper wiring 11 in the trench 13 is formed by using a dual damascene process. A plurality of via holes 14 are formed to be selectively exposed.
도 1b에 도시한 바와 같이 상기 트랜치(13)와 비아홀(14) 및 하부 구리배선(11)의 표면을 세정한 후, 구리 배리어 및 씨드(seed)층을 이온화된 PVD 방법에 의해 증착한다. 이때, 상기 세정방법은 Ar RF 플라즈마(Radio Frequency Plasma) 또는 Ar/H2RF 플라즈마 처리법 등이 있다. 그리고 상기 구리 배리어은 Ta 또는 TaN 등을 사용하며, 상기 이온화된 PVD 방식은 기존의 스퍼터닝 방법에 비해스텝 커버리지를 크게 향상시킬 수 있는 방법이다.After cleaning the surface of the trench 13, the via hole 14, and the lower copper wiring 11 as shown in FIG. 1B, a copper barrier and seed layer is deposited by an ionized PVD method. At this time, the cleaning method may include Ar RF plasma (Radio Frequency Plasma) or Ar / H 2 RF plasma treatment. In addition, the copper barrier uses Ta or TaN, and the ionized PVD method is a method capable of greatly improving step coverage compared to the conventional sputtering method.
이어, 상기 트랜치(13) 및 비아홀(14)에 전해도금 방법에 의해 구리층을 매립하고, CMP 공정을 통해 평탄화하여 상부 구리배선(15)을 형성한 후, 표면을 세정한다,Subsequently, the copper layer is embedded in the trench 13 and the via hole 14 by an electroplating method, and planarized through a CMP process to form the upper copper wiring 15, and then the surface is cleaned.
그리고 상기 상부 구리배선(15) 표면에 생성된 구리 자연산화막(도면에 도시하지 않았음)을 환원시킨 후, 공기중에 노출시키지 않는 채로 캡핑층(16)을 PECVD(Plasma Enhanced Chemical Vapor Deposition) 방법에 의해 형성한다.After the reduction of the copper native oxide film (not shown) formed on the surface of the upper copper wiring 15, the capping layer 16 is subjected to PECVD (Plasma Enhanced Chemical Vapor Deposition) without exposure to air. By forming.
이때, 상기 캡핑층(16)은 SiN 또는 실리콘 질화막이다. 그리고 상기 캡핑층(16)은 구리배선내의 구리원자가 상부 절연층으로 확산되는 것을 막는 역할을 한다. 즉, 구리원자의 확산은 배선 사이의 누설전류를 유발하기 때문이다.In this case, the capping layer 16 is SiN or silicon nitride film. The capping layer 16 serves to prevent the copper atoms in the copper wiring from diffusing into the upper insulating layer. That is, diffusion of copper atoms causes leakage current between wirings.
한편, 상기 구리 자연산화막의 환원방법은 질소/수소가스의 혼합분위기에서 RTP(Rapid Thermal Process) 열처리하거나 플라즈마 처리한다.On the other hand, the reduction method of the natural copper oxide film is RTP (Rapid Thermal Process) heat treatment or plasma treatment in a mixed atmosphere of nitrogen / hydrogen gas.
도 1c에 도시한 바와 같이 상기 캡핑층(16)상에 보호막(17)을 형성한 후, 상기 상부 구리배선(15)의 패드부위가 노출되도록 식각공정을 이용하여 상기 보호막(17)과 캡핑층(16)을 선택적으로 식각한다.As shown in FIG. 1C, after the protective layer 17 is formed on the capping layer 16, the protective layer 17 and the capping layer are formed by using an etching process to expose the pad portion of the upper copper wiring 15. Etch (16) selectively.
이때, 상기 보호막(17)의 두께는 3000∼10000Å이며, 실리콘 산화막, 실리콘 질화막 중 하나를 사용한다.At this time, the thickness of the protective film 17 is 3000 to 10000 kPa, and one of a silicon oxide film and a silicon nitride film is used.
여기서, 상기 캡핑층(16)이 실리콘 질화막일 경우 상기 보호막(17)은 실리콘 산화막이 적당하다. 왜냐하면, 실리콘 질화막만을 두껍게 증착할 경우 스트레스(stress)가 과도해져, 보호막(17)에 손상(defect)이 생성되기 때문이다.Here, when the capping layer 16 is a silicon nitride film, the protective film 17 is preferably a silicon oxide film. This is because, when only a silicon nitride film is thickly deposited, stress is excessive and defects are generated in the protective film 17.
도 1d에 도시한 바와 같이 상기 노출된 상부 구리배선(15)의 패드부위에 무전해도금 방법을 이용하여 니켈층(18)을 선택적으로 형성한 후, 세정 공정 및 건조공정을 진행한다.As shown in FIG. 1D, the nickel layer 18 is selectively formed on the exposed pad portion of the upper copper wiring 15 by using an electroless plating method, and then a cleaning process and a drying process are performed.
상기 니켈층(18)은 무전해도금 용액내에서의 니켈 이온의 환원반응에 의해 형성되는데, 웨이퍼의 앞면을 무전해도금 용액에 수분간 담그면 된다.The nickel layer 18 is formed by a reduction reaction of nickel ions in the electroless plating solution, and the front surface of the wafer may be immersed in the electroless plating solution for several minutes.
이때, 상기 무전해도금 용액은 황산니켈 26g/ℓ(금속염 : 니켈이온 공급원 역할), 차아인산소다 16g/ℓ(환원제 : 전자공급원 역할), 아세트산소다 26g/ℓ와 구연산소다 15g/ℓ(착화제 : 무전해도금 용액의 수명 연장을 목적으로 첨가하는 성분), 티오뇨소 3∼5ppm(안정제 : 용액의 pH 안정성 확보)으로 구성된다. 그리고 도금 온도는 80∼100℃이고, pH는 4.5∼5.5이다.At this time, the electroless plating solution is nickel sulfate 26g / ℓ (metal salt: serves as nickel ion source), sodium hypophosphite 16g / ℓ (reducing agent: serves as electron source), sodium acetate 26g / ℓ and sodium citrate 15g / ℓ (complexing agent) : A component added for the purpose of extending the life of an electroless plating solution), and 3 to 5 ppm of thionyo (stabilizer: ensuring pH stability of the solution). And plating temperature is 80-100 degreeC, pH is 4.5-5.5.
상기 무전해도금 방법에 의해 형성된 니켈층(18)의 두께는 1000∼4000Å이다.The thickness of the nickel layer 18 formed by the electroless plating method is 1000 to 4000 mm.
이상에서 설명한 바와 같이 본 발명의 구리배선의 패키징 능력을 향상시키는 방법은 구리배선 패드의 자연산화를 방지할 수 있고, 패키징시 구리배선 패드의 본딩 능력 특성을 향상시킬 수 있는 효과가 있다.As described above, the method of improving the packaging capability of the copper wiring of the present invention can prevent the natural oxidation of the copper wiring pad and have the effect of improving the bonding capability of the copper wiring pad during packaging.
또한, 종래의 알루미늄 본딩 레이어에 비해 단위공정을 감소시킬 수 있으므로 공정시간을 단축할 수 있다.In addition, since the unit process can be reduced compared to the conventional aluminum bonding layer, the process time can be shortened.
그리고 신뢰성을 향상시킬 수 있고, 니켈은 구리에 비해 접촉저항이 낮은 금속이므로 전기적 특성, 물리적 특성을 향상시킬 수 있다.In addition, reliability can be improved, and nickel is a metal having lower contact resistance than copper, thereby improving electrical and physical properties.
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| KR100909131B1 (en) * | 2007-05-16 | 2009-07-23 | 주식회사 동부하이텍 | Method for forming semiconductor device and device suitable therefor |
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| KR100909131B1 (en) * | 2007-05-16 | 2009-07-23 | 주식회사 동부하이텍 | Method for forming semiconductor device and device suitable therefor |
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