KR20030050594A - Method for forming dual damascene pattern and method for fabricating multi-metal interconnect by using the same - Google Patents

Abstract

PURPOSE: A method for forming a dual damascene pattern and a method for manufacturing a multilayer metal line using the same are provided to be capable of preventing the deterioration of device characteristics due to a plurality of etching processes by simultaneously forming a line and a via hole when carrying out the following trench process without an additional via etching process. CONSTITUTION: After forming the first etch stop layer(33) on the first interlayer dielectric(32) by carrying out an ion implantation, a hole mask is formed on the first etch stop layer. After implanting doped dopants into the exposed portion of the first etch stop layer through the hole mask, the hole mask is then removed. The second interlayer dielectric(36) and the second etch stop layer(37) are sequentially formed on the resultant structure. After forming a line mask(38) on the resultant structure, a line pattern and a hole pattern are simultaneously formed by carrying out a single etching process at the resultant structure using the line mask as an etching mask.

Description

Method for forming dual damascene pattern and method for fabricating multi-metal interconnect by using the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a multi-layer metal wiring by a dual damascene process.

The higher the integration, the more damaging the application of an insulating film with a low dielectric constant (low-k) as an Inter Metal Dielectric (IMD) to reduce the wiring capacitance affecting RC delay, AC power, and crosstalk. Is being developed.

In general, the damascene process forms a trench by etching an insulating film and fills a wiring film in the trench, and a self-aligned dual damascene etching process in which vias are aligned under the trench is mainly used. It is used.

In the self-aligned dual damascene process, the insulating film is etched by photo and etching to form a trench, and the trench is filled with a conductive material such as tungsten (W), aluminum, or copper, and the conductive material other than the necessary wiring is etched back. It is a technique for forming wiring in the trench shape first formed by removing using techniques such as etching or chemical mechanical polishing (CMP).

The self-aligned dual damascene technology is mainly used for forming bit lines, word lines, and metal wirings of DRAMs, and the upper metal wirings and the upper metals, which are line patterns, especially in multilayer metal wirings. Not only can the via pattern, which is a hole pattern for connecting the wiring and the lower metal wiring, to be formed at the same time, but also the step difference caused by the metal wiring can be removed, thereby facilitating subsequent processes.

1A to 1D are cross-sectional views illustrating a method of forming a multilayer metal wiring by a self-aligned dual damascene process according to the prior art.

As shown in FIG. 1A, after forming the lower metal wiring 11, the first interlayer insulating film 12 is formed on the entire surface including the lower metal wiring 11, and then the first interlayer insulating film 12 is planarized. The first nitride film 13 is formed on the entire surface of the resultant product.

Next, after the photoresist is coated on the first nitride film 13 and patterned by exposure and development to form the via mask 14, the first nitride film 13 is etched using the via mask 14. At this time, the etching portion of the first nitride film 13, that is, the hole 13a, is equal to the width of the via hole to be formed later.

As shown in FIG. 1B, after the via mask 14 is removed, the second interlayer insulating film 15 and the second nitride film 16 are sequentially formed on the entire surface including the first nitride film 13 having the holes 13a formed therein. do.

Next, the photoresist film is again applied on the second nitride film 16 and patterned by exposure and development to form the trench mask 17. At this time, the trench mask 17 has a larger line width than the via mask 14 described above.

As shown in FIG. 1C, the second nitride film 16 is etched first using the trench mask 17 of FIG. 1B as an etch mask, and the second interlayer insulating film 15 is subsequently etched so that the subsequent upper metal wiring line ( to form a trench 18 for the line.

At this time, when the second interlayer insulating layer 15 is etched, the etching stops in the first nitride layer 13 and the first interlayer insulating layer 12 is etched through the hole 13a of the first nitride layer 13. At the same time the via hole 19 is formed.

When the via hole 19 is formed, the first interlayer insulating layer 12 is etched until the lower metal wiring 11 is exposed.

Next, the trench mask 17 is removed. Since the trench mask 17 uses a conventional photoresist film, it is removed by a photoresist strip process.

In addition, a cleaning process is performed to remove by-products after the photosensitive film strip process, and solvent solutions such as EKC, ACT, and R502 are commonly used.

Next, as shown in FIG. 1D, a copper film is deposited on the entire surface, and chemical mechanical polishing (CMP) is performed until the surface of the second nitride film 16 is exposed to be buried in the trench 18 and the via hole 19. The upper metal wiring 20 is formed. Here, when the upper metal wiring 20 is formed, vias 20a for connection with the lower metal wiring 11 are simultaneously formed.

In the above-described prior art, a nitride film is used as an etch stop film and an oxide film is used as an interlayer insulating film. In the dual damascene process, a trench is etched again after forming a hole by a via hole mask. As a result, the interlayer insulating film is attacked and there is a problem that the characteristics of the metal wiring become unstable.

The above problem occurs even when dual damascene patterns are formed, such as word lines and bit lines using the dual damascene process.

The present invention has been made to solve the problems of the prior art, a method of forming a dual damascene pattern suitable for preventing the deterioration of the characteristics of the device by a plurality of etching process during the dual damascene process and the formation of a multi-layer metal wiring using the same The purpose is to provide a method.

1a to 1d is a cross-sectional view of the manufacturing process of the multi-layered metal wiring by the dual damascene process according to the prior art,

2A to 2C are cross-sectional views illustrating a method of forming a dual damascene pattern according to an embodiment of the present invention;

3A to 3D are cross-sectional views illustrating a method of manufacturing a multilayer metal wiring by a dual damascene process to which an embodiment of the present invention is applied.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 first interlayer insulating film

33 undoped polysilicon film 34 hole mask

35 doped polysilicon film 36 second interlayer insulating film

37: nitride film 38: line mask

39: trench 40: hole

A method of forming a dual damascene pattern of the present invention for achieving the above object comprises the steps of forming a first etch stop layer in which the etch rate is increased by ion implantation on the first interlayer insulating layer, and a hole mask on the first etch stop layer Forming an ion, implanting an impurity into a portion of the first etch stop layer exposed by the hole mask, removing the hole mask, and removing the hole mask on the entire surface including the first etch stop layer into which the impurity is implanted. Forming a second interlayer insulating film and a second etch stop film in sequence, forming a line mask having a line width larger than that of the hole mask on the second etch stop film, and using the line mask as an etch mask to stop the second etch stop. Etching a film and the second layer insulating film to form a line pattern and simultaneously forming a hole pattern penetrating the first interlayer insulating film. It features a load.

In addition, the method of manufacturing a multilayer metal wiring of the present invention includes the steps of forming a first interlayer insulating film on a first metal wiring layer, forming a undoped polysilicon film on the first interlayer insulating film, on the undoped polysilicon film Forming a via mask, modifying a portion of the undoped polysilicon film exposed by the via mask with a doped polysilicon film, removing the via mask, over the entire surface including the modified undoped polysilicon film Forming a second interlayer insulating film and a nitride film sequentially; forming a trench mask having a line width larger than that of the via mask on the nitride film; etching the nitride film and the second layer insulating film using the trench mask as an etching mask. Forming a via hole penetrating the first interlayer insulating film while forming a trench; and Wrench and features a yirueojim by forming a second metal wiring layer to be connected to the first metal wiring layer through the via hole.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A to 2C are cross-sectional views illustrating a method of forming a dual damascene pattern according to an exemplary embodiment of the present invention.

As shown in FIG. 2A, after the first interlayer insulating film 32 is formed on the semiconductor substrate 31, the first silicon interlayer 32 is undoped on the entire surface of the product. ).

At this time, the first interlayer insulating film 32 is an oxide film having a high density plasma (HDP) -oxide film, a plasma-enhanced (PE) -tetra ethyl ortho silicate (TEOS), a spin on glass (SOG), and a low dielectric constant (Low-k). It is selected from, and the thickness is 3000 kPa-30000 kPa.

The undoped polysilicon film 33 is formed to a thickness of 500 kPa to 2000 kPa.

Next, a photoresist film is coated on the undoped polysilicon film 33 and patterned by exposure and development to form a hole mask 34, and then the hole mask 34 is used as an ion implantation mask. The doped polysilicon film 35 is formed by ion implanting the impurity I into the undoped polysilicon film 33 exposed by the mask 34.

At this time, one selected from As, P, and B is used as the impurity (I), and these impurities (I) are ion implanted at a dose of 1 × E ^{10 to} 1 × E ²⁰ atom / cm ² .

As shown in FIG. 2B, after the hole mask 34 is removed, the second interlayer insulating film 36 and the nitride film 37 are sequentially formed on the undoped polysilicon film 33.

Here, the second interlayer insulating film 36 is selected from among HDP-oxide film, PE-TEOS, SOG, and oxide film having low dielectric constant, and its thickness is 3000 kPa to 30000 kPa. The nitride film 37 is formed to a thickness of 500 kPa to 2000 kPa.

Next, the photoresist film is applied again on the nitride film 37 and patterned by exposure and development to form a line mask 38. At this time, the line mask 38 has a larger line width than the above-described hole mask 34.

As shown in FIG. 2C, a trench having a line shape is formed by first etching the nitride layer 37 using the line mask 38 of FIG. 2B as an etch mask and subsequently etching the second interlayer insulating layer 36. 39).

In this case, when the second interlayer insulating layer 36 is etched, the etch stops in the undoped polysilicon layer 33 according to the difference in the etching selectivity between the second interlayer insulating layer 35 and the undoped polysilicon layer 33. The doped polysilicon film 35 in the silicon film 33 is etched by an etching gas that etches the second interlayer insulating film 36 with a difference in etching speed from that of the undoped polysilicon film 33.

The reason why the doped polysilicon film 35 is etched is because the polysilicon film has a higher etching rate as the doping concentration increases.

Accordingly, the first interlayer dielectric layer 32, which is exposed by etching the doped polysilicon layer 35, is continuously etched to form holes 40, and when the hole 40 is formed, the first interlayer dielectric layer 32 is etched at a lower layer. It proceeds until the metal wiring 31 is exposed.

Next, the line mask 38 is removed, which is removed by the photoresist strip process because the line mask 38 uses a conventional photoresist film, and a cleaning process is performed to remove by-products after the photoresist strip process. In this case, a solvent solution such as EKC, ACT, or R502, which is commonly known in the washing process, is used.

The above-described embodiment is applicable to a case in which a line pattern and a hole pattern are simultaneously formed in a word line and a bit line process using a dual damascene process in a semiconductor device manufacturing process.

3A to 3D are cross-sectional views illustrating a manufacturing process of a multilayer metal wiring by a dual damascene process to which an embodiment of the present invention is applied.

As shown in FIG. 3A, after the lower metal wiring 41 is formed, the first interlayer insulating film 42 is formed on the entire surface including the lower metal wiring 41, and then the first interlayer insulating film 42 is planarized. An undoped polysilicon film 43 is formed on the entire surface of the resultant product.

At this time, the first interlayer insulating film 42 is selected from among HDP-oxide film, PE-TEOS, SOG, and oxide film having a low dielectric constant, and its thickness is 3000 kPa to 30000 kPa.

The undoped polysilicon film 43 is formed to a thickness of 500 kPa to 2000 kPa.

Next, after the photoresist is coated on the undoped polysilicon film 43 and patterned by exposure and development to form the via mask 44, the via mask 44 is used as the ion implantation mask. An impurity (I) is ion-implanted into the undoped polysilicon film 43 exposed by the dope to be modified into the dope polysilicon film 45.

At this time, one selected from As, P, and B is used as the impurity (I), and these impurities (I) are ion implanted at a dose of 1 × E ^{10 to} 1 × E ²⁰ atom / cm ² .

As shown in FIG. 3B, after the via mask 44 is removed, the second interlayer insulating film 46 and the nitride film 47 are sequentially formed on the undoped polysilicon film 43.

Here, the second interlayer insulating film 46 is selected from among HDP-oxide film, PE-TEOS, SOG, and oxide film having low dielectric constant, and its thickness is 3000 kPa to 30000 kPa. The nitride film 47 is formed to a thickness of 500 kPa to 2000 kPa.

Next, the photoresist film is applied again on the nitride film 47 and patterned by exposure and development to form the trench mask 48. At this time, the trench mask 48 has a larger line width than the via mask 44 described above.

As shown in FIG. 3C, the nitride film 47 is first etched using the trench mask 48 of FIG. 3B as an etch mask, and the second interlayer insulating film 46 is successively etched to form trenches for subsequent lines of upper metallization. Form 49.

In this case, when the second interlayer insulating layer 46 is etched, the etch stops in the undoped polysilicon layer 43 according to the difference in the etching selectivity between the second interlayer insulating layer 45 and the undoped polysilicon layer 43. The doped polysilicon film 45 in the silicon film 43 is etched by an etching gas that etches the second interlayer insulating film 46 with a difference in etching speed from that of the undoped polysilicon film 43.

The reason why the doped polysilicon film 45 is etched is because the polysilicon film has a higher etching rate as the doping concentration increases.

Accordingly, the first interlayer insulating layer 42, which is exposed by etching the doped polysilicon layer 45, is continuously etched to form the via holes 50, and when the via holes 50 are formed, the first interlayer insulating layer 42 is etched under the lower layer. It proceeds until the metal wiring 41 is exposed.

Next, the trench mask 48 is removed, and the trench mask 48 is removed by a photoresist strip process because it uses a conventional photoresist film, and a cleaning process is performed to remove by-products after the photoresist strip process. In this case, a solvent solution such as EKC, ACT, or R502, which is commonly known in the washing process, is used.

Next, as shown in FIG. 3D, a metal film such as copper or aluminum is deposited on the entire surface, and chemical mechanical polishing (CMP) is performed until the surface of the nitride film 47 is exposed to form the trench 49 and the via hole 50. An upper metal wiring 51 embedded in the upper portion is formed. Here, when the upper metal wiring 51 is formed, vias 51a for connection with the lower metal wiring 41 are simultaneously formed.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above has the effect of stabilizing the characteristics of the device by reducing the attack caused by a plurality of etching process by simplifying the process by forming a line and a via hole at the same time in the subsequent trench process without a via etching process.

Claims (5)

Forming a first etch stop layer on the first interlayer insulating layer, the etch rate of which is increased by ion implantation; Forming a hole mask on the first etch stop layer; Implanting impurities into a portion of the first etch stop layer exposed by the hole mask; Removing the hole mask; Sequentially forming a second interlayer insulating film and a second etch stop film on the entire surface including the first etch stop film implanted with impurities; Forming a line mask having a line width greater than that of the hole mask on the second etch stop layer; And Etching the second etch stop layer and the second layer insulating layer using the line mask as an etch mask to form a line pattern and simultaneously form a hole pattern penetrating the first interlayer insulating layer. Method of forming a dual damascene pattern, characterized in that consisting of. The method of claim 1, Wherein the first etch stop layer is an undoped polysilicon layer, and the second etch stop layer is a nitride layer. The method of claim 2, In the step of implanting the impurity, The impurity is ion-implanted in a dose of 1 × E ¹⁰ ~ 1 × E ²⁰ atom / cm ² using one selected from As, P and B, the dual damascene pattern forming method. Forming a first interlayer insulating film on the first metal wiring layer, Forming an undoped polysilicon film on the first interlayer insulating film; Forming a via mask on the undoped polysilicon film; Modifying a portion of the undoped polysilicon film exposed by the via mask with a dope polysilicon film; Removing the via mask; Sequentially forming a second interlayer insulating film and a nitride film on the entire surface including the modified undoped polysilicon film; Forming a trench mask having a line width greater than that of the via mask on the nitride film; Etching the nitride layer and the second layer insulating layer using the trench mask as an etch mask to form a trench and simultaneously forming a via hole penetrating the first interlayer insulating layer; And Forming a second metal wiring layer connected to the first metal wiring layer through the trench and the via hole; Method for forming a multi-layer metal wiring by the dual damascene process, characterized in that made. The method of claim 4, wherein The step of modifying a portion of the undoped polysilicon film to a doped polysilicon film, is carried out by ion implantation of one of the impurities selected from As, P and B in a dose of 1 × E ¹⁰ ~ 1 × E ²⁰ atom / cm ² Forming method of forming a multi-layered metal wiring by a dual damascene process characterized in that.