KR20030049576A - Method for forming via hole in semiconductor device - Google Patents
Method for forming via hole in semiconductor device Download PDFInfo
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- KR20030049576A KR20030049576A KR1020010079818A KR20010079818A KR20030049576A KR 20030049576 A KR20030049576 A KR 20030049576A KR 1020010079818 A KR1020010079818 A KR 1020010079818A KR 20010079818 A KR20010079818 A KR 20010079818A KR 20030049576 A KR20030049576 A KR 20030049576A
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- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 239000010410 layer Substances 0.000 claims abstract description 117
- 229910052751 metal Inorganic materials 0.000 claims abstract description 59
- 239000002184 metal Substances 0.000 claims abstract description 59
- 239000011229 interlayer Substances 0.000 claims abstract description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000003667 anti-reflective effect Effects 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 16
- 239000000460 chlorine Substances 0.000 claims description 7
- 229910052731 fluorine Inorganic materials 0.000 claims description 6
- 239000011737 fluorine Substances 0.000 claims description 6
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 4
- 229910052801 chlorine Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 2
- 229920000642 polymer Polymers 0.000 abstract description 7
- 239000000126 substance Substances 0.000 abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 11
- 239000007789 gas Substances 0.000 description 7
- 229910052755 nonmetal Inorganic materials 0.000 description 7
- 238000001459 lithography Methods 0.000 description 6
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000678 plasma activation Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000779 smoke Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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Abstract
Description
본 발명은 반도체 소자의 비아홀 형성방법에 관한 것으로, 보다 상세하게는 금속성 폴리머 생성 억제 및 비아홀 크기의 원활한 확보가 가능한 반도체 소자의 비아홀 형성방법에 관한 것이다.The present invention relates to a method of forming a via hole of a semiconductor device, and more particularly, to a method of forming a via hole of a semiconductor device capable of suppressing the generation of metallic polymers and ensuring the via hole size smoothly.
일반적으로, 논리 소자(logic device)와 같은 반도체 소자에 있어서는 설계 구조상 비아홀(via hole)은 금속배선(metal line) 위에만 형성된다. 최근에는 소자의 크기가 축소됨에 따라 인접 금속배선간의 RC 지연 문제가 대두되어 저유전상수값을 갖는 물질로 층간절연물질로 쓰이고 있다. 이 가운데 수소를 포함하고 있는 FOx(flowable oxide)도 RC 지연을 줄이기 위한 층간절연물질의 하나로서 사용되고 있다.In general, in a semiconductor device such as a logic device, via holes are formed only on metal lines due to the design structure. Recently, as the size of the device is reduced, the problem of RC delay between adjacent metal interconnects has emerged, which has been used as an interlayer insulating material. Among them, FO x (flowable oxide) containing hydrogen is also used as one of the interlayer insulating materials to reduce the RC delay.
상기한 FOX를 층간절연물질로 사용하는 종래 기술에 따른 반도체 소자의 비아홀 형성방법은, 도 1a에 도시된 바와 같이, 산화막(3)내에 텅스텐 플러그(5)가 형성된 반도체 기판(1)상에 Al 금속층과 Ti/TiN층을 형성한 다음 패터닝하여, 반사방지층(Anti Reflective Coating; 이하, ARC)인 Ti/TiN막(9)이 상부에 도포된 Al 금속배선(7)을 형성한다. 여기서, 미설명 도면부호 4는 상기 텅스텐 플러그(5) 형성을 원활하게 위한 접착층으로서의 Ti/TiN층(4)이다.In the method of forming a via hole of a semiconductor device according to the prior art using the above-described FO X as an interlayer insulating material, as shown in FIG. 1A, a semiconductor substrate 1 having a tungsten plug 5 formed in an oxide film 3 is formed. An Al metal layer and a Ti / TiN layer are formed and then patterned to form an Al metal interconnection 7 coated with a Ti / TiN film 9, which is an Anti Reflective Coating (hereinafter, ARC). Herein, reference numeral 4 denotes a Ti / TiN layer 4 as an adhesive layer for smoothly forming the tungsten plug 5.
그다음, 도 1b에 도시된 바와 같이, 상기 금속배선(9)을 포함한 상기 산화막(3)상에 저유전상수 물질인 FOX(11)를 도포한 다음, 상기 금속배선(9)에 영향을 주지 않는 온도(약 400℃)에서 일정시간(약 30~60분) 동안 열처리(curing)를 실시한다. 그런다음, PE-TEOS(plasma enhanced tetra ethyl ortho silicate)를 층간절연막(13)을 형성한 다음, 상기 층간절연막(13)을 화학적기계적연마(CMP)로 평탄화시킨다.Then, as shown in FIG. 1B, FO X 11, which is a low dielectric constant material, is applied onto the oxide film 3 including the metal wiring 9 and then does not affect the metal wiring 9. Curing is performed at a temperature (about 400 ° C.) for a certain time (about 30 to 60 minutes). Then, PE-TEOS (plasma enhanced tetra ethyl ortho silicate) is formed to form an interlayer insulating film 13, and then the interlayer insulating film 13 is planarized by chemical mechanical polishing (CMP).
이어서, 도 1c에 도시된 바와 같이, 상기 층간절연막(13)상에 감광물질(미도시)을 도포한 후 노광 및 현상공정으로 비아홀 형태로 패터닝한다. 그다음, 활성화된 플라즈마를 이용한 건식각(dry etching)으로 상기 금속배선(7)이 노출되도록 상기 층간절연막(13)을 관통하는 비아홀(15)을 완성한다. 이때, 상기 플라즈마 활성화 기체로는 CXFY와 CAHBFC및 Ar을 일정비율로 혼합하여 사용한다. 또한, 상기 비아홀(15) 형성을 위한 건식각은 공정변수를 고려하여 과도식각을 실시한다.Subsequently, as shown in FIG. 1C, a photosensitive material (not shown) is coated on the interlayer insulating layer 13, and then patterned into via holes in an exposure and development process. Next, the via hole 15 penetrating the interlayer insulating layer 13 is completed so that the metal wiring 7 is exposed by dry etching using an activated plasma. At this time, the plasma activation gas is used by mixing C X F Y and C A H B F C and Ar at a constant ratio. In addition, the dry etching for forming the via hole 15 is overetched in consideration of process variables.
그러나, 종래기술에 따른 반도체 소자의 비아홀 형성방법에 있어서는 다음과 같은 문제점이 있었다.However, the via hole forming method of the semiconductor device according to the prior art has the following problems.
종래기술에 있어서는, 도 1c에 도시된 바와 같이, 상기 FOx(11)는 ARC Ti/TiN막(9)과 반응을 일으켜 일반적인 세정공정으로는 제거하기 어려운 금속성 폴리머(17)를 상기 비아홀(15) 측벽에 쌓이게 한다. 따라서, 설계법칙(design rule)에서 요구하는 비아홀 크기를 확보하기 어려우며, 비아 저항이 커져서 소자의 동작속도가 저하되는 등 소자의 신뢰성을 확보하기 어렵다는 문제점이 있었다.In the prior art, as shown in FIG. 1C, the FO x 11 reacts with the ARC Ti / TiN film 9 to remove the metallic polymer 17, which is difficult to be removed by a general cleaning process. ) On the side wall. Therefore, it is difficult to secure the via hole size required by the design rule, and it is difficult to secure the reliability of the device, such as a decrease in the operating speed of the device due to a large via resistance.
이를 해결하기 위하여 종래에는 과도식각 자체를 줄여 상대적으로 양이 적은금속성 폴리머가 발생토록 하는 방법이 제안된 바 있었다. 그러나, 이러한 방법에 있어서는 비아홀 하부의 금속배선 패턴 밀도 등에 의해 FOX및 PE-TEOS 막의 스택(stack) 구성 차이가 발생하여 서로 다른 식각속도를 갖는 두가지 필름 특성으로 인해 과도식각 자체를 줄이기 힘들다는 문제점이 있다.In order to solve this problem, a method of reducing the excessive etching itself has been proposed to generate a relatively small amount of metallic polymer. However, in this method, the difference in stack composition of the FO X and PE-TEOS films due to the density of the metallization pattern in the lower part of the via hole occurs, which makes it difficult to reduce the transient etching itself due to two film characteristics having different etching rates. There is this.
또한, 과도식각 자체를 줄일 경우 산화막 증착 및 연마공정 등으로 기인한 산화막 두께 차이로 인한 언더에치(underetch) 가능성을 내재한다는 문제점이 있었다.In addition, when the excessive etching itself is reduced, there is a problem inherent in the possibility of underetching due to the difference in the thickness of the oxide due to oxide deposition and polishing processes.
이에, 본 발명은 상기한 종래기술의 제반 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 Si3N4막이나 SiON 등을 반사방지층, 하드마스크, 또는 금속배선 주위의 라이너(liner)로 사용하여 금속성 폴리머 형성을 방지함과 동시에 적정한 크기의 비아홀을 확보할 수 있는 반도체 소자의 비아홀 형성방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, an object of the present invention is to convert a Si 3 N 4 film or SiON, etc. into an anti-reflection layer, a hard mask, or a liner around metal wiring The present invention provides a method of forming a via hole in a semiconductor device which can prevent the formation of a metallic polymer and secure a via hole of an appropriate size.
도 1a 및 도 1b는 종래기술에 따른 반도체 소자의 비아홀 형성방법을 설명하기 위한 단면도.1A and 1B are cross-sectional views illustrating a method of forming a via hole in a semiconductor device according to the prior art.
도 2a 및 도 2b는 본 발명의 실시예 1에 따른 반도체 소자의 비아홀 형성방법을 설명하기 위한 단면도.2A and 2B are cross-sectional views illustrating a method of forming a via hole in a semiconductor device according to example 1 of the present invention.
도 3a 및 도 3b는 본 발명의 실시예 2에 따른 반도체 소자의 비아홀 형성방법을 설명하기 위한 단면도.3A and 3B are cross-sectional views illustrating a method of forming a via hole in a semiconductor device according to a second exemplary embodiment of the present invention.
도 4a 및 도 4b는 본 발명의 실시예 3에 따른 반도체 소자의 비아홀 형성방법을 설명하기 위한 단면도.4A and 4B are cross-sectional views illustrating a method of forming a via hole in a semiconductor device according to a third exemplary embodiment of the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
101: 반도체 기판103: 산화막101: semiconductor substrate 103: oxide film
104: 접촉층105: 플러그104: contact layer 105: plug
107: 금속배선109: 반사방지층107: metal wiring 109: antireflection layer
111: 저유전상수물질층113: 층간절연막111: low dielectric constant material layer 113: interlayer insulating film
115: 비아홀115: Via Hole
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 비아홀 형성방법은, 반도체 기판상에 금속층과 반사방지층을 순차로 적층한 다음, 상기 금속층 및 반사방지층을 패터닝하여 금속층 패턴 및 반사방지층 패턴을 형성하는 단계; 상기 반사방지층 패턴을 포함한 반도체 기판상에 저유전상수물질층 및 층간절연막을 형성하는 단계; 및 상기 층간절연막 및 저유전상수물질층을 상기 금속층 패턴 일부를 노출시키도록 선택적으로 패터닝하여 비아홀을 형성하는 단계를 포함하는 것을 특징으로 한다.In the method of forming a via hole of a semiconductor device according to the present invention, a metal layer and an antireflection layer are sequentially stacked on a semiconductor substrate, and then the metal layer and the antireflection layer are patterned to form a metal layer pattern and an antireflection layer pattern. step; Forming a low dielectric constant material layer and an interlayer insulating film on the semiconductor substrate including the anti-reflection layer pattern; And selectively patterning the interlayer dielectric layer and the low dielectric constant material layer to expose a portion of the metal layer pattern to form a via hole.
이하, 본 발명에 따른 반도체 소자의 비아홀 형성방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a via hole of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 및 도 2b는 본 발명의 실시예 1에 따른 반도체 소자의 비아홀 형성방법을 설명하기 위한 공정별 단면도이고, 도 3a 및 도 3b는 본 발명의 실시예 2에 따른 반도체 소자의 비아홀 형성방법을 설명하기 위한 공정별 단면도이고, 도 4a 및 도 4b는 본 발명의 실시예 3에 따른 반도체 소자의 비아홀 형성방법을 설명하기 위한 공정별 단면도이다.2A and 2B are cross-sectional views illustrating a method of forming a via hole of a semiconductor device according to a first embodiment of the present invention, and FIGS. 3A and 3B illustrate a method of forming a via hole in a semiconductor device according to a second embodiment of the present invention. 4A and 4B are cross-sectional views illustrating a method of forming a via hole of a semiconductor device according to example embodiments of the present invention.
본 발명의 실시예 1에 따른 반도체 소자의 비아홀 형성방법은, 도 2a에 도시된 바와 같이, 산화막(103)과 플러그(105)가 형성된 반도체 기판(101)상에 금속배선용 금속층, 예를 들면, 알루미늄(Al) 금속층을 증착한 다음, 상기 금속층상에 비금속으로 구성된 반사방지층(ARC:Anti Reflective Coating)을 순차로 증착한다. 그런다음, 리소그라프(lithograph) 공정으로 상기 금속층 및 반사방지층을 패터닝하여 상기 비금속층을 반사방지층(109)으로 하는 금속배선(107)을 형성한다.In the method of forming a via hole of a semiconductor device according to the first exemplary embodiment of the present invention, as shown in FIG. 2A, a metal layer for metal wiring, for example, is formed on a semiconductor substrate 101 on which an oxide film 103 and a plug 105 are formed. After depositing an aluminum (Al) metal layer, an anti-reflective layer (ARC) consisting of a nonmetal is sequentially deposited on the metal layer. Then, the metal layer and the antireflection layer are patterned by a lithography process to form a metal wiring 107 having the nonmetal layer as the antireflection layer 109.
이때, 상기 반사방지층(109)으로는 금속이 아닌 비금속, 예를 들면, 옥시나이트라드(Oxynitride) 또는 실리콘나이트라이드(Silicon nitride: Si3N4)를 사용한다.In this case, as the anti-reflection layer 109, a non-metal, for example, oxynitride or silicon nitride (Si 3 N 4 ) is used.
상기 금속배선 형성과정을 구체적으로 살펴보면 다음과 같다. 먼저, 상기 비금속층(예; 옥시나이트라이드 또는 실리콘나이트라이드)을 감광막(미도시)과불소(F) 계열의 가스 케미스트리(gas chemistry), 즉 불소(F:fluorine) 계열 가스의 화학적 성질을 이용하여 식각한다. 그다음, 상기 금속층(예; Al)을 염소(Cl:chlorine) 계열 가스의 화학적 성질을 이용하여 식각하여 금속배선(107)을 형성한다. 이 경우, 상기 반사방지층(107)으로는 비금속인 옥시나이트라이드 또는 실리콘나이트라이드를 사용하므로 상기 금속배선(107) 형성시 선택비를 확보할 수 있어서 상기 감광막(미도시)의 공정마진을 확보할 수 있다.Looking at the formation process of the metal wiring in detail as follows. First, the non-metal layer (eg, oxynitride or silicon nitride) may be used by using a photochemical film (not shown) and a fluorine (F) -based gas chemistry, that is, a chemical property of a fluorine-based gas. To etch. Next, the metal layer (eg, Al) is etched using the chemical properties of chlorine (Cl) -based gas to form a metal wiring 107. In this case, oxynitride or silicon nitride, which is a non-metal, may be used as the anti-reflection layer 107 to secure a selection ratio when forming the metal wiring 107, thereby securing a process margin of the photoresist film (not shown). Can be.
여기서, 미설명 도면부호 104는 상기 플러그(105) 형성을 원활하게 위한 접착층(104), 예를들면, Ti/TiN층이다.Here, reference numeral 104 denotes an adhesive layer 104, for example, a Ti / TiN layer, for smoothly forming the plug 105.
이어서, 도 2b에 도시된 바와 같이, 상기 금속배선(107)이 형성된 상기 산화막(103)상에 저유전상수물질, 예를 들어, FOX(111:flowable oxide)를 증착한 다음, 상기 FOX(111)상에 층간절연막, 예를 들어, PE-TEOS(113:plasma enhanced tetra ethyl ortho silicate)를 증착하고 이를 평탄화시킨다.Subsequently, as shown in FIG. 2B, a low dielectric constant material such as FO X (111: flowable oxide) is deposited on the oxide film 103 on which the metal wiring 107 is formed, and then the FO X ( An interlayer insulating film, for example, PE-TEOS (plasma enhanced tetra ethyl ortho silicate) (113) is deposited and planarized on the layer 111).
다음으로, 상기 PE-TEOS(113)상에 리소그라피 공정으로 마스크(미도시)를 혀성한 다음, 상기 반사방지층(109)인 옥시나이트라이드 또는 실리콘나이트라이드에 대해 선택비가 높은 조건으로 상기 PE-TEOS(113)를 관통하도록 식각을 진행하여 비아홀(115)을 형성한다. 이때, 상기 비아홀(115) 형성과정은 식각중단층 역할을 하는 상기 반사방지층(107)인 옥시나이트라이드 또는 실리콘나이트라이드에서 중단하 후, 상기 옥시나이트라이드 또는 실리콘나이트라이드에 대해 식각속도가 빠른 조건을 이용하여 상기 금속배선(107)을 노출시킨다.Next, a mask (not shown) is formed on the PE-TEOS 113 by a lithography process, and then the PE-TEOS is selected under conditions of high selectivity with respect to the anti-reflection layer 109, oxynitride or silicon nitride. Etching is performed to penetrate 113 to form the via hole 115. In this case, the via hole 115 forming process stops at the oxynitride or silicon nitride, the anti-reflection layer 107 serving as an etch stop layer, and then the etching rate of the oxynitride or silicon nitride is high. Using to expose the metal wiring 107.
한편, 상기 금속배선(107)과 반사방지층(109) 사이의 접합을 원활하게 하기 위하여 별도의 산화막(미도시)을 상기 금속배선용 금속층과 반사방지층용 비금속층 사이에 더 형성할 수 있다.On the other hand, in order to facilitate the bonding between the metal wiring 107 and the antireflection layer 109, an additional oxide film (not shown) may be further formed between the metal wiring metal layer and the anti-reflection layer non-metal layer.
본 발명의 실시예 2에 따른 반도체 소자의 비아홀 형성방법은, 도 3a에 도시된 바와 같이, 산화막(203)과 플러그(205)가 형성된 반도체 기판(201)상에 금속배선용 금속배선층을 증착한 다음, 상기 금속배선층상에 반사방지층 및 하드마스크층을 순차로 증착한다. 그런다음, 리소그라프(lithograph) 공정으로 상기 하드마스크층과 반사방지층 및 금속배선층을 패터닝하여 하드마스크(210) 및 반사방지층(209)이 증착된 금속배선(207)을 형성한다.In the method of forming a via hole of a semiconductor device according to the second exemplary embodiment of the present invention, as shown in FIG. 3A, a metal wiring layer for metal wiring is deposited on a semiconductor substrate 201 on which an oxide film 203 and a plug 205 are formed. On the metal wiring layer, an antireflection layer and a hard mask layer are sequentially deposited. Then, the hard mask layer, the antireflection layer, and the metal wiring layer are patterned by a lithography process to form the metal wiring 207 on which the hard mask 210 and the antireflection layer 209 are deposited.
이때, 상기 반사방지층(209)으로는 Ti/TiN을 사용하고, 상기 하드마스크(210)로는 옥시나이트라드 (Oxynitride) 또는 실리콘나이트라이드 (Silicon nitride: Si3N4)를 사용한다.In this case, Ti / TiN is used as the antireflection layer 209, and oxynitride or silicon nitride Si 3 N 4 is used as the hard mask 210.
상기 금속배선 형성과정을 구체적으로 살펴보면 다음과 같다. 먼저, 상기 하드마스크층 및 반사방지층을 감광막(미도시)과 불소(F) 계열의 가스 케미스트리(gas chemistry), 즉 불소(F:fluorine) 계열 가스의 화학적 성질을 이용하여 식각한다. 그다음, 상기 금속배선층을 염소(Cl:chlorine) 계열 가스의 화학적 성질을 이용하여 식각하여 금속배선(207)을 형성한다.Looking at the formation process of the metal wiring in detail as follows. First, the hard mask layer and the anti-reflection layer are etched by using a chemical property of a photoresist (not shown) and a fluorine (F) -based gas chemistry, that is, a fluorine-based gas. Next, the metal wiring layer is etched using chemical properties of chlorine-based gas to form metal wiring 207.
여기서, 미설명 도면부호 204는 상기 플러그(205) 형성을 원활하게 위한 접착층(204), 예를들면, Ti/TiN층이다.Herein, reference numeral 204 denotes an adhesive layer 204 for smoothly forming the plug 205, for example, a Ti / TiN layer.
이어서, 도 3b에 도시된 바와 같이, 상기 금속배선(207)이 형성된 상기 산화막(203)상에 저유전상수물질, 예를 들어, FOX(111:flowable oxide)를 증착한 다음, 상기 FOX(211)상에 층간절연막, 예를 들어, PE-TEOS(213:plasma enhanced tetra ethyl ortho silicate)를 증착하고 이를 평탄화시킨다.Subsequently, as shown in FIG. 3B, a low dielectric constant material, for example, FO X (111: flowable oxide) is deposited on the oxide film 203 on which the metal wiring 207 is formed, and then the FO X ( An interlayer insulating film, for example, 213 (plasma enhanced tetra ethyl ortho silicate) (PE-TEOS) is deposited and planarized on 211).
다음으로, 상기 PE-TEOS(213)상에 리소그라피 공정으로 마스크(미도시)를 혀성한 다음, 상기 하드마스크(209)인 옥시나이트라이드 또는 실리콘나이트라이드에 대해 선택비가 높은 조건으로 상기 PE-TEOS(213)를 관통하도록 식각을 진행하여 비아홀(215)을 형성한다. 이때, 상기 비아홀(215) 형성과정은 식각중단층 역할을 하는 상기 하드마스크(209)인 옥시나이트라이드 또는 실리콘나이트라이드에서 중단하 후, 상기 옥시나이트라이드 또는 실리콘나이트라이드에 대해 식각속도가 빠른 조건을 이용하여 상기 금속배선(207)을 노출시킨다.Next, a mask (not shown) is formed on the PE-TEOS 213 by a lithography process, and then the PE-TEOS is subjected to a high selectivity to the oxynitride or silicon nitride, which is the hard mask 209. The via hole 215 is formed by etching through 213. In this case, the via hole 215 forming process is stopped in the oxynitride or silicon nitride, the hard mask 209 serving as an etch stop layer, and then the etching rate is faster with respect to the oxynitride or silicon nitride. Exposing the metal wiring 207 by using;
본 발명의 실시예 3에 따른 반도체 소자의 비아홀 형성방법은, 도 4a에 도시된 바와 같이, 먼저 산화막(303)과 플러그(305)가 형성된 반도체 기판(301)상에 금속층을 증착한 다음, 상기 금속배선층상에 반사방지층을 순차로 증착한다. 그런다음, 리소그라프(lithograph) 공정으로 상기 반사방지층 및 금속층을 패터닝하여 반사방지층(309)이 도포된 금속배선(307)을 형성한다. 이때, 상기 반사방지층(109)으로는 Ti/TiN을 사용한다.In the method of forming a via hole of a semiconductor device according to Embodiment 3 of the present invention, as shown in FIG. 4A, a metal layer is first deposited on a semiconductor substrate 301 on which an oxide film 303 and a plug 305 are formed. The antireflection layer is sequentially deposited on the metallization layer. Then, the antireflection layer and the metal layer are patterned by a lithography process to form a metal wiring 307 coated with the antireflection layer 309. In this case, Ti / TiN is used as the antireflection layer 109.
그런다음, 상기 금속배선(307)을 포함하도록 상기 산화막(303)상에 비금속층, 예를들어, 옥시나이트라아드(Oxynitride) 또는 실리콘나이트라이드(Siliconnitride)로 라이너(310:liner)를 형성한다. 상기 라이너(310)는 후속공정에서 식각중단층 역할을 한다.Then, a liner 310 is formed on the oxide layer 303 to include the metal wiring 307 by using a non-metal layer, for example, oxynitride or silicon nitride. . The liner 310 serves as an etch stop layer in a subsequent process.
여기서, 미설명 도면부호 304는 상기 플러그(305) 형성을 원활하게 위한 접착층(304), 예를들면, Ti/TiN층이다.Here, reference numeral 304 denotes an adhesive layer 304, for example, a Ti / TiN layer, for smoothly forming the plug 305.
이어서, 도 4b에 도시된 바와 같이, 상기 금속배선(307)이 형성된 상기 산화막(303)상에 저유전상수물질, 예를 들어, FOX(311:flowable oxide)를 증착한 다음, 상기 FOX(311)상에 층간절연막, 예를들어, PE-TEOS(313:plasma enhanced tetra ethyl ortho silicate)를 증착하고 이를 평탄화시킨다.Subsequently, as shown in FIG. 4B, a low dielectric constant material, for example, FO X (311: flowable oxide) is deposited on the oxide film 303 on which the metal wiring 307 is formed, and then the FO X ( An interlayer insulating film, for example, plasma enhanced tetra ethyl ortho silicate (PE-TEOS), is deposited and planarized on 311).
다음으로, 상기 PE-TEOS(313)상에 리소그라피 공정으로 마스크(미도시)를 혀성한 다음, 상기 라이너(310)인 옥시나이트라이드 또는 실리콘나이트라이드에 대해 선택비가 높은 조건으로 상기 PE-TEOS(313)를 관통하도록 식각을 진행하여 비아홀(315)을 형성한다. 이때, 상기 비아홀(315) 형성과정은 상기한 바와 같이 식각중단층 역할을 하는 상기 라이너(310)인 옥시나이트라이드 또는 실리콘나이트라이드에서 중단하 후, 상기 옥시나이트라이드 또는 실리콘나이트라이드에 대해 식각속도가 빠른 조건을 이용하여 상기 금속배선(307)을 노출시킨다.Next, a mask (not shown) is formed on the PE-TEOS 313 by a lithography process, and then the PE-TEOS (on the condition that the selectivity is high for oxynitride or silicon nitride, which is the liner 310). The via hole 315 is formed by etching through 313. At this time, the formation process of the via hole 315 is stopped in the oxynitride or silicon nitride, the liner 310 serving as an etch stop layer as described above, and then the etching rate with respect to the oxynitride or silicon nitride. The metal wire 307 is exposed using a fast condition.
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims encompass all patentable new matters inherent in the invention, and are common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 비아홀 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the method of forming the via hole of the semiconductor device according to the present invention has the following effects.
본 발명에 있어서는, ARC Ti/TiN, FOX및 O2플라즈마 상태에서 발생할 수 있는 금속성 폴리머 발생을 억제할 수 있으므로 설계법칙에서 요구하는 비아홀의 크기를 원활하게 구현할 수 있다.In the present invention, since the generation of metallic polymers that can occur in ARC Ti / TiN, FO X and O 2 plasma states can be suppressed, the size of the via hole required by the design rule can be smoothly implemented.
또한, 산화막 증착 및 연막공정에서 발생하는 산화막 두께 차이로 인한 과도식각을 해소할 수 있으므로 ARC Ti/TiN 등 금속배선에서 발생하는 금속성 폴리머를 방지할 뿐만 아니라 옥시나이트라이드(oxynitride) 또는 Si3N4등이 식각중단층으로 작용하므로 식각량을 조절할 수 있으므로 산화막 두께에서 비롯되는 언더에치(underetch)를 방지할 수 있다.In addition, it is possible to eliminate the excessive etching due to the oxide film thickness difference generated in the oxide film deposition and smoke film process, so as not only to prevent the metallic polymer generated in the metal wiring such as ARC Ti / TiN but also oxynitride or Si 3 N 4 Since the back serves as an etch stop layer, the amount of etching can be controlled to prevent underetch caused by the thickness of the oxide layer.
아울러, 금속배선시 증착된 옥시나이트라이드(oxynitride) 또는 Si3N4등이 하드마스크로 작용하므로 상대적으로 부족했던 감광물질에 대한 선택비를 보상해주므로 금속배선 공정에 대한 공정여유를 확보할 수 있게 된다는 장점이 있다.In addition, oxynitride or Si 3 N 4 deposited during the metal wiring acts as a hard mask, thus compensating the selection ratio for the relatively insufficient photosensitive material, thereby securing process margin for the metal wiring process. The advantage is that there is.
Claims (13)
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