KR20030048961A - Method of forming an isolation film in semiconductor device - Google Patents

Method of forming an isolation film in semiconductor device Download PDF

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Publication number
KR20030048961A
KR20030048961A KR1020010079017A KR20010079017A KR20030048961A KR 20030048961 A KR20030048961 A KR 20030048961A KR 1020010079017 A KR1020010079017 A KR 1020010079017A KR 20010079017 A KR20010079017 A KR 20010079017A KR 20030048961 A KR20030048961 A KR 20030048961A
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South Korea
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trench
forming
layer
semiconductor substrate
film
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KR1020010079017A
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Korean (ko)
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차한섭
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주식회사 하이닉스반도체
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Priority to KR1020010079017A priority Critical patent/KR20030048961A/en
Publication of KR20030048961A publication Critical patent/KR20030048961A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: A method for fabricating an isolation layer of a semiconductor device is provided to prevent boron ions in a p-well from being diffused into a trench by forming a silicon germanium layer in the sidewall of the trench of a shallow trench isolation(STI) structure, and to prevent a characteristic of the device from being degraded by maintaining a uniform density of the boron ions in the p-well. CONSTITUTION: After a pad oxide layer and a nitride layer are formed on a semiconductor substrate(11), a trench region is defined. The nitride layer, the pad nitride layer and the semiconductor substrate in the trench region are removed to form the trench in the semiconductor substrate. The silicon germanium layer(16) is formed in the semiconductor substrate inside the sidewall of the trench. A thermal oxide layer(17) is formed on the sidewall of the trench. After a high density plasma(HDP) oxide layer(18) is formed on the resultant structure, a planarization process is performed to expose the nitirde layer. The nitride layer and the pad oxide layer are eliminated.

Description

반도체 소자의 소자 분리막 형성 방법{Method of forming an isolation film in semiconductor device}Method of forming an isolation film in semiconductor device

본 발명은 소자 분리막 형성 방법에 관한 것으로, STI(Shallow Trench Isolation)구조의 트랜치 측벽내에 실리콘 게르마늄(Silicon Germanium)막을 형성하여 P웰(Pwell)의 붕소(Boron)가 STI구조의 트랜치 내부로 확산되는 것을 억제함으로 소자의 특성향상과 원가를 절감할 수 있는 소자 분리막 형성 방법에 관한 것이다.The present invention relates to a method of forming a device isolation layer, wherein a silicon germanium film is formed in a sidewall of a trench trench isolation (STI) structure so that boron of a P well is diffused into a trench of an STI structure. The present invention relates to a method of forming a device isolation layer capable of reducing device characteristics and reducing costs.

도 1은 종래의 활성영역이 소자 분리막에 의해 고립된 후 플로팅 게이트가 형성된 상부단면도이다.1 is a top sectional view in which a floating gate is formed after a conventional active region is isolated by an isolation layer.

도 2는 도 1의 a - a 선상의 구조도 이다.FIG. 2 is a structural diagram of a-a line in FIG. 1. FIG.

도 1 및 도 2를 참조하면, 실리콘 기판(Si substrate)(1)상에 트랜치(Tranch)(2)를 형성하여 활성영역(3)을 고립한 후 상기 활성 영역(3)에 P형 이온을 주입을 통하여 P웰(Pwell)(6)을 형성한다. 상기 전체 구조 상부에 게이트 산화막(5)과 폴리 실리콘(Poly Si)(4)을 증착한 후 플로팅 게이트패턴(Floating gate pattern)을 형성한다.1 and 2, a trench 2 is formed on a Si substrate 1 to isolate an active region 3, and then P-type ions are formed in the active region 3. Pwell 6 is formed by implantation. After the gate oxide layer 5 and the polysilicon layer 4 are deposited on the entire structure, a floating gate pattern is formed.

상기 활성 영역(3)에 주입되는 P형 이온으론 붕소(Boron)(7)를 사용한다. 하지만 상기 붕소(7)는 실리콘(Silicon) 내부에 존재하는 것 보다 실리콘산화막(Silicon oxide) 내부에 존재하는 것이 열역학적으로 안정한 특성을 갖는다. 이로 인해 추후 열 공정시 P웰(6) 영역에 있던 붕소(7)가 STI구조의 트랜치(2) 내부로 급속히 확산된다. 이는 P웰(6) 영역 중 STI구조의 트랜치(2)와 인접하고 있는 부분의 붕소(7)의 농도를 국부적으로 감소시키게 된다. 이는 접합 부분의 누설 전류(Junction leakage)와 협폭 효과(Narrow Width Effect) 같은 소자의 특성을 악화 시키는 형상을 유발한다.Boron (Boron) 7 is used as the P-type ion implanted into the active region 3. However, the boron 7 is thermodynamically stable in that it is present in the silicon oxide film rather than in the silicon. As a result, boron 7 in the P well 6 region during the thermal process is rapidly diffused into the trench 2 of the STI structure. This locally reduces the concentration of boron 7 in the portion of the P well 6 region adjacent to the trench 2 of the STI structure. This causes shapes that degrade the device's characteristics, such as junction leakage and narrow width effects.

따라서 본 발명은 상술한 단점을 해소할 수 있는 반도체 소자의 소자 분리막 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of forming a device isolation film of a semiconductor device capable of solving the above-mentioned disadvantages.

본 발명의 다른 목적은 트랜치 측벽내에 실리콘 게르마늄막을 형성하여 P웰의 붕소가 STI구조의 트랜치 내부로 확산되지 않는 소자 분리막을 형성하는데 그 목적이 있다.Another object of the present invention is to form a silicon germanium film in the trench sidewalls to form an isolation layer in which boron of the P well is not diffused into the trench of the STI structure.

도 1은 종래의 활성영역이 소자 분리막에 의해 고립된 후 플로팅 게이트가 형성된 상부단면도.1 is a top sectional view in which a floating gate is formed after a conventional active region is isolated by an isolation layer;

도 2는 도 1의 a - a 선상의 구조도.2 is a structural diagram of a-a line in FIG.

도 3a 내지 도 3f는 본 발명에 따른 소자 분리막 형성방법을 설명하기 위한 단면도.3A to 3F are cross-sectional views illustrating a method of forming an isolation layer in accordance with the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

1, 11 : 실리콘 기판2, 15 : 트랜치1, 11: silicon substrate 2, 15: trench

3 : 활성 영역4 : 폴리 실리콘3: active area 4: polysilicon

5 : 게이트 산화막6 : P웰5: gate oxide film 6: P well

7 : 붕소12 : 패드 산화막7: boron 12: pad oxide film

13 : 질화막14 : 포토레지스트13 nitride film 14 photoresist

16 : 실리콘 게르마늄17 : 열 산화막16: silicon germanium 17: thermal oxide film

18 : HDP 산화막18: HDP oxide film

반도체 기판에 패드 산화막 및 질화막을 형성한 후 트랜치 영역을 정의하는 단계, 상기 트랜치 영역의 상기 질화막, 상기 패드 산화막 및 상기 반도체 기판을 제거하여 상기 반도체 기판 내에 트랜치를 형성하는 단계, 상기 트랜치 측벽 내측의 상기 반도체 기판내에 실리콘 게르마늄막을 형성하는 단계, 상기 트랜치 측벽에 열 산화막을 형성하는 단계, 전체 구조 상부에 HDP산화막을 형성한 후 상기 질화막이 노출되도록 평탄화공정을 수행하는 단계 및 상기 질화막 및 패드 산화막을 제거하는 단계를 포함하여 이루어진 것을 특징으로 하는 소자 분리막 형성 방법을 제공한다.Defining a trench region after forming a pad oxide film and a nitride film on the semiconductor substrate, removing the nitride film, the pad oxide film, and the semiconductor substrate of the trench region to form a trench in the semiconductor substrate, and forming a trench in the semiconductor sidewall Forming a silicon germanium film in the semiconductor substrate, forming a thermal oxide film on the sidewalls of the trench, forming an HDP oxide film over the entire structure, and then performing a planarization process to expose the nitride film and the nitride film and the pad oxide film. It provides a device isolation film forming method comprising the step of removing.

이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3f는 본 발명에 따른 소자 분리막 형성방법을 설명하기 위한 단면도이다.3A to 3F are cross-sectional views illustrating a method of forming a device isolation film according to the present invention.

도 3a를 참조하면, 실리콘 기판(Si substrate)(11)상에 패드 산화막(pad oxidation)(12)과 질화막(nitride)(13)을 순차적으로 증착한다. 상기의 패드 산화막(12)과 질화막(13)이 증착된 실리콘 기판(11)상에 포토레지스트(Photoresist)(14)를 도포한 후 포토 마스크를 이용하여 포토레지스트 패턴을 형성함으로 트랜치(15)가 형성될 영역을 정의한다.Referring to FIG. 3A, a pad oxide film 12 and a nitride film 13 are sequentially deposited on a Si substrate 11. After the photoresist 14 is coated on the silicon substrate 11 on which the pad oxide film 12 and the nitride film 13 are deposited, the trench 15 is formed by forming a photoresist pattern using a photo mask. Define the area to be formed.

도 3b를 참조하면, 상기 트랜치(15)가 형성될 영역의 질화막(13), 패드 산화막(12)및 실리콘 기판(11)에 소정의 식각 공정을 실시하여 트랜치(trench)(15)를 형성함으로 활성(active) 영역이 정의된다.Referring to FIG. 3B, a trench 15 is formed by performing a predetermined etching process on the nitride layer 13, the pad oxide layer 12, and the silicon substrate 11 in the region where the trench 15 is to be formed. An active region is defined.

도 3c를 참조하면, 전체 구조 상부에 게르마늄(Germanium) 이온을 주입하여 상기 트랜치(15) 측벽내에 실리콘 게르마늄(Silicon Germanium)막(16)을 형성한다.Referring to FIG. 3C, germanium ions are implanted into the entire structure to form a silicon germanium layer 16 in the sidewalls of the trench 15.

구체적으로 전체 구조 상부에 게르마늄 이온을 약 100Å 깊이로 이온주입 한 후 900 내지 1100의 온도에서 5 내지 30초간 급속 열처리를 실시하면, 상기 게르마늄이온과 상기 실리콘 기판(11)이 반응하여 실리콘 게르마늄 화합물이 형성된다. 즉 이온 주입공정은 5 내지 20KeV의 에너지와 1E15 또는 9E16/㎠로 가급적 높은 함유량을 가진 게르마늄 이온의 프로젝션 레인지(Projection Range)를 약 50 내지 150Å으로 한다.Specifically, when germanium ions are implanted into the upper portion of the entire structure to a depth of about 100 μs and then rapidly heat treated at a temperature of 900 to 1100 for 5 to 30 seconds, the germanium ions and the silicon substrate 11 react to form a silicon germanium compound Is formed. That is, the ion implantation process has a projection range of about 50 to 150 kW of germanium ions having energy of 5 to 20 KeV and a high content of 1E15 or 9E16 / cm 2 as possible.

또한 산소(Oxygen)가 포함되지 않은 순수한 게르마늄이온을 주입함으로 산화막이 발생되지 않게 하고 상기 프로젝션 레인지를 후속 열 산화막(17)의 두께의 절반보다 깊은 프로젝션 레인지를 가지게 함으로써 후속 열 산화에 의해 실리콘 게르마늄막(16)에 산화막을 형성되지 않게 한다. 한편 상기 트랜치(15) 측벽에 실리콘 게르마늄막(16)이 형성되어 상기 실리콘 게르마늄막(16)에 의해 P웰 영역에 도핑된 붕소가 STI구조의 트랜치(15) 내부로 확산되는 것을 막아준다.In addition, by injecting pure germanium ions that do not contain oxygen (oxygen), the oxide film is not generated and the projection range has a projection range that is deeper than half of the thickness of the subsequent thermal oxide film 17. The oxide film is not formed at (16). Meanwhile, a silicon germanium layer 16 is formed on the sidewalls of the trench 15 to prevent boron doped in the P well region by the silicon germanium layer 16 from being diffused into the trench 15 of the STI structure.

도 3d 및 3e를 참조하면, STI구조의 트랜치(15) 측벽의 식각 손상을 보상하기 위해 상기 STI구조의 트랜치(15)에 측벽 산화를 실시하여 열 산화막(16)을 형성한다. 상기 열 산화막(16)이 형성된 STI구조의 트랜치(15)를 매립하기 위해서 HDP(High Density Plasma) 산화막(18)을 실리콘 기판상에 증착한 후 평탄화 공정을 수행한다.3D and 3E, in order to compensate for etch damage of the sidewalls of the trenches 15 of the STI structure, sidewall oxidation is performed on the trenches 15 of the STI structure to form a thermal oxide film 16. In order to fill the trench 15 of the STI structure in which the thermal oxide film 16 is formed, the HDP (High Density Plasma) oxide film 18 is deposited on a silicon substrate, and then a planarization process is performed.

구체적으로 상기 트랜치 내부에 빈 공간이 형성되지 않도록 HDP 산화막(18)을 증착한 후 질화막(13)을 식각정지층으로 하여 상기 질화막(13) 상의 HDP 산화막(18)을 제거하기 위한 STI CMP 공정을 수행함으로써 평탄화 한다.Specifically, an STI CMP process for removing the HDP oxide layer 18 on the nitride layer 13 using the nitride layer 13 as an etch stop layer after depositing the HDP oxide layer 18 so as not to form an empty space in the trench. Plane by doing.

도 3f를 참조하면, 상기 질화막(13)과 패드 산화막(12)을 제거함으로써 활성 영역을 고립하는 소자 분리막이 형성된다.Referring to FIG. 3F, the device isolation layer is formed to isolate the active region by removing the nitride layer 13 and the pad oxide layer 12.

이와 같이 본 발명에 의한 소자 분리막 형성 방법은 STI구조의 트랜치 측벽내에 실리콘 게르마늄막을 형성함으로써 P웰의 붕소가 트랜치 내부로 확산하는 것을 막을 수 있다.As described above, the device isolation film forming method according to the present invention can prevent the boron of the P well from diffusing into the trench by forming a silicon germanium film in the trench sidewalls of the STI structure.

또한 P웰의 붕소의 농도를 일정하게 유지시켜 접합 누설 전류와 협폭 효과에 의해 소자의 특성악화를 막을 수 있다.In addition, the concentration of boron in the P well is kept constant to prevent deterioration of the device due to the junction leakage current and the narrow effect.

Claims (5)

반도체 기판에 패드 산화막 및 질화막을 형성한 후 트랜치 영역을 정의하는 단계;Defining a trench region after forming a pad oxide film and a nitride film on the semiconductor substrate; 상기 트랜치 영역의 상기 질화막, 상기 패드 산화막 및 상기 반도체 기판을 제거하여 상기 반도체 기판 내에 트랜치를 형성하는 단계;Removing the nitride film, the pad oxide film, and the semiconductor substrate in the trench region to form a trench in the semiconductor substrate; 상기 트랜치 측벽 내측의 상기 반도체 기판내에 실리콘 게르마늄막을 형성하는 단계;Forming a silicon germanium film in the semiconductor substrate inside the trench sidewalls; 상기 트랜치 측벽에 열 산화막을 형성하는 단계;Forming a thermal oxide film on the trench sidewalls; 전체 구조 상부에 HDP산화막을 형성한 후 상기 질화막이 노출되도록 평탄화공정을 수행하는 단계; 및Forming an HDP oxide film on the entire structure and then performing a planarization process to expose the nitride film; And 상기 질화막 및 패드 산화막을 제거하는 단계를 포함하여 이루어진 것을 특징으로 하는 소자 분리막 형성 방법.And removing the nitride film and the pad oxide film. 제 1 항에 있어서,The method of claim 1, 상기 실리콘 게르마늄막은 게르마늄이온주입 공정 후 급속 열처리 공정을 수행하여 형성되는 것을 특징으로 하는 소자 분리막 형성 방법.The silicon germanium layer is formed by performing a rapid heat treatment process after the germanium ion implantation process. 제 2 항에 있어서,The method of claim 2, 상기 게르마늄이온주입 공정은 이용하여 주입 에너지를 5 내지 20KeV로 하고 프로젝션 레인지를 50 내지 150Å으로 실시하는 것을 특징으로 하는 소자 분리막 형성 방법.The germanium ion implantation process is a device isolation film forming method characterized in that the implantation energy is set to 5 to 20 KeV and the projection range is 50 to 150 kW. 제 2 항에 있어서,The method of claim 2, 상기 게르마늄이온주입 공정시 게르마늄이온의 투여량은 1E15 또는 9E16/㎠인 것을 특징으로 하는 소자 분리막 형성 방법.In the germanium ion implantation process, the germanium ion dosage is 1E15 or 9E16 / ㎠ characterized in that the method for forming a device. 제 2 항에 있어서,The method of claim 2, 상기 급속 열처리 공정은 900 내지 1100℃의 온도에서 5 내지 30초간 실시하는 것을 특징으로 하는 소자 분리막 형성 방법.The rapid heat treatment process is a device isolation film forming method, characterized in that performed for 5 to 30 seconds at a temperature of 900 to 1100 ℃.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107785422A (en) * 2016-08-29 2018-03-09 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and its manufacture method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107785422A (en) * 2016-08-29 2018-03-09 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and its manufacture method
CN107785422B (en) * 2016-08-29 2021-07-13 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and manufacturing method thereof

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