KR20030048215A - Method for forming fine damascene pattern - Google Patents

Abstract

PURPOSE: A method for forming a fine damascene pattern in a semiconductor device is provided to easily obtain the fine damascene pattern of 0.13 micro meter below by reflowing resist. CONSTITUTION: A resist pattern having a space pattern of the first width(A) is formed on a semiconductor substrate(1). Reflowing process is performed to the resist pattern so as to form a reflowing resist pattern(2a) having a space pattern of the second width(B). At this time, the second width(B) is narrower than the first width(A). The resist reflow processing is carried out by heating using oven or hot plate at the temperature of 50-250°C.

Description

Method for forming fine damascene pattern {METHOD FOR FORMING FINE DAMASCENE PATTERN}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a fine damascene pattern using resist reflow.

As semiconductor fabrication techniques are developed, increasingly finer patterns are required in semiconductor fabrication processes of 0.13 μm or less. In addition, a damascene process is introduced in a semiconductor manufacturing process of 0.13 µm or less, and thus, a resist pattern formed by a photolithography process is a space pattern instead of a conventional line pattern. It is formed.

Here, the damascene process, in contrast to the conventional pattern formation process of etching the pattern formation layer using a resist pattern in the form of a line, forms a resist pattern in a space shape, and then embeds the pattern formation layer in the space to form a desired pattern. It is a way of forming.

On the other hand, the implementation of the fine pattern in the photolithography process has been proceeded simply by selecting a short wavelength of the light source used in the exposure apparatus. For example, conventionally, G-line (λ = 435 nm) or I-line (λ = 365 nm) light sources have been mainly used. The above light sources can form patterns of fine line widths required for highly integrated devices. Therefore, recently, a light source of KrF (λ = 248 nm) has been used.

However, although the DUV (Deep UV) process using the KrF light source can form a 0.13 μm line pattern, it is difficult to form a pattern of 0.13 μm or less due to the resolution limitation of the light source. In addition, in the damascene process, since the photolithography process must be performed on the oxide-based film having high transmittance, a problem of CD uniformity of the resist pattern occurs even when an antireflection film is used, which makes it difficult to form a fine pattern.

Recently, an exposure technique using an ArF (λ = 193 nm) light source having a shorter wavelength than a KrF light source has been proposed, and in fact, an exposure process using an ArF light source instead of a KrF light source is considered in the 0.10 μm technology. In order to replace the ArF light source is another problem that requires a huge investment in equipment.

Accordingly, an object of the present invention is to provide a method for forming a fine damascene pattern that can realize a fine damascene pattern of 0.13 μm or less while using a KrF light source as it is.

1A and 1B are cross-sectional views illustrating a method for forming a fine damascene pattern according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1 semiconductor substrate 2 resist pattern

2a: Reflowed resist pattern

The method for forming a fine damascene pattern of the present invention for achieving the above object is a method for forming a damascene pattern having a space of fine width in a pattern formation process using a damascene process, Forming a resist pattern having a space pattern of one width; And reflowing the resist pattern to have a space pattern of a second width smaller than the first width, wherein the resist reflow is performed using an oven or hot plate heating method. It is carried out at 50 to 250 ℃.

According to the present invention, by reducing the width of the space pattern through the reflow of the resist, it is possible to easily implement a fine damascene pattern while using a conventional KrF light source.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A and 1B are cross-sectional views illustrating a method of forming a fine damascene pattern according to an embodiment of the present invention.

First, as shown in FIG. 1A, a process of coating, exposing, and developing a resist on a semiconductor substrate 1 having a predetermined lower pattern (not shown) is performed in order to obtain a width larger than the actual width (A). The resist pattern 2 which has a space of ()) is formed.

Then, the substrate 1 is heated to 50 to 250 ° C. by using an oven or hot plate heating method, and thereby, the resist pattern 2 formed on the substrate 1 is formed. Reflow

At this time, as the resist pattern 2 is reflowed, as shown in FIG. 1B, the width B of the space pattern implemented by the reflowed resist pattern 2a is defined by the resist pattern ( It becomes smaller than the width A of the space pattern implemented by 2).

Accordingly, since the CD of the space pattern is reduced simply by resist reflow, it is possible to obtain a fine space very easily, and eventually, to form a fine damascene pattern very easily.

In other words, the present invention can obtain a desired degree of CD reduction in the damascene pattern by applying a suitable temperature of heat to the substrate on which the resist pattern is formed, so that the existing KrF light source is kept as it is. Even if it is used, the damascene pattern below the resolution limit of an exposure apparatus can be obtained easily.

In FIG. 1B, the dotted lines represent the resist pattern before reflow.

As described above, the present invention can easily implement a fine damascene pattern that can not be implemented by the conventional exposure apparatus by using a resist reflow, and thus can be very advantageously applied to the manufacture of highly integrated devices.

In addition, since it is possible to implement a 0.13㎛ class device using the existing KrF light source as it is, no additional equipment investment cost is required, thereby reducing the cost.

Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (3)

In the pattern formation process using a damascene process, a method for forming a damascene pattern having a space of fine width, Forming a resist pattern having a space pattern of a first width on the semiconductor substrate; And And reflowing the resist pattern to have a space pattern of a second width smaller than the first width. The method of claim 1 wherein the resist reflow is Method for forming a fine damascene pattern, characterized in that carried out by an oven or hot plate heating method. The method of claim 2, wherein the resist reflow is performed at 50 to 250 ° C. 4.