KR20030047020A - High voltage generator - Google Patents

Abstract

PURPOSE: A high voltage generator is provided to generate high voltages according to each bank and reduce an area of a layout by improving a structure of the high voltage generator. CONSTITUTION: A high voltage generator includes a high voltage sensing portion(100), a plurality of oscillator portions(110,120,130,140), and a plurality of pump portions(112,122,132,142). The high voltage sensing portion receives bank active signals corresponding to the number of banks, compares a high voltage level with a core voltage level to sense the high voltage level lower than the core voltage level, and outputs a sense signal. The oscillator portions outputs periodically pulse signals according to the sense signal. The pump portions correspond to outputs of the oscillator portions and supply electric charges to an output terminal.

Description

High voltage generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage generator, and more particularly, to a high voltage generator in which a high voltage detection unit is formed regardless of a bank.

In general, a semiconductor device generates and uses a high voltage VPP higher than a power supply voltage VDD when driving a word line of a DRAM device.

1 is a block diagram showing a conventional high voltage generator.

Referring to FIG. 1, the high voltage generator receives the final output high voltage as a feed-back, and compares the high voltage VPP and the power supply voltage CVDD to detect the level down of the high voltage. 41), the oscillator section (12,22,32,42) and the oscillator section (12,22,32,42) for generating a predetermined clock based on the value output from the high voltage sensing section to control the high voltage pumping drive stage. High voltage pump pumping the voltage under the control of the control unit (13, 23, 33, 43) and the control unit (13, 23, 33, 43) to pump the high voltage (VPP) leveled down again according to the output clock It consists of parts 14, 24, 34 and 44.

FIG. 2 is a circuit diagram illustrating the high voltage detector of FIG. 1.

Referring to FIG. 2, the high voltage detectors 11, 21, 31, and 41 are connected in series with the first, second, and third channel MOSs to which the internal voltage CVDD is applied to the gate and the high voltage VPP is applied to one side. Transistors MP1, MP2, and MP3, and fourth, fifth, and sixth channel MOS transistors MP4, MP5, and MP6 connected in series with a ground power supply VSS to a gate and an internal voltage CVDD to one side thereof; First and third N-channel MOS transistors MN1 and MN3 connected to the third P-channel MOS transistor MP3 and the sixth P-channel MOS transistor MP6, respectively, to form a current mirror, and the first and third N-channel Second and fourth N-channel MOS transistors MN2 and MN4 that connect the MOS transistors MN1 and MN3 and the ground power supply VSS, respectively, and receive the output of the first inverter I1 to the gate, and bank active. The fourth and fifth inverters I4 and I5 that receive and buffer the signal, and the first and second inverters I1 which receive and invert the output of the fourth inverter I4; Second and third inverters I2 and I3 that are inputted and buffered and output from a common terminal of a six-channel MOS transistor MP6 and a third N-channel MOS transistor MN3, and a third inverter I3 and a fifth inverter. The first enable signal is input to the second input first NAND gate NAND1 receiving the output of I5 and the first NAND gate NAND1 to the oscillator units 12, 22, 32, and 42 at the rear stage. and sixth, seventh, and eighth inverters I6, I7, and I8 that output (enable signal1).

FIG. 3 is a circuit diagram illustrating the oscillator part of FIG. 1.

Referring to FIG. 3, the oscillator units 12, 22, 32, and 43 are the ninth, 10, 11, 12, 13, and 14 inverters (I9, I10, I11, I12, I13, I14) that constitute the ring oscillator. 15, 16, 17 inverters I15, I16, and I17 which output the second enable signal 2 by inverting the output of the I / O and the first NOR gate NOR1 and the fourteenth inverter I14. And a first NAND gate NAND1 that receives the first enable signal 1 and the power-up signal pwrup and outputs the first enable signal NOR1 to the first NOR gate NOR1.

4 is a circuit diagram illustrating a control unit of FIG. 1.

Referring to FIG. 4, the control units 13, 23, 33, and 43 are supplied with an external power supply vext to one side, and the seventh and eighth channel MOS transistors MP7 and MP8 having their gates cross-coupled with each other. ) And the fifth and sixth N-channel MOS transistors MN5, which connect the other side of the seventh and eighth P-channel MOS transistors MP7 and MP8 and receive a second enable signal and its inverted signal to the gate. MN6) and inputs 22, 23, 24, 25, 26, and 27 inverters (I22, I23) connected in series to an common terminal of an eighth P-channel MOS transistor MP8 and a sixth N-channel MOS transistor MN6. , I24, I25, I26, and I27, the output N2 of the twenty-third inverter I23, the second input second NOR gate NOR2 receiving the ground power, and the output of the second NOR gate NOR2 Receiving the 28th, 29th and 30th inverters I28, I29, and I30 that output the first third enable signal (enable signal3_p1), the output N2 and the external power source vext of the 23rd inverter I23. 2nd input 34th and 35th inverters I34 and I35 for buffering the output of the drain gate NAND2 and the second NAND gate NAND2 to output a second third enable signal enable_signal3_p2, and the 23rd inverter I23 A third third enable signal (enable_signal3_g2) by inverting the output of the second input third NAND gate NAND3 and the third NAND gate NAND3 receiving the output N2 and the output N2 of the 27th inverter I27. 2nd input third to receive the 31st, 32nd and 33th inverters I31, I32, and I33 which outputs?), The output N2 of the 23rd inverter I23 and the output N2 of the 27th inverter I27. The NOR3 and the 36th and 37th inverters I36 and I37 output the fourth third enable signal enable_signal3_g1 by inverting the output of the third NORgate NOR3.

FIG. 5 is a circuit diagram illustrating the pump part of FIG. 1. FIG.

Referring to FIG. 5, the pump units 14, 24, 34, and 44 have the third and fourth third enable signals enable_signal3_g1 and enable_signal3_g1 applied to one side at different timings, and the nodes N7 and N8 to the other side. The ninth and twelfth NMOS transistors MN9 and MN12 that are diode-connected between capacitors C1 and C3 each having a MOS transistor connected to each other, an external power supply vext, and nodes N3 and N4, respectively. And the tenth and twelfth n-channel MOS transistors MN3 and MN4 connected in a cross-coupling structure between an external power supply vext applying end and the nodes N9 and N10, and gates are respectively provided to the nodes N9 and N10. 7th and 8th NMOS transistors MN7 and MN8 connected between an external power supply Vext terminal and nodes N7 and N8, respectively, and the first and second third enable signals enable signal 3_p1 and enable to one side. Capacitor consisting of MOS transistors connected to nodes N7 and N8 on the other side, respectively, after receiving signal3_p2) It consists of (C2, C4), and the 9,10 P channel MOS transistors, respectively connected between the high voltage generating stage (VPP) and the node (N1, N2) and a gate input coupled to the cross-coupling structure (MP9, MP10).

Hereinafter, the operation of the high voltage generator will be described with reference to FIGS. 1 to 5.

First, the high voltage generator generates and provides a high voltage required by the DRAM device, and redetects the generated high voltage to determine the level of the high voltage.If the level is down, the high voltage generator operates the pumping means. Will raise the action again.

In addition, in order to control the generation of the high voltage (VPP) for each bank, the high voltage sensing units 11, 21, 31, 41, oscillator units 12, 22, 32, 42, and control units 13, 23, 33, 43 for each bank. And pump sections 14, 24, 34 and 44. In this way, when the current of Icc1 flows, it can produce high voltage with less power consumption than when the current of Icc5 flows. Where Icc1 is an operating current per cycle and Icc5 is a standby current for CMOS inputs.

The high voltage detectors 11, 21, 31, and 41 use active signals for respective banks as inputs, but are mainly divided into four banks in Sync DRAM and DDR DRAM. That is, in order to control the generation of high voltage for each bank, a high voltage sensing unit should be provided as many as the number of banks. The problem caused by this use is that all four high voltage detectors must be operated during standby, consuming a large amount of current, and the layout area is increased.

In the standby mode, when all four high voltage detectors are in a ready state for detecting a high voltage, when the high voltage detector becomes lower than a desired level, the pump unit is operated through the oscillator and the controller so that the high voltage (VDD) is applied. Keep it at the desired level. However, since the part that consumes the most current in the high voltage generator is the high voltage detector, when one high voltage detector operates and pumps, the high voltage (VDD) is maintained and the high voltage detector of the other bank cannot function as the high voltage detector. Will not work.

An object of the present invention is to provide a high voltage generator capable of generating a high voltage for each bank while operating at low power and having a reduced layout area.

1 is a block diagram showing a conventional high voltage generator.

FIG. 2 is a circuit diagram illustrating the high voltage detector of FIG. 1. FIG.

3 is a circuit diagram showing an oscillator section of FIG.

4 is a circuit diagram showing a control unit of FIG.

FIG. 5 is a circuit diagram showing a pump part of FIG. 1; FIG.

6 is a block diagram showing a high voltage generator according to a preferred embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating the high voltage detector of FIG. 6. FIG.

FIG. 8 is a circuit diagram showing an oscillator part of FIG. 6; FIG.

<Description of the symbols for the main parts of the drawings>

100: high voltage detection unit

110,120,130,140: Oscillator

111,121,131,141: control unit

112,122,132,142: Pump part

In order to achieve the above object, according to an aspect of the present invention is received according to at least one bank active signal as the number of provided bank active signal is enabled, and the high voltage by comparing the high voltage level and the core voltage level A high voltage detection unit for outputting a signal for detecting when a level is relatively smaller than the core voltage level; An oscillator unit periodically outputting a pulse signal according to the sensing signal and the bank active signal and provided with the number of banks; And a pump unit for supplying charge to maintain the voltage level of the output terminal at the high voltage level corresponding to the output of the oscillator unit, respectively.

The basic concept of the present invention is to put a high voltage detection unit in a high voltage generator and perform bank-specific operations normally using a bank active signal. To do this, a method of controlling the final pump section by using the bank active signal as the input signal of the oscillator section and enabling or disabling the oscillator is used.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

6 is a block diagram showing a high voltage generator according to a preferred embodiment of the present invention.

Referring to FIG. 6, the high voltage generator receives the final output high voltage as a feed-back and compares the high voltage VPP and the power supply voltage CVDD to detect the level down of the high voltage, and a high voltage detection unit. The oscillator units 110, 120, 130, and 140 controlling the high voltage pumping driving stage by generating a predetermined clock based on the value output from the unit 100 and the high voltage VPP leveled down according to the clock output from the oscillator units 110, 120, 130, and 140 are normally returned. The control unit 111, 121, 131, 141 to be pumped, and the high voltage pump unit 112, 122, 132, 142 to pump the voltage under the control of the control unit (111, 121, 131, 141).

FIG. 7 is a circuit diagram illustrating the high voltage detector of FIG. 6.

Referring to FIG. 7, the high voltage detector 100 outputs a voltage comparator 101 for comparing the high voltage VPP and the internal voltage CVDD, and a driver for enabling a signal (enable signal1) for enabling an oscillator at a later stage. The unit 102 and the high voltage detecting unit _ enable unit 103 for enabling the high voltage detecting unit according to any one of the bank active signals bank active 0, 1, 2, 3, and 4 are configured.

The voltage comparator 101 is a series-connected eleventh, twelve, thirteen-channel MOS transistors MP11, MP12, and MP13 that receive an internal voltage CVDD through a gate and a high voltage VPP to one side thereof, and a ground power supply through a gate. (14), 15, 16 P-channel MOS transistors (MP14, MP15, MP16) connected in series and (13) P-channel MOS transistors (MP13) and 16-P are connected to each other by (VSS) and an internal voltage (CVDD) to one side. It is composed of thirteenth and fifteenth n-channel MOS transistors MN13 and MN15 that are connected to the channel MOS transistor MP16 and form a current mirror.

The high voltage sensing unit _ enable unit 103 connects the thirteenth and fifteenth N-channel MOS transistors MN13 and MN15 and the ground power supply VSS, respectively, and receives the output of the third inverter IN3 through a gate. 16 N-channel MOS transistors MN14 and MN16, a fourth NOR gate NOR4 for receiving and outputting four bank active signals 4 and 4 and a fourth NOR gate inverting the output of the fourth NOR gate. And 5,6 inverters IN4, IN5, and IN6, and a third inverter IN3 that receives and inverts the output of the fifth inverter IN5.

The driver unit 102 receives the first and second inverters IN1 and IN2 which are inputted from the common terminal of the sixteenth P-channel MOS transistor MP16 and the fifteenth N-channel MOS transistor MN15, and are buffered and output. Inverting the outputs of the second input fourth NAND gate NAND4 and the fourth NAND gate NAND4 receiving the outputs of the IN2 and the sixth inverter IN6 and enabling the first to the oscillator units 110, 120, 130, and 140 of the rear stage. And seventh, eighth and ninth inverters IN7, IN8, and IN9 for outputting a signal (enable signal1).

FIG. 8 is a circuit diagram illustrating an oscillator part of FIG. 6.

Referring to FIG. 8, the oscillator units 110, 120, 130, and 140 are the ninth, 10, 11, 12, 13, and 14 inverters (IN9, IN10, IN11, IN12, IN13, IN14, IN15) and the fifth constituting the ring oscillator. 15th, 16th, 17th inverters IN15, IN16, and IN17 that output the second enable signal 2 by inverting the output of the NOR gate NOR5 and the twelfth inverter IN12, and the first enable. And a third input fifth NAND gate NAND5 that receives a signal enable signal1, a power-up signal pwrup, and bank active signals bank active0 to 4 and outputs the same to the fifth knock gate NOR5.

6 to 8, the operation of the high voltage generator will be described.

First, the high voltage detection unit 100 receives a voltage and an idle signal at a level corresponding to a high voltage VPP corresponding to a voltage and an internal voltage CVDD. The idle signal is a signal indicating that one bank is active in any bank, and when this signal is input, the high voltage VPP level is compared with the internal voltage CVDD. In this case, when the high voltage VPP level is lower than the internal voltage CVDD level, the first enable signal for driving the pump unit is output.

Conventionally, one high voltage detection unit is required per bank active signal, so that a high voltage detection unit is required by the number of banks. However, only one high voltage detection unit is required by controlling the oscillator unit using the bank active signal. This also reduces the current consumed by the high voltage detector and reduces the layout area.

On the other hand, the oscillator unit 110, 120, 130, 140 receives a bank active signal (bank active 0 ~ 3) to use as a control signal to properly adjust the amount of current used by the high voltage (VPP) generator according to the number of active banks. That is, by driving only the oscillator necessary for operation, unnecessary current can be reduced.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, it is possible to implement a high voltage generator capable of operating at low power and controlling each bank while reducing layout area.

Claims (3)

Receives as many bank active signals as the number of provided banks and is enabled according to at least one bank active signal, and compares a high voltage level with a core voltage level to detect when the high voltage level becomes relatively smaller than the core voltage level. A high voltage detector for outputting a detection signal; A plurality of oscillator units provided with the number of banks and periodically outputting a pulse signal according to the detection signal; And A plurality of pump units respectively corresponding to the outputs of the oscillator unit and supplying electric charges to the output stages to maintain the voltage levels of the output stages at the high voltage levels. High voltage generator comprising a. The method of claim 1, The high voltage detection unit, A voltage comparing unit comparing the high voltage level with the core voltage level; A driver unit outputting the detection signal according to the output of the voltage comparing unit; And And a high voltage detector _ enable unit for enabling the high voltage detector according to at least one of the bank active signals. The method of claim 1, The oscillator unit, And the high voltage generator is enabled according to one of the bank active signals.