KR20030045469A - Capacitor of semiconductor device and method for manufacturing the same - Google Patents
Capacitor of semiconductor device and method for manufacturing the same Download PDFInfo
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- KR20030045469A KR20030045469A KR1020010076193A KR20010076193A KR20030045469A KR 20030045469 A KR20030045469 A KR 20030045469A KR 1020010076193 A KR1020010076193 A KR 1020010076193A KR 20010076193 A KR20010076193 A KR 20010076193A KR 20030045469 A KR20030045469 A KR 20030045469A
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- layer
- lower electrode
- contact hole
- capacitor
- conductive layer
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- 239000003990 capacitor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 title claims description 26
- 239000010410 layer Substances 0.000 claims description 87
- 239000011229 interlayer Substances 0.000 claims description 17
- 239000007789 gas Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 238000005452 bending Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 3
- 239000012495 reaction gas Substances 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 238000007865 diluting Methods 0.000 claims 2
- 230000010354 integration Effects 0.000 abstract description 5
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052707 ruthenium Inorganic materials 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 25
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- 229910008484 TiSi Inorganic materials 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000005054 agglomeration Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- IKGXIBQEEMLURG-NVPNHPEKSA-N rutin Chemical compound O[C@@H]1[C@H](O)[C@@H](O)[C@H](C)O[C@H]1OC[C@@H]1[C@@H](O)[C@H](O)[C@@H](O)[C@H](OC=2C(C3=C(O)C=C(O)C=C3OC=2C=2C=C(O)C(O)=CC=2)=O)O1 IKGXIBQEEMLURG-NVPNHPEKSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
- H10D1/712—Electrodes having non-planar surfaces, e.g. formed by texturisation being rough surfaces, e.g. using hemispherical grains
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/01—Manufacture or treatment
- H10D1/041—Manufacture or treatment of capacitors having no potential barriers
- H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/694—Electrodes comprising noble metals or noble metal oxides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
- H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체 소자의 캐패시터 및 그의 제조 방법에 관한 것으로, 특히 요(凹) 구조의 캐패시터의 제조 방법에 있어서, 캐패시터 콘택홀에 평평한 표면을 갖는 제 1 루테늄(Ru)층과 울퉁불퉁한 표면을 갖는 제 2 Ru층의 적층 구조를 포함하여 하부전극을 형성하므로, 상기 하부전극의 유효 면적 증가로 캐패시턴스(Capacitance)가 증가되므로 0.10㎛ 이하의 설계가 가능하여 소자의 특성 및 집적도를 향상시키는 특징이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor device and a method of manufacturing the same. In particular, in a method of manufacturing a capacitor having a yaw structure, the first ruthenium (Ru) layer having a flat surface in the capacitor contact hole and an uneven surface are provided. Since the lower electrode is formed to include the second Ru layer, the capacitance is increased due to the increase of the effective area of the lower electrode, so that design of 0.10 μm or less is possible, thereby improving the characteristics and integration of the device. .
Description
본 발명은 반도체 소자의 캐패시터 및 그의 제조 방법에 관한 것으로, 특히 요(凹) 구조의 캐패시터의 제조 방법에 있어서, 캐패시터 콘택홀에 평평한 표면을 갖는 제 1 루테늄(Ru)층과 울퉁불퉁한 표면을 갖는 제 2 Ru층의 적층 구조를 포함하여 하부전극을 형성하므로 소자의 특성 및 집적도를 향상시키는 반도체 소자의 캐패시터 및 그의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor device and a method of manufacturing the same. In particular, in a method of manufacturing a capacitor having a yaw structure, the first ruthenium (Ru) layer having a flat surface in the capacitor contact hole and an uneven surface are provided. The present invention relates to a capacitor of a semiconductor device and a method of manufacturing the same, in which a lower electrode is formed including a stacked structure of a second Ru layer, thereby improving the characteristics and integration of the device.
일반적으로 캐패시터의 용량은Generally, the capacity of a capacitor
(극판의 면적×층간물질의 유전상수)÷(양극판의 간격)(Area of positive electrode plate × dielectric constant of interlayer material) ÷ (gap of positive electrode plate)
으로 표시된다. 상기 캐패시터의 용량을 증가시키기 위해서 극판의 면적을 크게하거나 유전물질의 유전 상수를 높이기 위해 유전율이 큰 새로운 유전물질의 개발에 노력하여 왔다.Is displayed. In order to increase the capacity of the capacitor, efforts have been made to develop a new dielectric material having a high dielectric constant in order to increase the area of the electrode plate or increase the dielectric constant of the dielectric material.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 캐패시터 제조 방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the prior art.
도 1a를 참조하면, 반도체 기판(11) 상에 제 1 콘택홀(부호화 하지 않음)을 구비한 층간 산화막(13)을 형성한다.Referring to FIG. 1A, an interlayer oxide film 13 having a first contact hole (not encoded) is formed on a semiconductor substrate 11.
그리고, 상기 제 1 콘택홀을 포함한 전면에 다결정 실리콘층을 형성한 후, 전면 식각 공정으로 상기 다결정 실리콘층을 식각하여 실리콘(Si) 플러그(Plug)(15)를 형성한다.After the polycrystalline silicon layer is formed on the entire surface including the first contact hole, the polycrystalline silicon layer is etched by the front surface etching process to form a silicon (Si) plug 15.
이어, 전면 식각 공정으로 상기 Si 플러그(15)의 상부 일부분을 식각한다.Subsequently, an upper portion of the Si plug 15 is etched by the front etching process.
그리고, 상기 Si 플러그(15)를 포함한 전면에 티타늄(Ti)층(도시하지 않음)을 형성한 후, 전면의 열처리 공정으로 상기 Si 플러그(15)와 Ti층을 반응시켜 TiSi2층(17)을 형성한다.Then, a titanium (Ti) layer (not shown) is formed on the entire surface including the Si plug 15, and then the Si plug 15 and the Ti layer are reacted with each other by a heat treatment process on the entire surface of the TiSi 2 layer 17. To form.
그 후, 상기 Ti층을 제거하고, 상기 TiSi2층(17)을 포함한 전면에 TiN층(19)을 형성한 다음, 상기 층간 산화막(13)을 식각 방지막으로 사용하는 화학적 기계 연마 방법에 의해 상기 TiN층(19)을 평탄 식각한다.Thereafter, the Ti layer is removed, a TiN layer 19 is formed on the entire surface including the TiSi 2 layer 17, and then the chemical mechanical polishing method using the interlayer oxide layer 13 as an etch stop layer. The TiN layer 19 is etched flat.
도 1b를 참조하면, 상기 TiN층(19)을 포함한 전면에 질화막(21)과 산화막(23)을 순차적으로 형성한다.Referring to FIG. 1B, the nitride film 21 and the oxide film 23 are sequentially formed on the entire surface including the TiN layer 19.
그리고, 캐패시터 콘택 마스크를 사용한 사진 식각 공정에 의해 상기 산화막(23)을 식각한 후, 상기 질화막(21)을 식각하여 제 2 콘택홀(25)을 형성한다.The oxide layer 23 is etched by a photolithography process using a capacitor contact mask, and then the nitride layer 21 is etched to form a second contact hole 25.
도 1c를 참조하면, 상기 제 2 콘택홀(25)을 포함한 산화막(23) 상에 Ru층의 하부전극(27)을 형성한다.Referring to FIG. 1C, the bottom electrode 27 of the Ru layer is formed on the oxide film 23 including the second contact hole 25.
도 1d를 참조하면, 상기 하부전극(27) 상에 Ta2O5박막의 유전막(29) 그리고 상부전극(31)을 순차적으로 형성한다.Referring to FIG. 1D, a dielectric film 29 and an upper electrode 31 of a Ta 2 O 5 thin film are sequentially formed on the lower electrode 27.
그러나 종래의 유전율이 약 25 ∼ 50인 Ta2O5박막을 사용한 캐패시터의 제조 방법에 있어서, 하부전극으로 Ru, 백금(Pt) 등 단층의 귀금속을 사용하여 캐패시턴스(Capacitance)를 증가시키는 것에 한계가 있어 소자의 특성 및 집적화가 저하되는 문제점이 있었다.However, in the conventional method for manufacturing a capacitor using a Ta 2 O 5 thin film having a dielectric constant of about 25 to 50, there is a limit to increasing capacitance using a single layer of precious metal such as Ru and platinum (Pt) as the lower electrode. There is a problem that the characteristics and integration of the device is reduced.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 요(凹) 구조의 캐패시터의 제조 방법에 있어서, 캐패시터 콘택홀에 평평한 표면을 갖는 제 1 루테늄(Ru)층과 울퉁불퉁한 표면을 갖는 제 2 Ru층의 적층 구조를 포함하여 하부전극을 형성하므로, 상기 하부전극의 유효 면적을 증가시키는 반도체 소자의 캐패시터 및 그의 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in the manufacturing method of a capacitor having a yaw structure, a first Ru having a flat surface in the capacitor contact hole and a second Ru having an uneven surface. It is an object of the present invention to provide a capacitor of a semiconductor device and a method of manufacturing the same, since the lower electrode is formed to include a stacked structure of layers, thereby increasing the effective area of the lower electrode.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 캐패시터 제조 방법을 도시한 단면도.1A to 1D are cross-sectional views showing a capacitor manufacturing method of a semiconductor device according to the prior art.
도 2a 내지 도 2e는 본 발명의 실시 예에 따른 반도체 소자의 캐패시터 제조 방법을 도시한 단면도.2A through 2E are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
11, 41 : 반도체 기판13, 43 : 층간 산화막11, 41: semiconductor substrate 13, 43: interlayer oxide film
15, 45 : Si 플러그17, 47 : TiSi2층15, 45: Si plug 17, 47: TiSi 2 layer
19, 49 : TiN층21, 51 : 질화막19, 49: TiN layer 21, 51: nitride film
23, 53 : 산화막25, 55 : 제 2 콘택홀23, 53: oxide film 25, 55: second contact hole
27 : 하부전극29, 61 : 유전막27: lower electrode 29, 61: dielectric film
31, 63 : 상부전극57 : 제 1 Ru층31, 63: upper electrode 57: first Ru layer
59 : 제 2 Ru층59: second Ru layer
본 발명의 반도체 소자의 캐패시터는 기판 상에 제 1 콘택홀을 구비하며 형성되는 층간 절연막, 상기 제 1 콘택홀의 매립층인 플러그, 상기 층간 절연막 상에 하부전극용 콘택홀을 구비하며 형성되는 절연막, 상기 하부전극용 콘택홀 내면에 형성되는 요(凹) 구조의 제 1 하부전극, 상기 제 1 하부전극 상에 표면이 굴곡되어 형성되며 상기 제 1 하부전극과 동일한 물질인 제 2 하부전극 및 상기 하부전극 상에 순차적으로 형성되는 유전막과 상부전극을 포함하여 구성됨을 특징으로 한다.The capacitor of the semiconductor device of the present invention includes an interlayer insulating film formed with a first contact hole on a substrate, a plug which is a buried layer of the first contact hole, an insulating film formed with a contact hole for a lower electrode on the interlayer insulating film, and A first lower electrode having a concave structure formed on an inner surface of the contact hole for the lower electrode, a second lower electrode and the lower electrode formed of a curved surface on the first lower electrode and of the same material as the first lower electrode. It characterized in that it comprises a dielectric film and the upper electrode sequentially formed on the.
그리고 본 발명의 반도체 소자의 캐패시터 제조 방법은 기판 상에 제 1 콘택홀을 구비한 층간 절연막을 형성하는 단계, 상기 제 1 콘택홀의 매립층인 플러그를 형성하는 단계, 상기 플러그를 포함한 층간 절연막 상에 하부전극용 콘택홀을 구비한 절연막을 형성하는 단계, 상기 하부전극용 콘택홀을 포함한 절연막 상에 제 1 도전층을 형성하는 단계, 상기 제 1 도전층보다 낮은 밀도의 제 2 도전층을 상기 제 1 도전층 상에 형성하되, 상기 제 2 도전층을 상기 제 1 도전층과 동일한 물질로 형성하는 단계, 전면의 열처리 공정으로 상기 제 2 도전층의 표면의 굴곡을 발생시키는 단계, 상기 절연막 상의 제 1, 제 2 도전층을 전면 식각하여 요(凹) 구조의 하부전극을 형성하는 단계 및 상기 하부전극 상에 유전막과 상부전극을 순차적으로 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The method for manufacturing a capacitor of a semiconductor device according to the present invention includes forming an interlayer insulating film having a first contact hole on a substrate, forming a plug that is a buried layer of the first contact hole, and forming a lower layer on the interlayer insulating film including the plug. Forming an insulating film having an electrode contact hole, forming a first conductive layer on the insulating film including the lower electrode contact hole, and forming a second conductive layer having a lower density than the first conductive layer. Forming a second conductive layer on the conductive layer, the second conductive layer being formed of the same material as the first conductive layer, and generating bending of the surface of the second conductive layer by an entire heat treatment process; And etching the entire surface of the second conductive layer to form a lower electrode having a concave structure, and sequentially forming a dielectric film and an upper electrode on the lower electrode. It is characterized by that.
본 발명의 원리는 요(凹) 구조의 캐패시터의 제조 방법에 있어서, 캐패시터 콘택홀에 평평한 표면을 갖는 제 1 Ru층과 울퉁불퉁한 표면을 갖는 제 2 Ru층의 적층 구조를 포함하여 하부전극을 형성하므로, 상기 제 2 Ru층의 울퉁불퉁한 표면에 의해 상기 하부전극의 유효 면적을 증가시켜 캐패시턴스를 증가시키므로 소자의 특성 및 집적도를 향상시키는 발명이다.The principle of the present invention is a method of manufacturing a capacitor having a yaw structure, the lower electrode including a laminated structure of a first Ru layer having a flat surface and a second Ru layer having an uneven surface in the capacitor contact hole to form a lower electrode Therefore, the present invention improves the characteristics and integration of the device because the capacitance is increased by increasing the effective area of the lower electrode by the uneven surface of the second Ru layer.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명의 실시 예에 따른 반도체 소자의 캐패시터 제조 방법을 도시한 단면도이다.2A through 2E are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 반도체 기판(41) 상에 제 1 콘택홀(부호화 하지 않음)을 구비한 층간 산화막(43)을 형성한다. 이때, 상기 층간 산화막(43)을 2000 ∼ 10000Å 두께의 SiO2층으로 형성한다.Referring to FIG. 2A, an interlayer oxide film 43 having a first contact hole (not encoded) is formed on the semiconductor substrate 41. At this time, the interlayer oxide film 43 is formed of a SiO 2 layer having a thickness of 2000 to 10000 Pa.
그리고, 상기 제 1 콘택홀을 포함한 전면에 다결정 실리콘층을 형성한 후, 전면 식각 공정으로 상기 다결정 실리콘층을 식각하여 Si 플러그(45)를 형성한다.After the polycrystalline silicon layer is formed on the entire surface including the first contact hole, the polycrystalline silicon layer is etched by the front surface etching process to form the Si plug 45.
이어, 전면 식각 공정으로 상기 Si 플러그(45)의 상부 일부분을 식각한다.Subsequently, an upper portion of the Si plug 45 is etched by the front etching process.
그리고, 상기 Si 플러그(45)를 포함한 전면에 Ti층(도시하지 않음)을 형성한 후, 전면의 열처리 공정으로 상기 Si 플러그(45)와 Ti층을 반응시켜 TiSi2층(47)을 형성한다.After the Ti layer (not shown) is formed on the entire surface including the Si plug 45, the Si plug 45 and the Ti layer are reacted with each other to form a TiSi 2 layer 47. .
그 후, 상기 Ti층을 제거하고, 상기 TiSi2층(47)을 포함한 전면에 TiN층(49)을 형성한 다음, 상기 층간 산화막(43)을 식각 방지막으로 사용하는 화학적 기계 연마 방법에 의해 상기 TiN층(49)을 평탄 식각한다.Thereafter, the Ti layer is removed, a TiN layer 49 is formed on the entire surface including the TiSi 2 layer 47, and then the chemical mechanical polishing method using the interlayer oxide layer 43 as an etch stop layer. The TiN layer 49 is etched flat.
도 2b를 참조하면, 상기 TiN층(49)을 포함한 전면에 질화막(51)과 산화막(53)을 순차적으로 형성한다.Referring to FIG. 2B, the nitride film 51 and the oxide film 53 are sequentially formed on the entire surface including the TiN layer 49.
그리고, 캐패시터 콘택 마스크를 사용한 사진 식각 공정에 의해 상기 산화막(53)을 식각한 후, 상기 질화막(51)을 식각하여 제 2 콘택홀(55)을 형성한다.After the oxide layer 53 is etched by a photolithography process using a capacitor contact mask, the nitride layer 51 is etched to form a second contact hole 55.
도 2c를 참조하면, 상기 제 2 콘택홀(55)을 포함한 산화막(53) 상에 100 ∼ 200Å 두께의 제 1 Ru층(57)을 형성한다. 이때, 상기 제 1 Ru층(57)을 300 ∼ 500℃의 온도 하에 Ru(od)3을 소스 가스로 하고 O2또는 NH3를 반응 가스로 하며 아르곤(Ar)을 희석 가스로 하는 MOCVD(Metal Organic CVD) 증착 방법으로 형성하기 때문에 상기 제 1 Ru층(57)은 고밀도이며 표면이 평평한 막이다.Referring to FIG. 2C, a first Ru layer 57 having a thickness of 100 to 200 μm is formed on the oxide film 53 including the second contact hole 55. At this time, MOCVD (Metal) using Ru (od) 3 as a source gas, O 2 or NH 3 as a reaction gas, and argon (Ar) as a diluent gas under the temperature of 300 to 500 ° C. The first Ru layer 57 is a high density and flat surface film because of the organic CVD deposition method.
도 2d를 참조하면, 상기 제 1 Ru층(57) 상에 100 ∼ 200Å 두께의 제 2 Ru층(59)을 형성한다. 이때, 상기 제 2 Ru층(59)을 상기 제 1 Ru층(57)의 형성 공정보다 저온인 200 ∼ 300℃의 온도 하에 진행하고 그 외는 상기 제 1 Ru층(57)과 동일한 공정을 진행하여 형성한다. 상기 제 2 Ru층(59)을 저온에서 형성하기 때문에 상기 제 2 Ru층(59)은 밀도가 낮고 표면이 거칠게 된다.Referring to FIG. 2D, a second Ru layer 59 having a thickness of 100 to 200 μs is formed on the first Ru layer 57. At this time, the second Ru layer 59 is carried out at a temperature of 200 to 300 ° C., which is lower than the process of forming the first Ru layer 57, and otherwise, the same process as the first Ru layer 57 is performed. Form. Since the second Ru layer 59 is formed at a low temperature, the second Ru layer 59 has a low density and a rough surface.
그리고, RTP(Rapid Thermal Process) 또는 전기로에서 질소분위기 하에 600∼ 800℃의 온도로 전면의 열처리 공정을 실시한다. 이때, 상기 열처리 공정으로 고밀도의 상기 제 1 Ru층(57)은 표면 변화가 없으나 저밀도 다공질인 상기 제 2 Ru층(59)은 뭉침현상(A)이 발생된다. 상기 뭉침현상(A)으로 상기 제 1 Ru층(57)에 의해서 막의 연속성이 깨어지지 않으면서 상기 제 2 Ru층(59)의 표면만 울퉁불퉁(A)하게 되어 요(凹) 구조의 하부전극의 유효면적이 증가된다.Then, the entire heat treatment process is performed at a temperature of 600 to 800 ° C. under a nitrogen atmosphere in a rapid thermal process (RTP) or an electric furnace. At this time, the first Ru layer 57 of high density has no surface change in the heat treatment process, but the second Ru layer 59 of low density porous has agglomeration phenomenon (A). The surface of the second Ru layer 59 is bumpy (A) without breaking the continuity of the film by the first Ru layer 57 due to the agglomeration phenomenon (A). Effective area is increased.
도 2e를 참조하면, 상기 하부전극 상에 Ta2O5박막의 유전막(61) 그리고 상부전극(63)을 순차적으로 형성한다.Referring to FIG. 2E, the dielectric layer 61 and the upper electrode 63 of the Ta 2 O 5 thin film are sequentially formed on the lower electrode.
본 발명의 캐패시터의 제조 방법은 요(凹) 구조의 캐패시터의 제조 방법에 있어서, 요(凹) 구조의 캐패시터의 제조 방법에 있어서, 캐패시터 콘택홀에 평평한 표면을 갖는 제 1 Ru층과 울퉁불퉁한 표면을 갖는 제 2 Ru층의 적층 구조를 포함하여 하부전극을 형성하므로, 상기 하부전극의 유효 면적 증가로 캐패시턴스가 증가되므로 0.10㎛ 이하의 설계가 가능하여 소자의 특성 및 집적도를 향상시키는 효과가 있다.The manufacturing method of the capacitor of this invention is a manufacturing method of the capacitor of a yaw structure WHEREIN: The manufacturing method of the capacitor of a yaw structure WHEREIN: The 1st Ru layer which has a flat surface in a capacitor contact hole, and a bumpy surface Since the lower electrode is formed, including the stacked structure of the second Ru layer, the capacitance is increased by increasing the effective area of the lower electrode, so that a design of 0.10 μm or less is possible, thereby improving the characteristics and integration of the device.
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