KR20030043409A - Memory system including memory module with dual data channels - Google Patents

Abstract

PURPOSE: A memory system including a memory module having two data channels is provided to effectively increase a bandwidth by including two data channels in one memory module, and to increase spare space for designing the memory module by including a signal reflection preventing part to the outside of the memory module. CONSTITUTION: The memory system(20) includes a memory controller(21), a channel(CH3), memory modules(23,25), and a terminal resistor(RT) connecting to the terminal voltage(VT). The memory module(23) includes Rambus DRAMs. The memory module(25) includes a memory module including Rambus DRAMs or a continuing module not including Rambus DRAMs. The memory controller(21) inputs/outputs the data to the Rambus DRAM included in the memory modules(23,25) through the channel(CH3). The terminal resistor(RT) applying the terminal voltage(VT) to one end is connected to the terminal of the channel(CH3) in order to prevent the signal reflection. The signal reflection part is installed on a motherboard including the memory system(20).

Description

Memory system including memory module with dual data channels

The present invention relates to a memory system, and more particularly to a memory system including a rim (Rambus Inline Memory Module).

Rambus DRAM is a memory capable of high-speed data transfer. It is a DRAM that can input / output two pieces of data per unit clock signal in synchronization with the rising edge and the falling edge of the clock signal. . When the Rambus DRAM is used in a system, it is used as a memory module. A memory module is a set of devices having a single function, and a plurality of semiconductor devices interconnected on a printed circuit board (PCB) are mounted. is produced by mounting. The Rambus Inline Memory Module (RIMM) refers to a memory module in which interconnected Rambus DRAMs are mounted on a printed circuit board.

1 is a diagram illustrating a memory system including a conventional Rambus in-line memory module. Referring to FIG. 1, a memory system 10 having conventional dual channels includes a memory controller 11, dual channels CH1 and CH2, and memory modules 12, 13, and 14. 15 and a signal reflection preventing unit 16 are provided. The signal reflection prevention unit 16 is installed independently of the printed circuit board of the system in which the memory modules are installed.

Each of the memory modules 12 and 14 includes Rambus DRAMs (not shown) connected through the channels CH1 and CH2. Each of the memory modules 13 and 15 may be a memory module including Rambus DRAMs or a connecting module not including Rambus DRAMs.

The signal reflection prevention unit 16 includes a termination resistor RT to which an end voltage VT is applied at one end, and the termination resistor RT to which the termination voltage VT is applied to the channels CH1 and CH2. It serves to prevent the reflection of the transmitted signal.

The memory controller 11 controls data to be input / output to Rambus DRAMs included in the memory modules 12, 13, 14, and 15 through channels CH1 and CH2.

For example, the conventional memory system 10 may output 16 data through the first channel CH1 and 16 data through the second channel CH2 to output 32 data in total. Memory system.

FIG. 2 is a diagram illustrating in detail the Rambus in-line memory module 12 of FIG. 1. 2, a plurality of Rambus DRAMs RD are disposed on both sides of a printed circuit board PCB. The channel transmitting the serial initialization signal SIO is a channel passing through the Rambus DRAM RD. The channel for transmitting the data signal DATA and the command signal CMD is connected in parallel to the Rambus DRAM RD. The serial initialization signal SIO is a signal stored in a register installed inside the Rambus DRAM RD, and is a signal indicating information such as a location of a Rambus DRAM included in a Rambus in-line memory module.

However, the memory system 10 according to the related art needs to include a multi channel in order to increase the bandwidth and requires one or more Rambus in-line memory modules per one channel of the multi channels. There is a problem.

Accordingly, an object of the present invention is to provide a memory system including at least one memory module having two data channels in order to solve the above problem.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating a memory system including a conventional Rambus in-line memory module.

FIG. 2 is a diagram illustrating in detail the Rambus in-line memory module of FIG. 1.

3 is a diagram illustrating a memory system according to an exemplary embodiment of the present invention.

FIG. 4 is a diagram illustrating in detail the Rambus in-line memory DRAM of FIG. 3.

In order to achieve the above technical problem, a memory system of the present invention includes at least one memory module, a memory controller for controlling data input / output through a channel to the memory module, and a signal reflection prevention part connected to the channel end. Each of the memory devices included in one surface of the memory module and the memory devices included in the other surface of the memory module may independently include a channel for transmitting the data.

According to a preferred embodiment, each of the memory devices receives the location information indicating the location of each of the memory devices from the memory controller through the channel, and then receives the same location information among the memory devices to which the location information is given. Memory devices that have them operate simultaneously.

According to a preferred embodiment, each of the memory devices is a Rambus DRAM, and the signal reflection prevention portion is independently installed on a printed circuit board of a system in which the memory module is installed.

The memory system of the present invention can effectively increase bandwidth by including two data channels in one memory module. In addition, since only a small number of memory modules can be used when upgrading the memory system of the present invention, it is advantageous in terms of memory granularity. In addition, the memory system of the present invention may increase the free space for designing the memory module by including a signal reflection prevention unit outside the memory module.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a diagram illustrating a memory system according to an exemplary embodiment of the present invention. Referring to FIG. 3, the memory system 20 of the present invention has a termination resistor RT connected to a memory controller 21, a channel CH3, memory modules 23 and 25, and a termination voltage VT. It is provided. The memory module 23 includes interconnected Rambus DRAMs (not shown). The memory module 25 may be a memory module including rambus DRAMs or a connecting module not including rambus DRAMs.

The memory controller 21 controls data to be input / output to the Rambus DRAM included in the memory modules 23 and 25 through the channel CH3.

In order to prevent the signal from being reflected at the end of the channel CH3, a terminal resistor RT to which an end voltage VT is applied is connected at one end to serve as a signal reflection prevention part. The signal antireflection is located on a mother-board that includes the memory system 20 of the present invention. Therefore, the memory system 20 of the present invention increases the free space for designing the memory module.

Since one memory module included in the memory system 20 of the present invention has two data channels, the memory system 20 of the present invention is implemented as a dual channel memory system. Therefore, compared with the conventional memory system 10 that outputs 32 data, the memory system 20 of the present invention has an advantage of outputting 32 data using only one memory module.

FIG. 4 is a diagram illustrating in detail the Rambus in-line memory module of FIG. 3. Referring to FIG. 4, a plurality of Rambus DRAMs RD1, RD2, RD3, RD4,... Are disposed on both sides of a printed circuit board PCB. The channel transmitting the serial initialization signal SIO is a channel passing through each of the Rambus DRAMs RD1, RD2, RD3, RD4, .... The channel for transmitting the data signal DATA and the command signal CMD is connected in parallel to each of the Rambus DRAMs RD1, RD2, RD3, RD4, .... The serial initialization signal SIO is a signal stored in a register installed inside the rambus DRAM and indicates information such as a position of a rambus DRAM included in the rambus in-line memory module 23.

For example, when the memory system 20 of the present invention outputs 32 data, Rambus DRAMs [RD1, RD2] or [RD3, RD4] recognized as the same position by the serial initialization signal SIO. ) (Eg, RD1) outputs 16 data. Therefore, since 32 pieces of data are output in total, the memory system of the present invention has an advantage that a dual channel memory system can be implemented while having only one Rambus in-line memory module. In addition, by implementing a multi-channel memory system using the Rambus in-line memory module included in the present invention, the bandwidth can be effectively increased.

In order for the Rambus DRAMs [RD1, RD2] or [RD3, RD4] to be recognized as the same location, the Rambus DRAMs [RD1, RD2] or [RD3, RD4] are based on the printed circuit board PCB. The signal paths connected to Rambus DRAMs [RD1, RD2] or [RD3, RD4] are also symmetrically arranged. Each of the Rambus DRAMs [RD1, RD2] or [RD3, RD4] recognized as the same location has the same register information and the same address value to operate simultaneously.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The memory system of the present invention can effectively increase bandwidth by including two data channels in one memory module. In addition, since only a small number of memory modules can be used when upgrading the memory system of the present invention, it is advantageous in terms of memory granularity. In addition, the memory system of the present invention may increase the free space for designing the memory module by including a signal reflection prevention unit outside the memory module.

Claims (4)

At least one memory module; A memory controller for controlling data to be input / output through a channel to the memory module; And A signal reflection prevention part connected to the channel end; And each of the memory devices included in one surface of the memory module and the memory devices included in the other surface of the memory module independently include a channel for transmitting the data. The method of claim 1, After each of the memory devices is provided with location information indicating the location of each of the memory devices from the memory controller through the channel, the memory devices having the same location information among the memory devices to which the location information has been provided operate simultaneously. Memory system, characterized in that. The method of claim 2, Each of the memory devices is a Rambus DRAM. The method of claim 3, And the signal reflection prevention unit is independently installed on a printed circuit board of a system in which the memory module is installed.